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1. 发明申请

US20090240922A1 METHOD, SYSTEM, COMPUTER PROGRAM PRODUCT, AND HARDWARE PRODUCT FOR IMPLEMENTING RESULT FORWARDING BETWEEN DIFFERENTLY SIZED OPERANDS IN A SUPERSCALAR PROCESSOR 失效
标题翻译：方法，系统，计算机程序产品和用于在超级处理器中执行不同尺寸操作之前的结果的硬件产品
公开(公告)号：US20090240922A1
公开(公告)日：2009-09-24
申请号：US12051792
申请日：2008-03-19
申请人： David S. Hutton , Fadi Y. Busaba , Bruce C. Giamei , Christopher A. Krygowski , Edward T. Malley , Jeffrey S. Plate , John G. Rell, JR. , Chung-Lung Kevin Shum , Timothy J. Slegel
发明人： David S. Hutton , Fadi Y. Busaba , Bruce C. Giamei , Christopher A. Krygowski , Edward T. Malley , Jeffrey S. Plate , John G. Rell, JR. , Chung-Lung Kevin Shum , Timothy J. Slegel
IPC分类号： G06F9/30
CPC分类号： G06F9/3016 , G06F9/30036 , G06F9/3828
摘要： Result and operand forwarding is provided between differently sized operands in a superscalar processor by grouping a first set of instructions for operand forwarding, and grouping a second set of instructions for result forwarding, the first set of instructions comprising a first source instruction having a first operand and a first dependent instruction having a second operand, the first dependent instruction depending from the first source instruction; the second set of instructions comprising a second source instruction having a third operand and a second dependent instruction having a fourth operand, the second dependent instruction depending from the second source instruction, performing operand forwarding by forwarding the first operand, either whole or in part, as it is being read to the first dependent instruction prior to execution; performing result forwarding by forwarding a result of the second source instruction, either whole or in part, to the second dependent instruction, after execution; wherein the operand forwarding is performed by executing the first source instruction together with the first dependent instruction; and wherein the result forwarding is performed by executing the second source instruction together with the second dependent instruction.
摘要翻译：通过对用于操作数转发的第一组指令进行分组，以及对用于结果转发的第二组指令进行分组，在超标量处理器中的不同大小的操作数之间提供结果和操作数转发，所述第一组指令包括具有第一操作数的第一源指令以及具有第二操作数的第一依赖指令，所述第一依赖指令取决于所述第一源指令; 所述第二组指令包括具有第三操作数和第二从属指令的第二源指令，所述第三操作数和第二从属指令具有第四操作数，所述第二依赖指令取决于所述第二源指令，通过转发所述第一操作数全部或部分地执行操作数转发，因为它在执行之前被读取到第一个依赖指令; 执行结果转发，将第二源指令的结果全部或部分转发到第二依赖指令; 其中通过与第一依赖指令一起执行第一源指令来执行操作数转发; 并且其中通过与第二从属指令一起执行第二源指令来执行结果转发。

2. 发明授权

US07921279B2 Operand and result forwarding between differently sized operands in a superscalar processor 失效
标题翻译：操作数和结果在超标量处理器中的不同大小的操作数之间转发
公开(公告)号：US07921279B2
公开(公告)日：2011-04-05
申请号：US12051792
申请日：2008-03-19
申请人： David S. Hutton , Fadi Y. Busaba , Bruce C. Giamei , Christopher A. Krygowski , Edward T. Malley , Jeffrey S. Plate , John G. Rell, Jr. , Chung-Lung Kevin Shum , Timothy J. Slegel
发明人： David S. Hutton , Fadi Y. Busaba , Bruce C. Giamei , Christopher A. Krygowski , Edward T. Malley , Jeffrey S. Plate , John G. Rell, Jr. , Chung-Lung Kevin Shum , Timothy J. Slegel
IPC分类号： G06F9/30
CPC分类号： G06F9/3016 , G06F9/30036 , G06F9/3828
摘要： Result and operand forwarding is provided between differently sized operands in a superscalar processor by grouping a first set of instructions for operand forwarding, and grouping a second set of instructions for result forwarding, the first set of instructions comprising a first source instruction having a first operand and a first dependent instruction having a second operand, the first dependent instruction depending from the first source instruction; the second set of instructions comprising a second source instruction having a third operand and a second dependent instruction having a fourth operand, the second dependent instruction depending from the second source instruction, performing operand forwarding by forwarding the first operand, either whole or in part, as it is being read to the first dependent instruction prior to execution; performing result forwarding by forwarding a result of the second source instruction, either whole or in part, to the second dependent instruction, after execution; wherein the operand forwarding is performed by executing the first source instruction together with the first dependent instruction; and wherein the result forwarding is performed by executing the second source instruction together with the second dependent instruction.
摘要翻译：通过对用于操作数转发的第一组指令进行分组，以及对用于结果转发的第二组指令进行分组，在超标量处理器中的不同大小的操作数之间提供结果和操作数转发，所述第一组指令包括具有第一操作数的第一源指令以及具有第二操作数的第一依赖指令，所述第一依赖指令取决于所述第一源指令; 所述第二组指令包括具有第三操作数和第二从属指令的第二源指令，所述第三操作数和第二从属指令具有第四操作数，所述第二依赖指令取决于所述第二源指令，通过转发所述第一操作数全部或部分地执行操作数转发，因为它在执行之前被读取到第一个依赖指令; 执行结果转发，将第二源指令的结果全部或部分转发到第二依赖指令; 其中通过与第一依赖指令一起执行第一源指令来执行操作数转发; 并且其中通过与第二从属指令一起执行第二源指令来执行结果转发。

3. 发明授权

US07913067B2 Method and system for overlapping execution of instructions through non-uniform execution pipelines in an in-order processor 失效
标题翻译：用于通过按顺序处理器中的非均匀执行流水线重复执行指令的方法和系统
公开(公告)号：US07913067B2
公开(公告)日：2011-03-22
申请号：US12034084
申请日：2008-02-20
申请人： David S. Hutton , Khary J. Alexander , Fadi Y. Busaba , Bruce C. Giamei , John G. Rell, Jr. , Eric M. Schwarz , Chung-Lung Kevin Shum
发明人： David S. Hutton , Khary J. Alexander , Fadi Y. Busaba , Bruce C. Giamei , John G. Rell, Jr. , Eric M. Schwarz , Chung-Lung Kevin Shum
IPC分类号： G06F9/38
CPC分类号： G06F9/3836 , G06F9/3857 , G06F9/3873
摘要： A system and method for overlapping execution (OE) of instructions through non-uniform execution pipelines in an in-order processor are provided. The system includes a first execution unit to perform instruction execution in a first execution pipeline. The system also includes a second execution unit to perform instruction execution in a second execution pipeline, where the second execution pipeline includes a greater number of stages than the first execution pipeline. The system further includes an instruction dispatch unit (IDU), the IDU including OE registers and logic for dispatching an OE-capable instruction to the first execution unit such that the instruction completes execution prior to completing execution of a previously dispatched instruction to the second execution unit. The system additionally includes a latch to hold a result of the execution of the OE-capable instruction until after the second execution unit completes the execution of the previously dispatched instruction.
摘要翻译：提供了一种用于通过在顺序处理器中的非均匀执行管线来重复执行（OE）指令的系统和方法。该系统包括在第一执行流水线中执行指令执行的第一执行单元。该系统还包括第二执行单元，用于在第二执行流水线中执行指令执行，其中第二执行流水线包括比第一执行流水线更多的级数。该系统还包括一个指令调度单元（IDU），该IDU包括OE寄存器和用于向第一执行单元分配一个OE能力指令的逻辑，使得指令在完成先前发送的指令执行之前完成执行单元。该系统还包括一个锁存器，用于保持执行OE能力指令的结果，直到第二执行单元完成先前发送的指令的执行。

4. 发明申请

US20090210656A1 METHOD AND SYSTEM FOR OVERLAPPING EXECUTION OF INSTRUCTIONS THROUGH NON-UNIFORM EXECUTION PIPELINES IN AN IN-ORDER PROCESSOR 失效
标题翻译：通过非订单执行管理员在订单处理程序中执行指令的方法和系统
公开(公告)号：US20090210656A1
公开(公告)日：2009-08-20
申请号：US12034084
申请日：2008-02-20
申请人： David S. Hutton , Khary J. Alexander , Fadi Y. Busaba , Bruce C. Giamei , John G. Rell, JR. , Eric M. Schwarz , Chung-Lung Kevin Shum
发明人： David S. Hutton , Khary J. Alexander , Fadi Y. Busaba , Bruce C. Giamei , John G. Rell, JR. , Eric M. Schwarz , Chung-Lung Kevin Shum
IPC分类号： G06F15/76 , G06F9/02 , G06F9/312
CPC分类号： G06F9/3836 , G06F9/3857 , G06F9/3873
摘要： A system and method for overlapping execution (OE) of instructions through non-uniform execution pipelines in an in-order processor are provided. The system includes a first execution unit to perform instruction execution in a first execution pipeline. The system also includes a second execution unit to perform instruction execution in a second execution pipeline, where the second execution pipeline includes a greater number of stages than the first execution pipeline. The system further includes an instruction dispatch unit (IDU), the IDU including OE registers and logic for dispatching an OE-capable instruction to the first execution unit such that the instruction completes execution prior to completing execution of a previously dispatched instruction to the second execution unit. The system additionally includes a latch to hold a result of the execution of the OE-capable instruction until after the second execution unit completes the execution of the previously dispatched instruction.
摘要翻译：提供了一种用于通过在顺序处理器中的非均匀执行管线来重复执行（OE）指令的系统和方法。该系统包括在第一执行流水线中执行指令执行的第一执行单元。该系统还包括第二执行单元，用于在第二执行流水线中执行指令执行，其中第二执行流水线包括比第一执行流水线更多的级数。该系统还包括一个指令调度单元（IDU），该IDU包括OE寄存器和用于向第一执行单元分配一个OE能力指令的逻辑，使得指令在完成先前发送的指令执行之前完成执行单元。该系统还包括一个锁存器，用于保持执行OE能力指令的结果，直到第二执行单元完成先前发送的指令的执行。

5. 发明授权

US07861064B2 Method, system, and computer program product for selectively accelerating early instruction processing 失效
标题翻译：方法，系统和计算机程序产品，用于选择性加速早期指令处理
公开(公告)号：US07861064B2
公开(公告)日：2010-12-28
申请号：US12037861
申请日：2008-02-26
申请人： Khary J. Alexander , Fadi Y. Busaba , Bruce C. Giamei , David S. Hutton , Chung-Lung Kevin Shum
发明人： Khary J. Alexander , Fadi Y. Busaba , Bruce C. Giamei , David S. Hutton , Chung-Lung Kevin Shum
IPC分类号： G06F9/34 , G06F9/38
CPC分类号： G06F9/3826 , G06F9/3836
摘要： A method for selectively accelerating early instruction processing including receiving an instruction data that is normally processed in an execution stage of a processor pipeline, wherein a configuration of the instruction data allows a processing of the instruction data to be accelerated from the execution stage to an address generation stage that occurs earlier in the processor pipeline than the execution stage, determining whether the instruction data can be dispatched to the address generation stage to be processed without being delayed due to an unavailability of a processing resource needed for the processing of the instruction data in the address generation stage, dispatching the instruction data to be processed in the address generation stage if it can be dispatched without being delayed due to the unavailability of the processing resource, and dispatching the instruction data to be processed in the execution stage if it can not be dispatched without being delayed due to the unavailability of the processing resource, wherein the processing of the instruction data is selectively accelerated using an address generation interlock scheme. A corresponding system and computer program product.
摘要翻译：一种用于选择性地加速早期指令处理的方法，包括接收在处理器流水线的执行阶段中正常处理的指令数据，其中指令数据的配置允许指令数据的处理从执行阶段加速到地址在处理器流水线中比执行阶段更早发生的生成阶段，确定指令数据是否可以被分派到要处理的地址生成阶段，而不会由于处理指令数据所需的处理资源的不可用而被延迟地址生成阶段，如果能够由于处理资源的不可用而被分派而不被延迟，则在地址生成阶段调度要处理的指令数据，并且如果不能在执行阶段调度要处理的指令数据由于你而不被推迟处理资源的可用性，其中使用地址生成互锁方案选择性地加速指令数据的处理。相应的系统和计算机程序产品。

6. 发明申请

US20090217009A1 SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR TRANSLATING STORAGE ELEMENTS 有权
标题翻译：用于转储储存元件的系统，方法和计算机程序产品
公开(公告)号：US20090217009A1
公开(公告)日：2009-08-27
申请号：US12036520
申请日：2008-02-25
申请人： Chung-Lung Kevin Shum , Fadi Y. Busaba , Mark S. Farrell , Bruce C. Giamei , Bernd Nerz , David A. Schroter , Charles F. Webb
发明人： Chung-Lung Kevin Shum , Fadi Y. Busaba , Mark S. Farrell , Bruce C. Giamei , Bernd Nerz , David A. Schroter , Charles F. Webb
IPC分类号： G06F9/318
CPC分类号： G06F9/3017 , G06F9/30018 , G06F9/30101 , G06F9/355
摘要： A system, method and computer program product for translations in a computer system. The system includes a general purpose register containing a base address of an address translation table. The system also includes a millicode accessible special displacement register configured to receive a plurality of elements to be translated. The system further includes a multiplexer for selecting a particular one of the plurality of elements from the millicode accessible special displacement register and for generating a displacement or offset value. The system further includes an address generator for creating a combined address containing the base address from the general purpose register and the generated displacement or offset value.
摘要翻译：一种用于计算机系统中的翻译的系统，方法和计算机程序产品。该系统包括包含地址转换表的基地址的通用寄存器。该系统还包括被配置为接收多个要被翻译的元件的毫代可访问特殊位移寄存器。该系统还包括多路复用器，用于从毫代可访问特殊位移寄存器中选择多个元件中的特定元件，并用于产生位移或偏移值。该系统还包括地址发生器，用于创建包含来自通用寄存器的基地址和所生成的位移或偏移值的组合地址。

7. 发明申请

US20130339666A1 SPECIAL CASE REGISTER UPDATE WITHOUT EXECUTION 审中-公开
公开(公告)号：US20130339666A1
公开(公告)日：2013-12-19
申请号：US13524471
申请日：2012-06-15
申请人： Gregory W. Alexander , Brian D. Barrick , Fadi Y. Busaba , Bruce C. Giamei , Edward T. Malley , Chung-Lung K. Shum
发明人： Gregory W. Alexander , Brian D. Barrick , Fadi Y. Busaba , Bruce C. Giamei , Edward T. Malley , Chung-Lung K. Shum
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/30043 , G06F9/3017 , G06F9/384
摘要： A method of changing a value of associated with a logical address in a computing device. The method includes: receiving an instruction at an instruction decoder, the instruction including a target register expressed as a logical value; determining at an instruction decoder that a result of the instruction is to set the target register to a constant value, the target register being in a physical register file associated with an execution unit; and mapping, in a register mapper, the logical address to a location represented by a special register tag.

8. 发明授权

US08078843B2 Facilitating processing in a computing environment using an extended drain instruction 有权
标题翻译：在计算环境中利用扩展的漏极指令促进处理
公开(公告)号：US08078843B2
公开(公告)日：2011-12-13
申请号：US12023155
申请日：2008-01-31
申请人： Khary J. Alexander , Fadi Y. Busaba , Mark S. Farrell , Bruce C. Giamei , Timothy J. Slegel , Charles F. Webb
发明人： Khary J. Alexander , Fadi Y. Busaba , Mark S. Farrell , Bruce C. Giamei , Timothy J. Slegel , Charles F. Webb
IPC分类号： G06F9/30
CPC分类号： G06F9/30079 , G06F9/30145 , G06F9/3867
摘要： An extended DRAIN instruction is used to stall processing within a computing environment. The instruction includes an indication of the one or more processing stages at which processing is to be stalled. It also includes a control that allows processing to be stalled for additional cycles, as desired. The enhanced DRAIN instruction enables its use to be more granular and to have minimal impact with respect to each individual use.
摘要翻译：扩展DRAIN指令用于在计算环境中停止处理。该指令包括处理被停止的一个或多个处理阶段的指示。它还包括一个控制，允许根据需要使处理停滞在额外的周期。增强的DRAIN指令使其使用更细致，对每个用户的影响最小。

9. 发明申请

US20090198980A1 FACILITATING PROCESSING IN A COMPUTING ENVIRONMENT USING AN EXTENDED DRAIN INSTRUCTION 有权
标题翻译：使用更多的排水指令在计算环境中实现加工
公开(公告)号：US20090198980A1
公开(公告)日：2009-08-06
申请号：US12023155
申请日：2008-01-31
申请人： Khary J. Alexander , Fadi Y. Busaba , Mark S. Farrell , Bruce C. Giamei , Timothy J. Slegel , Charles F. Webb
发明人： Khary J. Alexander , Fadi Y. Busaba , Mark S. Farrell , Bruce C. Giamei , Timothy J. Slegel , Charles F. Webb
IPC分类号： G06F9/30
CPC分类号： G06F9/30079 , G06F9/30145 , G06F9/3867
摘要： An extended DRAIN instruction is used to stall processing within a computing environment. The instruction includes an indication of the one or more processing stages at which processing is to be stalled. It also includes a control that allows processing to be stalled for additional cycles, as desired.
摘要翻译：扩展DRAIN指令用于在计算环境中停止处理。该指令包括处理被停止的一个或多个处理阶段的指示。它还包括一个控制，允许根据需要使处理停滞在额外的周期。

10. 发明授权

US08407453B2 Facilitating processing in a computing environment using an extended drain instruction 有权
标题翻译：在计算环境中利用扩展的漏极指令促进处理
公开(公告)号：US08407453B2
公开(公告)日：2013-03-26
申请号：US13273320
申请日：2011-10-14
申请人： Khary J. Alexander , Fadi Y. Busaba , Mark S. Farrell , Bruce C. Giamei , Timothy J. Slegel , Charles F. Webb
发明人： Khary J. Alexander , Fadi Y. Busaba , Mark S. Farrell , Bruce C. Giamei , Timothy J. Slegel , Charles F. Webb
IPC分类号： G06F9/30
CPC分类号： G06F9/30079 , G06F9/30145 , G06F9/3867
摘要： Processing within a computing environment is facilitated using an extended DRAIN instruction. An extended DRAIN instruction is used to stall processing within a computing environment. The instruction includes an indication of the one or more processing stages at which processing is to be stalled. It also includes a control that allows processing to be stalled for additional cycles, as desired.
摘要翻译：使用扩展DRAIN指令便于计算环境内的处理。扩展DRAIN指令用于在计算环境中停止处理。该指令包括处理被停止的一个或多个处理阶段的指示。它还包括一个控制，允许根据需要使处理停滞在额外的周期。

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