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1. 发明专利

JPH09153583A METHOD FOR CONNECTING LEAD PIN TO SEMICONDUCTOR COMPONENT 失效
公开(公告)号：JPH09153583A
公开(公告)日：1997-06-10
申请号：JP33567795
申请日：1995-12-01
申请人： FURUKAWA ELECTRIC CO LTD , FUJITSU LTD
发明人： ZAMA SATORU , YUZAWA HITOSHI , NAKAGAWA SUSUMU , SUZUKI TAKUYA , MIZUKOSHI MASATAKA
IPC分类号： H01L23/12 , H01L23/50
摘要： PROBLEM TO BE SOLVED: To accurately align a lead pin without being affected by thermal expansion of a heat holder and surely connect the electrode of a semiconductor component with the lead pin by removing the pin holder prior to the connecting process of the lead pin. SOLUTION: Lead pins 2 for a semiconductor component are held to a pin holder 1, which is formed of silicon rubber sheet, in the prescribed arrangement. Then, the lead pins 2 held by the pin holder 1 are mounted on an alignment jig 5 to be aligned, and the pin holder 1 is removed under the condition that the lead pins 2 are mounted by the aligning jig 5. Then, the lead pin 2 is connected to the electrode 7a of a semiconductor component 7 under the condition that the lead pins 2 are mounted by the alignment jig 5.

2. 发明专利

DE3479271D1 WIRE BONDING METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE PRODUCED BY THIS METHOD 未知
公开(公告)号：DE3479271D1
公开(公告)日：1989-09-07
申请号：DE3479271
申请日：1984-04-19
申请人： FUJITSU LTD
发明人： MIZUKOSHI MASATAKA , ENDO TEIICHI
IPC分类号： H01L21/60 , H01L23/49 , H01L23/498 , H01L23/48
摘要： A semiconductor device comprising a semiconductor chip (10), a package (20) for housing the semiconductor chip, and wires (3a, 3b) for bonding one of a plurality of electrodes (1) formed on the semiconductor chip and one of a plurality of electrodes (2) formed on the package. Each of the wires (3a, 3b) has a portion rising at a steep angle with respect to one of the electrodes to be bonded and a portion descending at a gentle angle with respect to the other of the electrodes to be bonded. The rising portion and the descending portion of each wire are disposed in reverse positions with respect to the rising portion and the descending portion of the adjacent wires.

3. 发明公开

EP2384102A4 ELECTRONIC COMPONENT AND METHOD FOR MANUFACTURING SAME 审中-公开
标题翻译：电子元件及其制造方法
公开(公告)号：EP2384102A4
公开(公告)日：2012-08-08
申请号：EP09834606
申请日：2009-10-15
申请人： FUJITSU LTD
发明人： MIZUKOSHI MASATAKA , ISHIZUKI YOSHIKATSU
IPC分类号： H05K3/20 , H05K3/46
CPC分类号： H05K3/20 , H01L24/16 , H01L24/32 , H01L24/81 , H01L24/83 , H01L2224/10175 , H01L2224/131 , H01L2224/16237 , H01L2224/29111 , H01L2224/2919 , H01L2224/32225 , H01L2224/73204 , H01L2224/81001 , H01L2224/81191 , H01L2224/81192 , H01L2224/81193 , H01L2224/83193 , H01L2224/838 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/0665 , H01L2924/12042 , H01L2924/1517 , H01L2924/15788 , H01L2924/1579 , H05K1/142 , H05K3/4658 , H05K3/4694 , H05K2201/0108 , H05K2201/0352 , H05K2201/09972 , H05K2203/025 , H05K2203/1189 , Y10T29/49117 , Y10T156/1052 , Y10T428/24917 , H01L2924/00 , H01L2924/01047 , H01L2924/01083 , H01L2924/3512 , H01L2924/00014 , H01L2224/16225
摘要： [Problems] In an electronic component and a method of manufacturing the same, forming a finer conductive pattern than conventional counterpart [Means of Solving] A method of manufacturing an electronic component includes the steps of forming a resin layer over an underlying layer, pressing a conductor plate including a pattern formed on one major surface thereof against the resin layer, and embedding the pattern in the resin layer, and performing polishing, Chemical Mechanical Polishing, or cutting by the use of a diamond bit on another major surface of the conductor plate until the resin layer appears, and leaving the pattern in the resin layer as a conductor pattern.

4. 发明专利

JP2011211042A Electronic device 有权
标题翻译：电子设备
公开(公告)号：JP2011211042A
公开(公告)日：2011-10-20
申请号：JP2010078644
申请日：2010-03-30
申请人： Fujitsu Ltd , 富士通株式会社
发明人： AKAMATSU TOSHIYA , IMAIZUMI NOBUHIRO , MIZUKOSHI MASATAKA
IPC分类号： H01L21/60 , H01L23/12
CPC分类号： H01L2224/81897 , H01L2924/01019
摘要： PROBLEM TO BE SOLVED: To provide an electronic device that can obtain superior solder bonding without being affected by a shape before solder bonding.SOLUTION: The electronic device includes a first element 1; a columnar protrusion 5 formed on the first element 1 and in which an exposed surface is formed of an insulating material; and a plurality of first electrodes 3 formed around the columnar protrusion 5. The columnar protrusion 5 is set between a plurality of bump electrodes 14 formed on a second element 11 disposed opposite to the first element 1, and first electrodes 3 and bump electrodes 14 are connected via solder layers 4, 15.
摘要翻译：要解决的问题：提供一种能够在不受焊接之前的形状的影响的情况下获得优异的焊料接合的电子设备。解决方案：电子设备包括第一元件1; 形成在第一元件1上的柱状突起5，露出表面由绝缘材料形成; 以及形成在柱状突起5周围的多个第一电极3.柱状突起5设置在形成在与第一元件1相对设置的第二元件11上的多个突起电极14之间，第一电极3和凸块电极14 通过焊料层4,15连接。

5. 发明专利

JP2011204851A Loop-type heat pipe and electronic apparatus 有权
标题翻译：环型热管和电子设备
公开(公告)号：JP2011204851A
公开(公告)日：2011-10-13
申请号：JP2010069939
申请日：2010-03-25
申请人： Fujitsu Ltd , 富士通株式会社
发明人： OGATA SHIN , SHIOGA KENJI , AOKI SHIGENORI , UCHIDA HIROMOTO , MIZUKOSHI MASATAKA , NAGAOKA HIDEAKI
IPC分类号： H01L23/427 , F28D15/02 , H05K7/20
CPC分类号： F28D15/0266
摘要： PROBLEM TO BE SOLVED: To provide a loop-type heat pipe which is easy to promptly be started after heated.SOLUTION: The loop-type heat pipe has an evaporator 1 connected between a liquid pipe and a steam pipe where the evaporator 1 includes a porous body which makes a working fluid flowing in from the liquid pipe pass, a housing which houses the porous body therein, and forms a steam discharge portion which leads the working fluid evaporated by heat from a heating element together with the porous body, and a liquid-repellent portion 18 which has a liquid repellent property to the working liquid and is arranged between the housing and the porous body to be exposed to the steam discharging portion.
摘要翻译：要解决的问题：提供一种在加热后容易启动的环型热管。解决方案：环路式热管具有连接在液体管和蒸汽管之间的蒸发器1，蒸发器1包括使来自液体管道的工作流体流过的多孔体，容纳多孔体的壳体，形成蒸气排出部，该蒸汽排出部将与多孔体一起从加热元件的热量蒸发的工作流体引导，防液部分18，其对工作液体具有疏液性，并且布置在壳体和多孔体之间以暴露于蒸汽排放部分。

6. 发明专利

JP2010182904A Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：JP2010182904A
公开(公告)日：2010-08-19
申请号：JP2009025581
申请日：2009-02-06
申请人： Fujitsu Ltd , 富士通株式会社
发明人： AKABOSHI TOMOYUKI , ISHIZUKA TAKESHI , MIZUKOSHI MASATAKA
IPC分类号： H01L21/56 , H01L23/12
CPC分类号： H01L2224/48091 , H01L2224/48137 , H01L2924/00014
摘要： PROBLEM TO BE SOLVED: To manufacture a semiconductor device that is manufactured through small number of processes, is low-cost and has high mechanical strength, and secures insulation to have high connection reliability. SOLUTION: The semiconductor device in which semiconductor elements are laminated is obtained by the method of manufacturing the semiconductor device. The method comprises: a first cutting process (S1) of cutting a semiconductor substrate into the plurality of semiconductor elements which are partitioned off with a first cutting groove and each of which has an electrode on a principal surface; a process (S2) of wiring-connecting electrodes of adjacent semiconductor elements across the first cutting groove; a process (S3) of sealing the semiconductor elements with a resin so as to cover interconnects; and a second cutting process (S4) of forming a second cutting groove for re-dividing the semiconductor elements by cutting the sealed interconnects along the first cutting groove to expose cut surfaces of the interconnects. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了制造通过少量工艺制造的半导体器件，其成本低廉并且具有高机械强度，并且确保绝缘性以具有高连接可靠性。解决方案：通过半导体器件的制造方法获得半导体元件层叠的半导体器件。该方法包括：将半导体衬底切割成多个半导体元件的第一切割工艺（S1），所述多个半导体元件用第一切割槽分隔，并且每个半导体元件在主表面上具有电极; 将所述第一切割槽的相邻半导体元件的电极配线连接的工序（S2）用树脂密封半导体元件以覆盖互连的工艺（S3）; 以及第二切割工艺（S4），其形成用于通过沿着所述第一切割槽切割所述密封互连件来重新分割所述半导体元件的第二切割槽，以暴露所述互连件的切割表面。版权所有（C）2010，JPO＆INPIT

7. 发明专利

JP2009123941A Electronic component and its manufacturing method 有权
标题翻译：电子元件及其制造方法
公开(公告)号：JP2009123941A
公开(公告)日：2009-06-04
申请号：JP2007296600
申请日：2007-11-15
申请人： Fujitsu Ltd , 富士通株式会社
发明人： SHIMIZU KOZO , MIZUKOSHI MASATAKA
IPC分类号： H01L21/60
CPC分类号： H01L23/373 , H01L2224/16225
摘要： PROBLEM TO BE SOLVED: To provide an electronic component which mounts a packaged semiconductor chip on a mounting board and which can easily remove a semiconductor chip being found to have initial failure. SOLUTION: A first pad (2) is formed on the surface of a first substrate (1). A metal film (3) is arranged on the surface of the first pad (2). A second substrate (6) is so arranged that it is opposed to the surface of the first substrate (1) on which the first pad (2) is formed. A second pad (7) is formed on the surface of the second substrate (6) which is opposed to the first pad (2). Ends of one side of conductive nanotubes (8) are connected with the second pad (7) and their ends of the other side are embedded in the metal film (3). An intermediate film (9) which is made of a conductive compound including at least one constituent element of the nanotubes (8) and at least one constituent element of the first pad (1) is arranged at the interface between the metal film (3) and the nanotubes (8). COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种将封装的半导体芯片安装在安装板上并可容易地去除被发现具有初始故障的半导体芯片的电子部件。解决方案：在第一基板（1）的表面上形成第一焊盘（2）。金属膜（3）设置在第一焊盘（2）的表面上。第二基板（6）被布置成使得其与形成有第一焊盘（2）的第一基板（1）的表面相对。第二衬垫（7）形成在与第一衬垫（2）相对的第二衬底（6）的表面上。导电性纳米管（8）的一侧的端部与第二焊盘（7）连接，另一侧的端部嵌入金属膜（3）中。由包括纳米管（8）的至少一个构成元件和第一焊盘（1）的至少一个构成元件的导电化合物制成的中间膜（9）设置在金属膜（3）和纳米管（8）。版权所有（C）2009，JPO＆INPIT

8. 发明专利

JP2009094545A Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：JP2009094545A
公开(公告)日：2009-04-30
申请号：JP2009022023
申请日：2009-02-02
申请人： Fujitsu Ltd , 富士通株式会社
发明人： MIZUKOSHI MASATAKA , ISHIZUKI YOSHIKATSU , NAKAGAWA KANAE , OKAMOTO KEISHIRO , TESHIROGI KAZUO , SAKAI TAIJI
IPC分类号： H01L25/065 , H01L21/48 , H01L21/60 , H01L25/07 , H01L25/18
CPC分类号： H01L24/83 , H01L21/4853 , H01L24/11 , H01L24/29 , H01L24/45 , H01L2224/1134 , H01L2224/1184 , H01L2224/13099 , H01L2224/13144 , H01L2224/13147 , H01L2224/16145 , H01L2224/29298 , H01L2224/45015 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/73104 , H01L2224/749 , H01L2224/75 , H01L2224/75252 , H01L2224/83191 , H01L2224/838 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01023 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01039 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/0781 , H01L2924/15788 , H01L2924/3025 , H01L2924/00014 , H01L2924/00 , H01L2224/29099
摘要： PROBLEM TO BE SOLVED: To planarize surfaces of fine bumps formed on a substrate inexpensively and at high speed, and to easily and reliably connect bumps with each other without causing inconvenience such as dishing.
SOLUTION: A plurality of first bumps are formed on the surface of a first substrate, and a first insulating film is formed between the plurality of the first bumps. Planarization is performed by cutting using a byte so that the surfaces of the plurality of first bumps and the surface of the first insulating film become continuously planarized. A plurality of second bumps are formed on the surface of a second substrate, and a second insulating film is formed between the plurality of second bumps. The planarization is performed by cutting using the byte so that the surfaces of the plurality of second bumps and the surface of the second insulating film become continuously planarized. Then, the plurality of first bumps and the plurality of second bumps, and the first insulating film and the second insulating film are opposed to each other and connected with each other.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：以低成本且高速度平坦化形成在基板上的微细凸块的表面，并且容易且可靠地将凸块彼此连接，而不会产生诸如凹陷的不便。解决方案：在第一基板的表面上形成多个第一凸块，并且在多个第一凸块之间形成第一绝缘膜。通过使用字节进行切割来进行平面化，使得多个第一凸块的表面和第一绝缘膜的表面变得连续平坦化。在第二基板的表面上形成多个第二凸块，并且在多个第二凸块之间形成第二绝缘膜。通过使用字节进行切割来进行平坦化，使得多个第二凸块的表面和第二绝缘膜的表面连续地平坦化。然后，多个第一凸块和多个第二凸块以及第一绝缘膜和第二绝缘膜彼此相对并彼此连接。版权所有（C）2009，JPO＆INPIT

9. 发明专利

JP2008084933A Interposer and manufacturing method thereof 有权
标题翻译：其制造方法及其制造方法
公开(公告)号：JP2008084933A
公开(公告)日：2008-04-10
申请号：JP2006260548
申请日：2006-09-26
申请人： Fujitsu Ltd , 富士通株式会社
发明人： SHIOGA KENJI , KURIHARA KAZUAKI , NAKAGAWA KANAE , SAKAI TAIJI , MIZUKOSHI MASATAKA
IPC分类号： H01L23/12
CPC分类号： H05K1/162 , H01L21/486 , H01L23/15 , H01L23/498 , H01L23/49827 , H01L23/50 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2224/16235 , H01L2924/00014 , H01L2924/01019 , H01L2924/01046 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/15311 , H01L2924/3011 , H05K1/0306 , H05K1/112 , H05K3/4605 , H05K2201/0179 , H05K2201/09509 , H05K2201/096 , H05K2201/09627 , H05K2201/10378 , Y10T29/49002 , Y10T29/49128 , Y10T29/4913 , Y10T29/49144 , Y10T29/49155 , Y10T29/49156 , H01L2224/05599
摘要： PROBLEM TO BE SOLVED: To provide an inexpensive interposer having a thin-film capacitor having very high capacitance. SOLUTION: The interposer has a glass substrate 46 having a first through electrode 47 buried therein; a plurality of resin layers 68, 20, 32 supported by the glass substrate; a thin-film capacitor, as thin-film capacitors 18a, 18b buried between the first resin layer 68 out of the resin layers and the second resin layer 20 out of the resin layers, having first capacitor electrodes 12a, 12b, second capacitor electrodes 16 formed oppositely to the first capacitor electrodes, and capacitor dielectric films 14 formed between the first and second capacitor electrodes and having a dielectric constant of ≥200; and second through electrodes 77a, 77b piercing through the resin layers, electrically connected the first through electrode and electrically connected to the first capacitor electrode or the second capacitor electrode. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供具有非常高电容的薄膜电容器的便宜的插入器。解决方案：插入件具有埋置在其中的第一通孔47的玻璃基板46; 由玻璃基板支撑的多个树脂层68,20,32; 薄膜电容器，作为从树脂层中的第一树脂层68和树脂层之间的第二树脂层20埋设的薄膜电容器18a，18b，具有第一电容电极12a，12b，第二电容电极16 与第一电容器电极相对地形成，以及形成在第一和第二电容器电极之间并且介电常数≥200的电容器电介质膜14; 穿过树脂层的第二贯通电极77a，77b与第一贯通电极电连接，与第一电容电极或第二电容电极电连接。版权所有（C）2008，JPO＆INPIT

10. 发明专利

JP2008047694A Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：JP2008047694A
公开(公告)日：2008-02-28
申请号：JP2006221836
申请日：2006-08-16
申请人： Fujitsu Ltd , 富士通株式会社
发明人： MIZUKOSHI MASATAKA
IPC分类号： H01L21/60
CPC分类号： H01L2224/73104
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor manufacturing method that prevents an insulating resin adhesive from leaking into between electrodes to be connected which results in deterioration of electric characteristics thereof, when connecting a semiconductor element and another semiconductor element or a circuit board via electrodes and filling the insulating resin adhesive between the electrodes to be connected.
SOLUTION: A first substrate comprises an electrode 5 that has a surface flattened by cutting, and a semi-curing adhesive insulating paste layer 6 that is formed to surround the electrode 5 and has a top face little higher than that of the electrode 5. A second substrate comprises an electrode 15 that has a top face that is flattened by cutting and has an area smaller than that of a first electrode, and a semi-curing adhesive insulating paste layer 16 that is formed to surround the electrode 15 and has a top face a little lower than that of the electrode 15. The first substrate and the second substrate are bonded in such manner that the two substrates are disposed to face each other, and the electrode 5 and electrode 15 are fitted together while maintaining the current positional relationship, and are pressurized and heated. Thus, the electrode 5 and electrode 15 are solid-phase diffusion bonded. Then, the semi-curing adhesive insulating paste layers 6 and 16 are cured.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体制造方法，当连接半导体元件和另一半导体元件或电路板时，防止绝缘树脂粘合剂泄漏到待连接的电极之间，导致其电特性的劣化通过电极将绝缘树脂粘合剂填充在要连接的电极之间。解决方案：第一基板包括具有通过切割而平坦化的表面的电极5和形成为围绕电极5并且具有比电极的顶面稍高的顶部表面的半固化粘合绝缘浆料层6 第二基板包括电极15，其具有通过切割而平坦化的顶面，并且具有比第一电极小的面积;以及半固化粘合绝缘膏层16，其形成为围绕电极15和具有比电极15的顶面略低的第一基板和第二基板以使得两个基板彼此面对的方式接合，并且将电极5和电极15装配在一起，同时保持当前位置关系，并被加压和加热。因此，电极5和电极15是固相扩散接合的。然后，半固化粘合绝缘膏层6和16固化。版权所有（C）2008，JPO＆INPIT

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