专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JP2011198796A Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2011198796A
公开(公告)日：2011-10-06
申请号：JP2010060644
申请日：2010-03-17
申请人： Fujitsu Ltd , 富士通株式会社
发明人： SHIMIZU KOZO
IPC分类号： H05K3/34 , H01L21/3205 , H01L21/60 , H01L23/52
CPC分类号： H01L2224/48091 , H01L2224/48227 , H01L2924/15311 , H01L2924/00014
摘要： PROBLEM TO BE SOLVED: To efficiently manufacture a semiconductor device of high reliability.SOLUTION: The semiconductor device 31 has electrode pads 10 formed at predetermined positions on a circuit board 1, and solder bumps 26 of a semiconductor device 21 are bonded to the electrode pad 10. The solder bumps 26 are formed on electrodes 25 of the semiconductor device 21, and lead-free solder is used as a solder material thereof. Each of the electrode pads 10 of the circuit board 1 has pluralities of projections 10A and grooves 10B, and each of the solder bumps 26 is bonded such that parts thereof fill the grooves 10B of the electrode pad 10.
摘要翻译：要解决的问题：有效地制造具有高可靠性的半导体器件。解决方案：半导体器件31具有形成在电路板1上的预定位置的电极焊盘10，半导体器件21的焊料凸块26接合到电极焊盘焊料凸块26形成在半导体器件21的电极25上，并且无铅焊料用作其焊料材料。电路板1的每个电极焊盘10具有多个突起10A和槽10B，并且每个焊料凸块26被接合，使得其部分填充电极焊盘10的槽10B。

2. 发明专利

JP2010118469A Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2010118469A
公开(公告)日：2010-05-27
申请号：JP2008290200
申请日：2008-11-12
申请人： Fujitsu Ltd , 富士通株式会社
发明人： SHIMIZU KOZO , SAKUYAMA SEIKI
IPC分类号： H01L21/60
CPC分类号： H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/92125 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide an adhesive making it hard to pass through a gap between a semiconductor chip and a spacer so as to prevent adhesion since contact utilizing elasticity is imparted when the adhesive adheres to carbon nano-tubes and is cured. SOLUTION: A semiconductor chip 50 faces a mounting board 10 with a space therebetween and is electrically connected to electrodes of the mounting board by a connecting member 55. A spacer 21 is provided between the mounting board and the semiconductor chip, secures a space, and surrounds, when viewed in plan, the mounting board and a region where electrodes of the semiconductor chip are distributed. An adhesive 35 is provided on an outer side of a cavity surrounded by the spacer, the mounting board and the semiconductor chip. The adhesive is brought in close contact with a first region on a surface of the semiconductor chip and a second region on a surface of the mounting board to fix the semiconductor chip to the mounting board. An affinity of the adhesive for the spacer is lower than any of an affinity of the semiconductor chip for the first region and an affinity of the mounting board for the second region. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了提供粘合剂，使得难以通过半导体芯片和间隔物之间的间隙，以防止粘合，因为当粘合剂粘附到碳纳米管上并且被固化时，赋予接触利用弹性。解决方案：半导体芯片50面向其间具有空间的安装板10，并通过连接构件55与安装板的电极电连接。在安装板和半导体芯片之间设置间隔件21，确保空间和周围，当从平面看时，安装板和半导体芯片的电极分布的区域。粘合剂35设置在由间隔件，安装板和半导体芯片包围的空腔的外侧。粘合剂与半导体芯片的表面上的第一区域和安装板的表面上的第二区域紧密接触，以将半导体芯片固定到安装板。粘合剂对间隔物的亲合力低于半导体芯片对于第一区域的亲和力以及安装板对第二区域的亲合力。版权所有（C）2010，JPO＆INPIT

3. 发明专利

JP2009049162A Electronic component apparatus and its manufacturing method 有权
标题翻译：电子元器件及其制造方法
公开(公告)号：JP2009049162A
公开(公告)日：2009-03-05
申请号：JP2007213463
申请日：2007-08-20
申请人： Fujitsu Ltd , 富士通株式会社
发明人： SHIMIZU KOZO
IPC分类号： H01L21/60
CPC分类号： H01L24/75 , H01L2224/16225
摘要： PROBLEM TO BE SOLVED: To mount an electronic component chip on a mounting substrate with a simple structure and a simple operation by controlling it to prescribed height and to easily remove the mounted electronic component chip in an electronic component apparatus and its manufacturing method. SOLUTION: The electronic component chip 3 having conductive pads 2, which corresponds to the conductive pads 2 installed on the mounting substrate 1, is made to confront to the mounting substrate 1 where a plurality of the conductive pads 2 are arranged on a mounting face. A characteristic of the electronic component chip 3 is tested in a state where a tip of a plurality of conductive nano-tubes 5 extending from one of the conductive pad 2 arranged in the mounting substrate 1 or the conductive pad 2 disposed in the electronic component chip 3 is brought into contact with the other conductive pad 2 where the conductive nano-tube 5 is not formed. When there is a fault in the characteristic of the electronic component chip 3, the electronic component chip 3 is exchanged. When there is no fault in the characteristic of the electronic component chip 3, the electronic component chip 3 is fixed to a mounting board 1-side by adhesive 8. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：通过将电子部件芯片控制在规定的高度并且容易地将电子部件装置中的安装的电子部件芯片除去，将电子部件芯片以简单的结构和简单的操作安装在安装基板上，其制造方法。解决方案：具有对应于安装在安装基板1上的导电焊盘2的导电焊盘2的电子部件芯片3被制成面对安装基板1，其中多个导电焊盘2布置在安装面。电子元件芯片3的特征是在从设置在安装基板1中的导电焊盘2之一延伸的多个导电纳米管5的前端或设置在电子部件芯片中的导电焊盘2的状态下进行测试 3与未形成导电性纳米管5的另一导电焊盘2接触。当电子元件芯片3的特性存在故障时，更换电子元件芯片3。当电子元件芯片3的特性没有故障时，电子元件芯片3通过粘合剂8固定在安装板1侧。（C）2009年，JPO＆INPIT

4. 发明专利

JP2008072024A Mounting structure of semiconductor device 审中-公开
标题翻译：半导体器件的安装结构
公开(公告)号：JP2008072024A
公开(公告)日：2008-03-27
申请号：JP2006250866
申请日：2006-09-15
申请人： Fujitsu Ltd , 富士通株式会社
发明人： SHIMIZU KOZO , SAKUYAMA SEIKI
IPC分类号： H01L21/60
CPC分类号： H01L2224/16225
摘要： PROBLEM TO BE SOLVED: To provide a reliable mounting structure of semiconductor devices by suppressing open-circuit failures at the outer peripheral part of a package which are easy to occur when a lead-free solder is used, by applying a simple modification to the layout or the like of an electrode on a circuit wiring board.
SOLUTION: In the mounting structure of a semiconductor device, a lead-free solder bump 16 is interposed between an electrode 15 of a package type semiconductor device 14 and an electrode 12 of a circuit wiring board 11, to connect them each other. Relating to an alignment bump 17 provided at any one point within a mounting area of the semiconductor device 14, with at least a single point near the center being preferred, and an electrode 12 of the wiring circuit board 11 connected to correspond to the electrodes 15 of the semiconductor device 14, an electrode arrangement pattern is selected and formed in advance so that the center coordinate of each electrode 12 almost agrees with the center coordinate of each electrode 15 of the semiconductor device 14 when heated, for solder reflow connection, and reaches a solder solidification point.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了通过抑制在使用无铅焊料时易于发生的封装的外周部的开路故障，通过应用简单的修改来提供半导体器件的可靠的安装结构涉及电路布线板上的电极的布局等。解决方案：在半导体器件的安装结构中，将无铅焊料凸块16插入在封装型半导体器件14的电极15和电路布线板11的电极12之间，以将它们彼此连接。关于设置在半导体器件14的安装区域内的任何一个点处的对准突起17，优选地具有至少一个靠近中心的单点，并且布线电路板11的电极12相应于电极15 半导体器件14的电极布置图案被预先选择和形成，使得当加热时每个电极12的中心坐标几乎与半导体器件14的每个电极15的中心坐标一致，用于焊料回流连接，并到达焊锡凝固点。版权所有（C）2008，JPO＆INPIT

5. 发明专利

JP2007231393A Member with plated coating film and plating treatment method 有权
标题翻译：具有涂层薄膜和镀层处理方法的成员
公开(公告)号：JP2007231393A
公开(公告)日：2007-09-13
申请号：JP2006056633
申请日：2006-03-02
申请人： Fujitsu Ltd , 富士通株式会社
发明人： SAKUYAMA SEIKI , SHIMIZU KOZO
IPC分类号： C25D7/00 , C23C10/28 , C23C28/00 , C25D5/34 , H01L23/50
CPC分类号： C22C13/00 , B32B15/015 , C22C9/02 , C22C13/02 , C23C18/1601 , C23C18/1651 , C23C18/1692 , C23C18/18 , C23C18/1848 , C23C18/48 , C23C18/52 , H01L2924/0002 , Y10T428/12715 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a member with plated coating film, excellent in solder wettability in which the occurrence of whiskers is suppressed. SOLUTION: The plated coating film member includes a substrate (10) with copper as a principal component, a plated coating film (13) for coating the substrate and having tin as a principal component, and a compound barrier layer (12) of tin and copper existing at the boundary of the substrate and the plated coating film, wherein the density of the compound barrier layer is greater than the density of the copper. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种镀覆镀膜的部件，抑制晶须出现的焊料润湿性优异。电镀涂膜构件包括以铜为主要成分的基底（10），用于涂覆基底并具有锡作为主要成分的镀覆膜（13）和化合物阻挡层（12）存在于基板和镀覆膜的边界处的锡和铜，其中化合物阻挡层的密度大于铜的密度。版权所有（C）2007，JPO＆INPIT

6. 发明专利

JP2013191721A Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2013191721A
公开(公告)日：2013-09-26
申请号：JP2012056863
申请日：2012-03-14
申请人： Fujitsu Ltd , 富士通株式会社
发明人： SHIMIZU KOZO , SAKUYAMA SEIKI
IPC分类号： H01L21/60
CPC分类号： H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2924/10156 , H01L2924/15311 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To improve reliability of a semiconductor device without causing increase in the number of manufacturing steps, relating to a method of manufacturing the semiconductor device.SOLUTION: A semiconductor device includes a base material 2, a semiconductor element 3 equipped with a lower surface 3x that faces a surface 2b of the base material 2, a terminal 4 connecting the base material 2 to the semiconductor element 3, and a resin 5 packed between the base material 2 and the semiconductor element 3. An area of an upper surface 3z of the semiconductor element 3 is larger than the area of the lower surface 3x.
摘要翻译：要解决的问题：为了提高半导体器件的可靠性而不引起制造步骤数量的增加，涉及半导体器件的制造方法。解决方案：半导体器件包括基底材料2，半导体元件3，其配备有与基材2的表面2b相对的下表面3x，将基材2连接到半导体元件3的端子4以及填充在基材2与半导体元件3之间的树脂5。半导体元件3的3z大于下表面3x的面积。

7. 发明专利

JP2013093547A Semiconductor device, electronic apparatus and semiconductor device manufacturing method 有权
标题翻译：半导体器件，电子设备和半导体器件制造方法
公开(公告)号：JP2013093547A
公开(公告)日：2013-05-16
申请号：JP2012178509
申请日：2012-08-10
申请人： Fujitsu Ltd , 富士通株式会社
发明人： SHIMIZU KOZO , SAKUYAMA SEIKI , AKAMATSU TOSHIYA
IPC分类号： H01L21/60
CPC分类号： H01L24/81 , H01L21/50 , H01L23/3128 , H01L23/49816 , H01L23/49827 , H01L23/49866 , H01L23/5383 , H01L24/13 , H01L24/16 , H01L24/73 , H01L25/0655 , H01L25/0657 , H01L2224/0401 , H01L2224/05647 , H01L2224/13111 , H01L2224/16145 , H01L2224/16148 , H01L2224/16238 , H01L2224/16506 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/81002 , H01L2224/81065 , H01L2224/81075 , H01L2224/81191 , H01L2224/8121 , H01L2224/8142 , H01L2224/81439 , H01L2224/81444 , H01L2224/81447 , H01L2224/81455 , H01L2224/81457 , H01L2224/81464 , H01L2224/81469 , H01L2224/81805 , H01L2224/81893 , H01L2224/81931 , H01L2224/83815 , H01L2225/0651 , H01L2225/06513 , H01L2924/01322 , H01L2924/01327 , H01L2924/014 , H01L2924/15192 , H01L2924/15311 , H01L2924/351 , H01L2924/00014 , H01L2924/00 , H01L2924/00012 , H01L2924/01083
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method which enables bonding at a low temperature and can raise a fusion temperature of solder bumps after bonding.SOLUTION: A semiconductor device manufacturing method comprises: a step of forming a first connection pad 11a on a principal surface 11A of a first connection member 11; a step of forming a second connection pad 21a on a circuit formation surface 21A of a semiconductor chip 21; a step of placing the semiconductor chip on the first connection member such that the first connection pad contacts the second connection pad via a solder bump 31A composed of an Sn-Bi alloy; a step of bonding the first connection pad and the second connection pad by reflow of the solder bump; and a step of causing, after the bonding step, one of the first and the second connection pads to function as an anode and the other as a cathode and supplying a direct current from the anode to the cathode to concentrate Bi in the solder bump to the anode side and Sn in the solder bump to the cathode side.
摘要翻译：要解决的问题：提供一种能够在低温下进行接合并且可以在焊接后提高焊料凸块的熔融温度的半导体器件制造方法。解决方案：半导体器件制造方法包括：在第一连接部件11的主表面11A上形成第一连接焊盘11a的步骤; 在半导体芯片21的电路形成表面21A上形成第二连接焊盘21a的步骤; 将半导体芯片放置在第一连接部件上，使得第一连接焊盘经由由Sn-Bi合金构成的焊料凸块31A与第二连接焊盘接触的步骤; 通过所述焊料凸块的回流焊接所述第一连接焊盘和所述第二连接焊盘的步骤; 以及在所述接合步骤之后，使所述第一和第二连接焊盘中的一个作为阳极而另一个作为阴极并且将来自所述阳极的直流电流供应到所述阴极以将所述焊料凸块中的Bi浓缩到焊料凸块中的阳极侧和Sn到阴极侧。版权所有（C）2013，JPO＆INPIT

8. 发明专利

JP2012174926A Semiconductor device, manufacturing method of the same and power supply device 有权
标题翻译：半导体器件及其制造方法及电源装置
公开(公告)号：JP2012174926A
公开(公告)日：2012-09-10
申请号：JP2011036254
申请日：2011-02-22
申请人： Fujitsu Ltd , 富士通株式会社
发明人： SHIMIZU KOZO , OKAMOTO KEISHIRO , IMAIZUMI NOBUHIRO , IMADA TADAHIRO , WATABE KEIJI
IPC分类号： H01L21/52 , H01L21/338 , H01L29/778 , H01L29/812
CPC分类号： H01L23/48 , H01L23/3128 , H01L24/29 , H01L24/32 , H01L24/83 , H01L2224/04026 , H01L2224/05005 , H01L2224/05082 , H01L2224/05155 , H01L2224/05166 , H01L2224/05169 , H01L2224/05541 , H01L2224/05573 , H01L2224/05644 , H01L2224/0603 , H01L2224/26175 , H01L2224/2745 , H01L2224/2746 , H01L2224/29019 , H01L2224/29036 , H01L2224/29109 , H01L2224/29111 , H01L2224/29113 , H01L2224/2912 , H01L2224/29139 , H01L2224/29144 , H01L2224/29147 , H01L2224/29155 , H01L2224/2919 , H01L2224/2929 , H01L2224/29339 , H01L2224/29499 , H01L2224/32225 , H01L2224/32245 , H01L2224/325 , H01L2224/32502 , H01L2224/32506 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48245 , H01L2224/48247 , H01L2224/48644 , H01L2224/48744 , H01L2224/4903 , H01L2224/73265 , H01L2224/83193 , H01L2224/83194 , H01L2224/83801 , H01L2224/83851 , H01L2924/00013 , H01L2924/01029 , H01L2924/01322 , H01L2924/13064 , H01L2924/15311 , H01L2924/181 , H01L2224/83439 , H01L2924/00014 , H01L2924/00012 , H01L2924/0132 , H01L2924/01047 , H01L2924/0105 , H01L2924/0665 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To inhibit displacement of a semiconductor chip such as shifting and rotation when the semiconductor chip is mounted on a support plate such as a circuit board and a stage of a lead frame.SOLUTION: A semiconductor device manufacturing method includes the steps of: forming one of a layer 5 containing a fist metal and a layer 6 containing a second metal on one of a semiconductor chip mounting region 2A on a support plate 2 and a rear face of a semiconductor chip 1; forming the other of the layer containing the first metal and the layer containing the second metal in a region corresponding to a part of the region on which the one of the layer containing the first metal and the layer containing the second metal is formed, on the other of the semiconductor mounting region and the rear face of the semiconductor chip; aligning the semiconductor chip on the semiconductor chip mounting region; forming a layer 9 containing an alloy containing the first metal and the second metal; and bonding the semiconductor chip to the semiconductor chip mounting region.
摘要翻译：要解决的问题：当半导体芯片安装在诸如电路板的支撑板和引线框架的台架上时，抑制半导体芯片的位移，例如移位和旋转。解决方案：半导体器件制造方法包括以下步骤：在支撑板2上的半导体芯片安装区域2A和后部之一上形成包含第一金属的层5和含有第二金属的层6中的一个半导体芯片1的面; 在与包含第一金属和含有第二金属的层的一个区域形成的区域的一部分相对应的区域中形成含有第一金属和含有第二金属的层的另一层，在半导体安装区域和半导体芯片的背面中的另一个; 将半导体芯片对准半导体芯片安装区域; 形成含有含有第一金属和第二金属的合金的层9; 并将半导体芯片接合到半导体芯片安装区域。版权所有（C）2012，JPO＆INPIT

9. 发明专利

JP2011096803A Semiconductor device, and method of manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2011096803A
公开(公告)日：2011-05-12
申请号：JP2009248482
申请日：2009-10-29
申请人： Fujitsu Ltd , 富士通株式会社
发明人： SHIMIZU KOZO
IPC分类号： H01L21/60
CPC分类号： H01L2224/16225
摘要： PROBLEM TO BE SOLVED: To enhance connection reliability between an electrode and a solder bump in a semiconductor device and a method of manufacturing the same. SOLUTION: The semiconductor device includes a circuit board 1 on which a first electrode 4 containing copper is formed, a barrier metal layer 10 formed on a surface of the first electrode 4 and suppressing reaction of the copper and tin, a tin layer 12 formed on the barrier metal layer 10, the lead-free solder bump 18 bonded to the first electrode 4 through the tin layer 12, and a semiconductor package 20 having a second electrode 22 bonded to the lead-free solder bump 18. COPYRIGHT: (C)2011,JPO&INPIT

10. 发明专利

JP2010219397A Electronic component and method of manufacturing the same 有权
标题翻译：电子元件及其制造方法
公开(公告)号：JP2010219397A
公开(公告)日：2010-09-30
申请号：JP2009066050
申请日：2009-03-18
申请人： Fujitsu Ltd , 富士通株式会社
发明人： SHIMIZU KOZO , SAKUYAMA SEIKI , MIZUKOSHI MASATAKA
IPC分类号： H01L21/60
CPC分类号： H01L2224/16 , H01L2224/16225 , H01L2224/81903 , H01L2224/83951 , H01L2924/351 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide an electronic component having a semiconductor element mounted on a circuit board and a method of manufacturing the component which make it possible to effectively reduce a stress applied from the circuit board to the semiconductor element while maintaining a contact connection between the circuit board and the semiconductor element. SOLUTION: The electronic component includes a substrate 30, and a substrate 10 formed on the substrate 30 and connected electrically to the substrate 30 by means of a protruding terminal. The protruding terminal includes a bundle 20 of linear structures of carbon element having a conductive film 22 on an end portion facing the substrate 30, and a bundle 34 of linear structures of carbon element having a conductive film on an end portion facing the substrate 10. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种具有安装在电路板上的半导体元件的电子部件和制造该部件的方法，其可以有效地减少从电路板施加到半导体元件的应力，同时保持电路板与半导体元件之间的接触连接。解决方案：电子部件包括基板30和形成在基板30上并通过突出端子与基板30电连接的基板10。突出端子包括在面向基板30的端部上具有导电膜22的碳元素的线状结构的束20以及在面向基板10的端部上具有导电膜的碳元素的线状结构的束34。版权所有（C）2010，JPO＆INPIT

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式