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1. 发明公开

EP1489706A4 OPTICAL MODULE AND METHOD FOR ASSEMBLING OPTICAL MODULE 审中-公开
标题翻译：光模块联合施工方法光模块
公开(公告)号：EP1489706A4
公开(公告)日：2010-03-10
申请号：EP03710340
申请日：2003-03-13
申请人： FURUKAWA ELECTRIC CO LTD
发明人： ZAMA SATORU , MUGISHIMA TOSHIO , MITOSE KENGO , TSUZUKI YOSHIKAZU , SAKATA MASATO
IPC分类号： G02B6/42 , H01S5/022
CPC分类号： G02B6/4238 , G02B6/4201 , G02B6/4271 , H01S5/02216 , H01S5/02236 , H01S5/02252 , H01S5/02284

2. 发明专利

JP2002296431A POLARIZATION MAINTAINING FIBER AND METHOD OF MANUFACTURING THE SAME, AND SEMICONDUCTOR LASER MODULE 失效
公开(公告)号：JP2002296431A
公开(公告)日：2002-10-09
申请号：JP2001103804
申请日：2001-04-02
申请人： FURUKAWA ELECTRIC CO LTD
发明人： KUSANO TERUO , MUGISHIMA TOSHIO , MIYOKAWA JUN
IPC分类号： G02B6/00 , G02B6/02 , G02B6/024 , G02B6/10 , G02B6/26 , G02B6/42 , H01S5/022 , H01S5/14 , G02B6/17
摘要： PROBLEM TO BE SOLVED: To provide polarization maintaining fiber in which the crack of the exposed surface of a stress imparting part is prevented, and to provide a method of manufacturing the same, and a semiconductor laser module. SOLUTION: Planate inclined surfaces 6a and 6b opposed with each other are formed on a fiber tip part, and are process into a lens shape (here, wedge shape). The lens shape is formed so that a stress imparting parts 4a and 4b may not reside on the ridgeline 7 of a wedge where each of the inclined surfaces 6a and 6b are crossed. The stress imparting part 4a is exposed only on the one inclined surface 6a, and the stress imparting part 4b is exposed only on the other inclined surface 6b. Accordingly, one stress imparting part is not exposed over two inclined surfaces.

3. 发明专利

JPH07111383A METHOD FOR MANUFACTURING CIRCUIT BOARD 失效
公开(公告)号：JPH07111383A
公开(公告)日：1995-04-25
申请号：JP27883993
申请日：1993-10-13
申请人： FURUKAWA ELECTRIC CO LTD , FURUKAWA SAAKIT FOIL KK
发明人： OTANI KENICHI , MUGISHIMA TOSHIO , SEKI OSAMU , MATSUKI NOBORU
IPC分类号： H05K3/42
摘要： PURPOSE:To simultaneously performing punching for forming a through hole to be continuous and that to be insulated by depositing a metal plating layer on the conductive polymer layer surface on the wall surface within a first through hole which is not forced to be non-conductive by a non-conductor process. CONSTITUTION:A conductive polymer layer 6 is formed on each inner wall surface of first and second through holes 3 and 4 at a conductivity-giving process for a base 1 made of an insulation material such as plastic with first and second through holes 3 and 4. Then, the surface of the conductive polymer layer 6 formed on the inner wall surface of the second through hole (device hole) 4 in the non-conductor process is turned into non-conductive state and a metal plating layer is deposited on the surface of the conductive polymer layer 6 on the inner wall surface of the first through hole 3 which is not turned into non-conductive state by the non-conductor process in the plating process, thus simultaneously performing punching for forming the through hole 3 and the device hole 4, reducing the number of etchings, and simply manufacturing a circuit board.

4. 发明专利

JPH07111279A FILM CHIP CARRIER AND ITS MANUFACTURE 失效
公开(公告)号：JPH07111279A
公开(公告)日：1995-04-25
申请号：JP27884193
申请日：1993-10-13
申请人： FURUKAWA ELECTRIC CO LTD , FURUKAWA SAAKIT FOIL KK
发明人： SEKI OSAMU , MUGISHIMA TOSHIO , OTANI KENICHI
IPC分类号： H01L21/60 , H01L23/48 , H01L23/50
摘要： PURPOSE:To make it possible to form a stable circuit without dispersion in exposure and developing process, permitting the easy coating of uniform resist and eliminating level differences caused by the different thickness of a metal layer on the surface of a metal wiring layer where the outer leads have a thick film construction. CONSTITUTION:A metal plated layer 9 is adhered to an outer lead portion exposed to an outer lead hole region of a boundary surface to an insulation layer of a metal wiring layer 2 formed on at least one of the surfaces of an insulation layer 1 consisting of a plastic material to which outer lead holes 7 were drilled.

5. 发明专利

JPH0714886A CHIP CARRIER 失效
公开(公告)号：JPH0714886A
公开(公告)日：1995-01-17
申请号：JP17764493
申请日：1993-06-25
申请人： FURUKAWA ELECTRIC CO LTD , FURUKAWA SAAKIT FOIL KK
发明人： OTANI KENICHI , MUGISHIMA TOSHIO , SEKI OSAMU
IPC分类号： H01L21/60 , H05K1/11
摘要： PURPOSE:To enable a metal wiring to be very small in wire width and inter-wire pitch on both an inner lead side and an outer lead side by a method wherein the metal wiring is supported by a first flexible film member at the inner lead side and supported by a second flexible film member at the outer lead side respectively. CONSTITUTION:A metal wiring 1 is supported by a polyimide film 2 as a first flexible film member at an inner lead 1a side making its one side bear against the film 2 and supported by polyimide coating layers 3a to 3d as a second flexible film member at an outer lead 1b side making its other side bear against the polyimide coating layers 3a to 3d. The exposed surface of the inner lead 1a is made to face upward, and on the other hand that of the outer lead 1b is made to face downward. By this setup, metal wirings can be made very small in both wiring width and inter-writing pitch on both an inner lead side and an outer lead side.

6. 发明专利

JPH05206201A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH05206201A
公开(公告)日：1993-08-13
申请号：JP3853792
申请日：1992-01-28
申请人： FURUKAWA ELECTRIC CO LTD , FURUKAWA SAAKITSUTO FOIL KK
发明人： MUGISHIMA TOSHIO , SEKI OSAMU , OTANI KENICHI
IPC分类号： H01L21/60
摘要： PURPOSE:To improve bonding workability and durability of a chip carrier, by arranging a theremally conductive penetration post which penetrates a flexible film part, on the rear side of an inner lead part of metal wiring. CONSTITUTION:Metal wiring 1 is radially arranged in four directions in the manner in which inner lead parts la are positioned inside and outer lead parts 1b are positioned outside. The inner lead parts 1a are bonded to bumps 7 of a semiconductor chip 6, and the outer lead parts 1b are connected with a lead frame, terminal parts of an external circuit board, etc. Coating and exposure of cyclized isoprene rubber are repeated on the surface of a compound tape on which surface metal wiring 1 is formed and on the surface of a flexible tape 2, thereby forming through holes, sprocket holes 5, and outer lead holes 1b. After the wall surface of the through hole is subjected to conduction treatment, the hole is filled by electroplating, and a penetration post 8 is formed. At the time of bonding, a tool is made to abut against the penetration post 8, heat and pressure are applied, and the bump of the chip 6 is bonded to the inner lead part 1a. Sufficient finger strength can be obtained and the metal wiring can be made fine.

7. 发明专利

JPH04345044A MANUFACTURE OF TWO-LAYERED TAB 失效
公开(公告)号：JPH04345044A
公开(公告)日：1992-12-01
申请号：JP11771891
申请日：1991-05-22
申请人： FURUKAWA ELECTRIC CO LTD
发明人： SEKI OSAMU , OTANI KENICHI , MUGISHIMA TOSHIO
IPC分类号： H01L21/60
摘要： PURPOSE:To effectively obtain a two-layered TAB exerting no influence upon heating at the time of semiconductor element mounting, while compensating mechanical strength of inner leads, by performing etching while an outer lead part and a sprocket part are irradiated from the insulating layer side of a two-layered TAB original sheet, with a light having an ultraviolet wavelength region. CONSTITUTION:A two-layered TAB original sheet is obtained by forming a copper layer 11 on a polyimide film 10. After a resist layer 12 is formed on the polyimide film 10, said resist layer 12 is exposed to light by using a photo mask having patterns of a sprocket hole part 30, an inner lead part 31 and an outer lead part 32, and then developed, thus forming a resist mask 13. While the sprocket hole part 30 and the outer lead part 32 are irradiated with ultraviolet rays by using a high pressure mercury lamp, etching is performed. The resist layer 13 is eliminated, and the sprocket hole part 30 and the outer lead part 32 are completely etched, thereby obtaining a two-layered TAB wherein the inner lead part 31 of about 5mum in thickness is left.

8. 发明专利

JPH07249711A CHIP CARRIER 失效
公开(公告)号：JPH07249711A
公开(公告)日：1995-09-26
申请号：JP4990994
申请日：1994-02-24
申请人： FURUKAWA ELECTRIC CO LTD , FURUKAWA SAAKIT FOIL KK
发明人： OTANI KENICHI , MUGISHIMA TOSHIO , SEKI OSAMU , MATSUKI NOBORU
IPC分类号： H05K3/44 , H01L23/12
摘要： PURPOSE:To form a thin metal wiring at fine pitch at the inner lead part of a chip carrier by forming a thin part in the chip mounting region and coating the bonding surface at the inner lead part, lined with the thin part, with a solder layer. CONSTITUTION:A chromium layer 10a and copper layers 10b, 10c are formed on a tape-like polyimide film 12 to produce a copper foil layer 10. The copper foil layer 10 is then etched to form a metal wiring it including an inner lead part 11a and an outer lead part 11b. The polyimide layer is then removed from a predetermined region through etching on the rear side thus leaving a thin polyimide layer. Subsequently, a device hole 14 is opened while leaving the thin part 13 followed by formation of an outer lead hole 16. Finally, a lead-tin alloy based solder layer 18 is formed on the surface of each metal wiring 11 over the entire length of the inner lead part 11a.

9. 发明专利

JPH07111384A METHOD FOR MANUFACTURING CIRCUIT BOARD 失效
公开(公告)号：JPH07111384A
公开(公告)日：1995-04-25
申请号：JP27884093
申请日：1993-10-13
申请人： FURUKAWA ELECTRIC CO LTD , FURUKAWA SAAKIT FOIL KK
发明人： OTANI KENICHI , MUGISHIMA TOSHIO , SEKI OSAMU , MATSUKI NOBORU
IPC分类号： H05K3/42
摘要： PURPOSE:To reduce the number of etchings of an insulation layer for punching as compared with before by selectively forming a conductive polymer layer only on the inner wall surface of a first through hole to be continuous and then depositing a metal plating layer through it. CONSTITUTION:Formation of a conductive polymer layer 7 on the inner wall surface of a second through hole (device hole) 4 of a base 1 with first and second through holes 3 and 4 can be prevented and a conductive polymer layer 7 in contact with the inner wall surface is formed in the first through hole 3 only. Then, a metal plating layer is deposited on the surface of the conductive polymer layer 7, thus simultaneously performing punching for forming the through hole 3 and the device hole 4, reducing the number of etchings as compared with before, and then simply manufacturing a circuit board.

10. 发明专利

JPH0669644A METHOD OF MANUFACTURING LAMINATED MATERIAL FOR CIRCUIT BOARD 失效
公开(公告)号：JPH0669644A
公开(公告)日：1994-03-11
申请号：JP23633592
申请日：1992-08-13
申请人： FURUKAWA ELECTRIC CO LTD , FURUKAWA SAAKITSUTO FOIL KK
发明人： OTANI KENICHI , MUGISHIMA TOSHIO , SEKI OSAMU
IPC分类号： H05K3/16 , H05K3/38
摘要： PURPOSE:To realize a method of manufacturing a laminated material for a circuit board which can provided sufficient adhesion strength between a high polymer material layer and a metallic layer and in which an interlayer separation is not caused by various treatments and processings in manufacturing the circuit board. CONSTITUTION:After a low temperature plasma processing is performed on the high polymer material surface such as polyimide, etc., the high polymer material is soaked into a solvent, an aqueous solution, or the like (for example, an interface activator solvent in which soda pyro-sulfite is added to an anion group interface activator such as alkylbenzene sulfonic acid soda etc., degreasing agent such as an alkali group aqueous solution, etc., comprising sodium hydroxide, sodium carbonate, soda orthosilicic acid, interface activator or the like) to remove degenerated matter caused near the high polymer material layer surface when the plasma processing is performed. Thereafter, a metallic layer is provided on the high polymer material layer to obtain a laminated material for a circuit board.

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