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1. 发明申请

WO2007022136A2 IMPROVED TRANSIENT BLOCKING UNIT 审中-公开
标题翻译：改进的瞬时阻塞单元
公开(公告)号：WO2007022136A2
公开(公告)日：2007-02-22
申请号：PCT/US2006/031742
申请日：2006-08-11
申请人： FULTEC SEMICONDUCTOR, INC. , HARRIS, Richard, A. , BLANCHARD, Richard, A. , HEBERT, Francois
发明人： HARRIS, Richard, A. , BLANCHARD, Richard, A. , HEBERT, Francois
IPC分类号： H02H9/06
CPC分类号： H02H9/025
摘要： Improved electrical transient blocking is provided with a transient blocking unit (TBU) having a partial disconnect capability. A TBU is an arrangement of voltage controlled switches that normally conducts, but switches to a disconnected state in response to an above-threshold input transient. Partial disconnection improves the power handling capability of a TBU by preventing thermal damage to the TBU. Partial TBU disconnection can be implemented to keep power dissipation in the TBU below a predetermined level P max , thereby avoiding thermal damage to the TBU by keeping the TBU temperature below a temperature limit T max . Alternatively, partial TBU disconnection can be implemented to keep TBU temperature below T max using direct temperature sensing and feedback.
摘要翻译：提供了具有部分断开能力的瞬态阻塞单元（TBU）的改进的电瞬变阻塞。 TBU是通常导通的电压控制开关的布置，但是响应于高于阈值的输入瞬变而切换到断开状态。部分断开通过防止TBU的热损坏提高了TBU的功率处理能力。可以实施部分TBU断开以将TBU中的功率消耗降低到预定水平P max以下，从而通过将TBU温度保持在温度下限T max以下来避免对TBU的热损伤， SUB>。或者，可以使用直接温度感测和反馈来实现部分TBU断开以将TBU温度保持在T 以下。

2. 发明申请

WO2006116517A2 APPARATUS AND METHOD FOR TRANSIENT BLOCKING EMPLOYING RELAYS 审中-公开
标题翻译：瞬态阻塞使用继电器的装置和方法
公开(公告)号：WO2006116517A2
公开(公告)日：2006-11-02
申请号：PCT/US2006/015841
申请日：2006-04-25
申请人： FULTEC SEMICONDUCTOR, INC. , BLANCHARD, Richard, A. , HARRIS, Richard, A. , HEBERT, Francois
发明人： BLANCHARD, Richard, A. , HARRIS, Richard, A. , HEBERT, Francois
IPC分类号： H02H9/00
CPC分类号： H01J1/72 , C09K11/59 , H01H9/548 , H02H9/025
摘要： An apparatus and a method for uni-directional and bi-directional transient blocking. The uni-directional apparatus has a depletion mode n-channel device at its input and a normally closed relay, e.g., a micro-electro-mechanical (MEM) relay, interconnected with the depletion mode n-channel device and the input in such a way that at a predetermined current value the transient causes the normally closed relay to switch into an open state and produces a bias voltage V n on the depletion mode n-channel device that is sufficiently high to switch it "off" and thus block the transient. An analogous arrangement at the output taking advantage of the same or a second relay renders the apparatus bi-directional. The structure of the apparatus and the method of operation ensure a reliable and repeatable trip current I trip and render the apparatus very robust and feasible for low-cost manufacture.
摘要翻译：用于单向和双向瞬态阻塞的装置和方法。单向设备在其输入端具有耗尽模式n沟道器件和常闭继电器，例如与耗尽型n沟道器件互连的微机电（MEM）继电器，以及在这种在预定电流值下，瞬态使常闭继电器切换到打开状态，并且在耗尽型n沟道器件上产生足够高以切换它的偏置电压V N“ 关闭“，从而阻止瞬态。利用相同或第二中继器的输出处的类似布置使设备双向。该装置的结构和操作方法确保了可靠和可重复的跳闸电流跳闸，并且使得该装置非常坚固且适用于低成本制造。

3. 发明申请

WO2007058799A2 TRANSIENT BLOCKING UNIT HAVING SHUNT FOR OVER-VOLTAGE PROTECTION 审中-公开
标题翻译：具有过压保护的瞬态闭锁单元
公开(公告)号：WO2007058799A2
公开(公告)日：2007-05-24
申请号：PCT/US2006/043102
申请日：2006-11-03
申请人： FULTEC SEMICONDUCTOR, INC. , HARRIS, Richard, A. , HEBERT, Francois
发明人： HARRIS, Richard, A. , HEBERT, Francois
IPC分类号： H02H3/22
CPC分类号： H02H9/025 , H01L27/0266 , H02H9/04
摘要： A transient blocking unit (TBU) having improved damage resistance is provided. A TBU includes two or more depletion mode transistors arranged to provide a low series impedance in normal operation and a high series impedance when the input current exceeds a predetermined threshold. At least one of the TBU transistors is a protecting device having a shunt circuit element connected in parallel with its channel. When the TBU is in its high impedance state, the shunt circuit element provides a current path, thereby decreasing terminal voltages on at least one of the TBU transistors. The shunt element can be a discrete or integrated resistor, a current source including a transistor, or an appropriately engineered device parasitic.
摘要翻译：提供具有改进的抗损伤性的瞬变阻挡单元（TBU）。 TBU包括两个或更多个耗尽型晶体管，其布置成在正常操作中提供低串联阻抗，并且当输入电流超过预定阈值时提供高串联阻抗。至少一个TBU晶体管是具有与其沟道并联连接的分流电路元件的保护装置。当TBU处于其高阻抗状态时，分路电路元件提供电流路径，从而减小至少一个TBU晶体管上的端电压。分流元件可以是分立的或集成的电阻器，包括晶体管的电流源，或适当设计的寄生器件。

4. 发明申请

WO2006053025A2 APPARATUS AND METHOD FOR TEMPERATURE-DEPENDENT TRANSIENT BLOCKING 审中-公开
标题翻译：用于温度依赖性瞬态阻塞的装置和方法
公开(公告)号：WO2006053025A2
公开(公告)日：2006-05-18
申请号：PCT/US2005/040555
申请日：2005-11-09
申请人： FULTEC SEMICONDUCTOR, INC. , HARRIS, Richard, A. , COATES, Stephen , HEBERT, Francois
发明人： HARRIS, Richard, A. , COATES, Stephen , HEBERT, Francois
IPC分类号： H02H1/00
CPC分类号： H02H5/044 , H02H5/042 , H02H9/025
摘要： An apparatus and method for temperature-dependent transient blocking employing a transient blocking unit (TBU) that uses at least one depletion mode n-channel device interconnected with at least one depletion mode p-channel device. The interconnection is performed such that a transient alters a bias voltage V p of the p-channel device and a bias voltage V n of the n-channel device in concert to effectuate their mutual switch off to block the transient. The apparatus has a temperature control unit that is in communication with the TBU and adjusts at least one of the bias voltagesV P, V n in response to a sensed temperature T 5 , thereby enabling the apparatus to also respond to over-temperature. In some embodiments the p-channel device is replaced with a positive temperature coefficient thermistor (PTC). The temperature control unit can use any suitable circuit element, including, among other a PTC, resistor, negative temperature coefficient element, positive temperature coefficient element, transistor, diode.
摘要翻译：一种采用使用与至少一个耗尽型p沟道器件互连的至少一个耗尽型n沟道器件的瞬态阻断单元（TBU）的温度依赖性瞬态阻塞的装置和方法。执行互连，使得瞬态改变p沟道器件的偏置电压V SUB p N和N沟道器件的偏置电压V N n N一致地实现他们的相互关闭来阻止瞬态。该装置具有与TBU通信的温度控制单元，并且响应于感测到的温度T 5 ，从而使得该装置也能够对过温作出响应。在一些实施例中，用正温度系数热敏电阻（PTC）代替p沟道器件。温度控制单元可以使用任何合适的电路元件，包括PTC，电阻器，负温度系数元件，正温度系数元件，晶体管，二极管等。

5. 发明申请

WO2006053326A2 INTEGRATED TRANSIENT BLOCKING UNIT COMPATIBLE WITH VERY HIGH VOLTAGES 审中-公开
标题翻译：集成的瞬态阻塞单元兼容非常高的电压
公开(公告)号：WO2006053326A2
公开(公告)日：2006-05-18
申请号：PCT/US2005/041416
申请日：2005-11-09
申请人： FULTEC SEMICONDUCTOR, INC. , HEBERT, Francois , HARRIS, Richard, A.
发明人： HEBERT, Francois , HARRIS, Richard, A.
IPC分类号： H02H9/00
CPC分类号： H01L27/0266 , H01L27/0727 , H02H9/025 , H02H9/046
摘要： A transient blocking unit (TBU) with integrated over-current protection and discrete over-voltage protection. In one example embodiment, the present innovations are embodied as a unit for protecting a circuit from high voltage and high current, comprising a core transient blocking unit with at least one high voltage device wherein the core transient blocking unit is integrated, and wherein the at least one high voltage device is discrete.
摘要翻译：具有集成过流保护和离散过电压保护的瞬态阻断单元（TBU）。在一个示例性实施例中，本发明被实施为用于保护电路免受高电压和高电流的单元，其包括具有至少一个高压器件的核心瞬态阻塞单元，其中所述核心瞬态阻塞单元被集成，并且其中，至少一个高压装置是离散的。

6. 发明申请

WO2006053314A2 APPARATUS AND METHOD FOR HIGH-VOLTAGE TRANSIENT BLOCKING USING LOW-VOLTAGE ELEMENTS 审中-公开
标题翻译：使用低电压元件的高电压瞬态阻塞的装置和方法
公开(公告)号：WO2006053314A2
公开(公告)日：2006-05-18
申请号：PCT/US2005/041292
申请日：2005-11-09
申请人： FULTEC SEMICONDUCTOR, INC. , HARRIS, Richard, A. , HEBERT, Francois
发明人： HARRIS, Richard, A. , HEBERT, Francois
IPC分类号： H02H9/00
CPC分类号： H02H9/025 , H01L27/0266 , H01L27/0727 , H01L29/808 , H02H9/046
摘要： An apparatus and method for high-voltage transient blocking employing a transient blocking unit (TBU) that has at least one depletion mode n-channel device interconnected with at least one depletion mode p-channel device such that a transient alters a bias voltage V p of the p-channel device and a bias voltage V n of the n-channel device in concert. Specifically, the bias voltages are altered such that the pchannel device and n-channel device mutually switch off to block the transient. The depletion mode n-channel device employs a set of cascaded low-voltage depletion mode field effect transistors (FETs) such as metal-oxide-silicon field effect transistors (MOSFETs) connected source-to-drain to achieve the desired high-voltage operation of the TBU.
摘要翻译：一种使用具有与至少一个耗尽型p沟道器件互连的至少一个耗尽型n沟道器件的瞬态阻断单元（TBU）的装置和方法，使得瞬态改变偏置电压V' p沟道器件的SUB> p 和n沟道器件的偏置电压V N n N一致。具体地说，偏置电压被改变，使得p沟道器件和n沟道器件相互关闭以阻止瞬变。耗尽型n沟道器件采用一组级联的低电压耗尽型场效应晶体管（FET），例如连接源极到漏极的金属氧化物 - 硅场效应晶体管（MOSFET），以实现所需的高电压工作的TBU。

7. 发明申请

WO2006053292A2 APPARATUS AND METHOD FOR ENHANCED TRANSIENT BLOCKING 审中-公开
标题翻译：用于增强瞬态阻塞的装置和方法
公开(公告)号：WO2006053292A2
公开(公告)日：2006-05-18
申请号：PCT/US2005/041159
申请日：2005-11-09
申请人： FULTEC SEMICONDUCTOR, INC. , HARRIS, Richard, A. , HEBERT, Francois
发明人： HARRIS, Richard, A. , HEBERT, Francois
IPC分类号： H02H9/00
CPC分类号： H01L27/0266 , H02H5/042 , H02H5/044 , H02H9/025 , H02H9/046
摘要： An apparatus and method for enhanced transient blocking employing a transient blocking unit (TBU) that uses at least one depletion mode n-channel device interconnected with at least one depletion mode p-channel device. The interconnection is performed such that a transient alters a bias voltage V p of the p-channel device and a bias voltage V n of the n-channel device such that the p-and n-channel devices mutually switch off to block the transient. The apparatus has an enhancer circuit for applying an enhancement bias to a gate terminal of at least one of the depletion mode n-channel devices of the TBU to reduce a total resistance R tot of the apparatus. Alternatively, the apparatus has an enhancement mode NMOS transistor and a TBU connected thereto to help provide an enhancement bias to a gate terminal of the enhancement mode NMOS.
摘要翻译：一种用于增强瞬态阻塞的装置和方法，其采用使用与至少一个耗尽型p沟道器件互连的至少一个耗尽型n沟道器件的瞬态阻塞单元（TBU）。执行互连，使得瞬态改变p沟道器件的偏置电压V P和N沟道器件的偏置电压V N n N，使得p 并且n通道设备相互关闭以阻止瞬态。该装置具有增强器电路，用于将增强偏压施加到TBU的至少一个耗尽型n沟道器件的栅极端子，以减小器件的总电阻R ttt。或者，该装置具有增强型NMOS晶体管和与其连接的TBU，以帮助向增强型NMOS的栅极端提供增强偏置。

8. 发明申请

WO2006053238A2 INTELLIGENT TRANSIENT BLOCKING UNIT 审中-公开
标题翻译：智能瞬态阻塞单元
公开(公告)号：WO2006053238A2
公开(公告)日：2006-05-18
申请号：PCT/US2005/040981
申请日：2005-11-09
申请人： FULTEC SEMICONDUCTOR, INC. , HEBERT, Francois , HARRIS, Richard, A.
发明人： HEBERT, Francois , HARRIS, Richard, A.
IPC分类号： H02H9/06
CPC分类号： H01L27/0266 , H01L21/823462 , H01L27/088 , H02H9/025 , H02H9/046
摘要： A TBU system that includes a TBU combined with control and monitoring features. For example, in one embodiment, TBU elements are combined with a status indication switch or indicator. In another embodiment, TBU elements are combined with event logging for over voltage conditions, over current conditions, including an indication of when the event occurred and an amount of energy that was let through.
摘要翻译：一个TBU系统，包括TBU与控制和监控功能相结合。例如，在一个实施例中，TBU元件与状态指示开关或指示器组合。在另一个实施例中，TBU元件与过电压条件的事件记录相结合，包括当前状况的发生以及通过的能量的指示。

9. 发明申请

WO2006122328A2 INCREASING BREAKDOWN VOLTAGE IN SEMICONDUCTOR DEVICES WITH VERTICAL SERIES CAPACITIVE STRUCTURES 审中-公开
标题翻译：在具有垂直系列电容结构的半导体器件中增加断开电压
公开(公告)号：WO2006122328A2
公开(公告)日：2006-11-16
申请号：PCT/US2006/018922
申请日：2006-05-11
申请人： FULTEC SEMICONDUCTOR, INC. , YANG, Robert, Kuo-Chang , HEBERT, Francois
发明人： YANG, Robert, Kuo-Chang , HEBERT, Francois
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L29/7802 , H01L29/407 , H01L29/4236 , H01L29/7395 , H01L29/74 , H01L29/7803 , H01L29/7811 , H01L29/7813 , H01L29/861
摘要： This invention relates to an apparatus and method for achieving high breakdown voltage and low on-resistance in semiconductor devices that have top, intermediate and bottom regions with a controllable current path traversing any of these regions. The device has an insulating trench that is coextensive with the top and intermediate regions and girds these regions from at least one side and preferably from both or all sides. A series capacitive structure with a biased top element and a number of floating elements is disposed in the insulating trench, and the intermediate region is endowed with a capacitive property that is chosen to establish a capacitive interaction or coupling between the series capacitive structure and the intermediate region so that the breakdown voltage VBD is maximized and on- resistance is minimized. The capacitive property of the intermediate region is established by an appropriately chosen material constitution and is further controlled by a predetermined constitution of the insulating trench. The apparatus and method of invention are useful in any number of semiconductor devices including, among other, transistors, bipolar transistors, MOSFETs, JFETs, thyristors and diodes.
摘要翻译：本发明涉及一种用于实现半导体器件中的高击穿电压和低导通电阻的装置和方法，所述半导体器件具有穿过任何这些区域的可控电流路径的顶部，中间和底部区域。该装置具有与顶部和中间区域共同延伸的绝缘沟槽，并且从至少一个侧面，优选地从两侧或全部侧面将这些区域线化。具有偏置顶部元件和多个浮动元件的串联电容结构设置在绝缘沟槽中，并且中间区域具有被选择用于建立串联电容结构和中间体之间的电容性相互作用或耦合的电容性质使得击穿电压VBD最大化并且导通电阻最小化。通过适当选择的材料结构建立中间区域的电容性质，并通过绝缘沟槽的预定结构进一步控制。本发明的装置和方法可用于任何数量的半导体器件，其中包括晶体管，双极晶体管，MOSFET，JFET，晶闸管和二极管。

10. 发明公开

EP1815573A2 INTEGRATED TRANSIENT BLOCKING UNIT COMPATIBLE WITH VERY HIGH VOLTAGES 审中-公开
标题翻译：具有非常高的电压兼容集成的瞬态阻塞单元
公开(公告)号：EP1815573A2
公开(公告)日：2007-08-08
申请号：EP05826642.0
申请日：2005-11-09
申请人： Fultec Semiconductor Inc.
发明人： HEBERT, Francois , HARRIS, Richard, A.
IPC分类号： H02H9/00
CPC分类号： H01L27/0266 , H01L27/0727 , H02H9/025 , H02H9/046
摘要： A transient blocking unit (TBU) with integrated over-current protection and discrete over-voltage protection. In one example embodiment, the present innovations are embodied as a unit for protecting a circuit from high voltage and high current, comprising a core transient blocking unit with at least one high voltage device wherein the core transient blocking unit is integrated, and wherein the at least one high voltage device is discrete.

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