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1. 发明申请

WO2009099834A3 WAFER LEVEL CHIP SCALE PACKAGE AND PROCESS OF MANUFACTURE 审中-公开
标题翻译： WAFER LEVEL CHIP SCALE包装及其制造工艺
公开(公告)号：WO2009099834A3
公开(公告)日：2009-10-01
申请号：PCT/US2009032242
申请日：2009-01-28
申请人： ALPHA & OMEGA SEMICONDUCTOR , FENG TAO , HEBERT FRANCOIS , SUN MING , HO YUEH-SE
发明人： FENG TAO , HEBERT FRANCOIS , SUN MING , HO YUEH-SE
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L29/7827 , H01L21/76898 , H01L23/481 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/16 , H01L24/81 , H01L29/0657 , H01L29/41741 , H01L29/4175 , H01L29/45 , H01L29/49 , H01L29/7802 , H01L2224/02371 , H01L2224/03464 , H01L2224/0347 , H01L2224/0401 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/06181 , H01L2224/06183 , H01L2224/16225 , H01L2224/16227 , H01L2224/81815 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/30105 , H01L2924/30107 , H01L2924/00
摘要： Power wafer level chip scale package (CSP) and process of manufacture are enclosed. The power wafer level chip scale package includes all source, gate and drain electrodes located on one side of the device, which is convenient for mounting to a printed circuit board (PCB) with solder paste.
摘要翻译：封装了功率晶圆级芯片级封装（CSP）和制造工艺。功率晶片级芯片级封装包括位于器件一侧的所有源极，栅极和漏极，便于用焊膏安装到印刷电路板（PCB）。

2. 发明申请

WO2008118489A1 CHIP SCALE POWER CONVERTER PACKAGE HAVING AN INDUCTOR SUBSTRATE 审中-公开
标题翻译：具有电感基板的芯片尺寸功率转换器封装
公开(公告)号：WO2008118489A1
公开(公告)日：2008-10-02
申请号：PCT/US2008/004032
申请日：2008-03-27
申请人： ALPHA & OMEGA SEMICONDUCTOR LIMITED , HEBERT, Francois , SUN, Ming
发明人： HEBERT, Francois , SUN, Ming
IPC分类号： H01L29/00
CPC分类号： H01L23/645 , H01L23/5227 , H01L2224/16 , H01L2924/00011 , H01L2924/00014 , H01L2924/01019 , H01L2924/0102 , H01L2924/01057 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941 , H01L2924/13091 , H01L2924/1461 , H01L2924/1902 , H01L2924/3025 , Y10T29/4902 , Y10T29/49075 , H01L2924/00 , H01L2224/0401
摘要： A chip scale power converter package having an inductor substrate and a power integrated circuit flipped onto the inductor substrate is disclosed. The inductor substrate includes a high resistivity substrate having a planar spiral inductor formed thereon.
摘要翻译：公开了一种具有电感器基板和翻转到电感器基板上的功率集成电路的芯片级功率转换器封装。电感器基板包括其上形成有平面螺旋电感器的高电阻率基板。

3. 发明申请

WO2007022136A2 IMPROVED TRANSIENT BLOCKING UNIT 审中-公开
标题翻译：改进的瞬时阻塞单元
公开(公告)号：WO2007022136A2
公开(公告)日：2007-02-22
申请号：PCT/US2006/031742
申请日：2006-08-11
申请人： FULTEC SEMICONDUCTOR, INC. , HARRIS, Richard, A. , BLANCHARD, Richard, A. , HEBERT, Francois
发明人： HARRIS, Richard, A. , BLANCHARD, Richard, A. , HEBERT, Francois
IPC分类号： H02H9/06
CPC分类号： H02H9/025
摘要： Improved electrical transient blocking is provided with a transient blocking unit (TBU) having a partial disconnect capability. A TBU is an arrangement of voltage controlled switches that normally conducts, but switches to a disconnected state in response to an above-threshold input transient. Partial disconnection improves the power handling capability of a TBU by preventing thermal damage to the TBU. Partial TBU disconnection can be implemented to keep power dissipation in the TBU below a predetermined level P max , thereby avoiding thermal damage to the TBU by keeping the TBU temperature below a temperature limit T max . Alternatively, partial TBU disconnection can be implemented to keep TBU temperature below T max using direct temperature sensing and feedback.
摘要翻译：提供了具有部分断开能力的瞬态阻塞单元（TBU）的改进的电瞬变阻塞。 TBU是通常导通的电压控制开关的布置，但是响应于高于阈值的输入瞬变而切换到断开状态。部分断开通过防止TBU的热损坏提高了TBU的功率处理能力。可以实施部分TBU断开以将TBU中的功率消耗降低到预定水平P max以下，从而通过将TBU温度保持在温度下限T max以下来避免对TBU的热损伤， SUB>。或者，可以使用直接温度感测和反馈来实现部分TBU断开以将TBU温度保持在T 以下。

4. 发明申请

WO2006116517A2 APPARATUS AND METHOD FOR TRANSIENT BLOCKING EMPLOYING RELAYS 审中-公开
标题翻译：瞬态阻塞使用继电器的装置和方法
公开(公告)号：WO2006116517A2
公开(公告)日：2006-11-02
申请号：PCT/US2006/015841
申请日：2006-04-25
申请人： FULTEC SEMICONDUCTOR, INC. , BLANCHARD, Richard, A. , HARRIS, Richard, A. , HEBERT, Francois
发明人： BLANCHARD, Richard, A. , HARRIS, Richard, A. , HEBERT, Francois
IPC分类号： H02H9/00
CPC分类号： H01J1/72 , C09K11/59 , H01H9/548 , H02H9/025
摘要： An apparatus and a method for uni-directional and bi-directional transient blocking. The uni-directional apparatus has a depletion mode n-channel device at its input and a normally closed relay, e.g., a micro-electro-mechanical (MEM) relay, interconnected with the depletion mode n-channel device and the input in such a way that at a predetermined current value the transient causes the normally closed relay to switch into an open state and produces a bias voltage V n on the depletion mode n-channel device that is sufficiently high to switch it "off" and thus block the transient. An analogous arrangement at the output taking advantage of the same or a second relay renders the apparatus bi-directional. The structure of the apparatus and the method of operation ensure a reliable and repeatable trip current I trip and render the apparatus very robust and feasible for low-cost manufacture.
摘要翻译：用于单向和双向瞬态阻塞的装置和方法。单向设备在其输入端具有耗尽模式n沟道器件和常闭继电器，例如与耗尽型n沟道器件互连的微机电（MEM）继电器，以及在这种在预定电流值下，瞬态使常闭继电器切换到打开状态，并且在耗尽型n沟道器件上产生足够高以切换它的偏置电压V N“ 关闭“，从而阻止瞬态。利用相同或第二中继器的输出处的类似布置使设备双向。该装置的结构和操作方法确保了可靠和可重复的跳闸电流跳闸，并且使得该装置非常坚固且适用于低成本制造。

5. 发明申请

WO2010074842A2 STACKED POWER CONVERTER STRUCTURE AND METHOD 审中-公开
标题翻译：堆叠式电力转换器结构与方法
公开(公告)号：WO2010074842A2
公开(公告)日：2010-07-01
申请号：PCT/US2009/064748
申请日：2009-11-17
申请人： INTERSIL AMERICAS INC. , BELL, David B. , HEBERT, Francois , KELKAR, Nikhil
发明人： BELL, David B. , HEBERT, Francois , KELKAR, Nikhil
IPC分类号： H01L23/12 , H02M3/00
CPC分类号： H01L27/088 , H01L21/26513 , H01L21/823437 , H01L21/823487 , H01L23/535 , H01L23/62 , H01L29/0619 , H01L29/0692 , H01L29/0696 , H01L29/1083 , H01L29/1095 , H01L29/402 , H01L29/4175 , H01L29/41766 , H01L29/41775 , H01L29/456 , H01L29/66659 , H01L29/66681 , H01L29/66696 , H01L29/66712 , H01L29/66734 , H01L29/7802 , H01L29/7806 , H01L29/7811 , H01L29/7813 , H01L29/7816 , H01L29/7835 , H01L2224/48137 , H01L2224/48247 , H01L2224/49171 , H01L2924/12032 , H01L2924/1305 , H01L2924/13055 , H01L2924/13062 , H01L2924/13091 , H01L2924/1461 , H01L2924/30107 , H01L2924/3025 , H02M7/003 , H01L2924/00
摘要： A power converter can include an output circuit having a high-side device and a low-side device which can be formed on a single die (a "PowerDie"). The power converter can further include a controller integrated circuit (IC) formed on a different die which can be electrically coupled to, and co-packaged with, the PowerDie. The PowerDie can be attached to a die pad of a leadframe, and the controller IC die can be attached to an active surface of the first die such that the first die is interposed between the controller IC die and the die pad.
摘要翻译：功率转换器可以包括具有可形成在单个管芯（“PowerDie”）上的高侧器件和低侧器件的输出电路。功率转换器还可以包括形成在不同管芯上的控制器集成电路（IC），其可以与PowerDie电耦合并与其一体化。 PowerDie可以附接到引线框架的管芯焊盘，并且控制器IC管芯可以附接到第一管芯的有效表面，使得第一管芯插入在控制器IC管芯和管芯焊盘之间。

6. 发明申请

WO2006053326A3 INTEGRATED TRANSIENT BLOCKING UNIT COMPATIBLE WITH VERY HIGH VOLTAGES 审中-公开
标题翻译：集成的瞬态阻塞单元兼容非常高的电压
公开(公告)号：WO2006053326A3
公开(公告)日：2010-01-28
申请号：PCT/US2005041416
申请日：2005-11-09
申请人： FULTEC SEMICONDUCTOR INC , HEBERT FRANCOIS , HARRIS RICHARD A
发明人： HEBERT FRANCOIS , HARRIS RICHARD A
IPC分类号： H02H9/00
CPC分类号： H01L27/0266 , H01L27/0727 , H02H9/025 , H02H9/046
摘要： A transient blocking unit (TBU) with integrated over-current protection and discrete over-voltage protection. In one example embodiment, the present innovations are embodied as a unit for protecting a circuit from high voltage and high current, comprising a core transient blocking unit with at least one high voltage device wherein the core transient blocking unit is integrated, and wherein the at least one high voltage device is discrete.
摘要翻译：具有集成过流保护和离散过电压保护的瞬态阻塞单元（TBU）。在一个示例性实施例中，本发明被实施为用于保护电路免受高电压和高电流的单元，其包括具有至少一个高压器件的核心瞬态阻塞单元，其中所述核心瞬态阻塞单元被集成，并且其中，至少一个高压装置是离散的。

7. 发明申请

WO2006053055A3 HIGH-VOLTAGE TRANSISTOR FABRICATION WITH TRENCH ETCHING TECHNIQUE 审中-公开
标题翻译：具有TRENCH蚀刻技术的高压晶体管制造
公开(公告)号：WO2006053055A3
公开(公告)日：2009-04-16
申请号：PCT/US2005040615
申请日：2005-11-09
申请人： FULTEC SEMICONDUCTOR INC , BLANCHARD RICHARD A , HEBERT FRANCOIS
发明人： BLANCHARD RICHARD A , HEBERT FRANCOIS
IPC分类号： H01L21/336
CPC分类号： H01L29/7838 , H01L23/535 , H01L29/0626 , H01L29/0646 , H01L29/0692 , H01L29/1066 , H01L29/2003 , H01L29/4236 , H01L29/4238 , H01L29/808 , H01L2924/0002 , H01L2924/00
摘要： A lateral high-voltage depletion-mode device structure in which fingers of semiconductor material are interdigitated with trench gates. Since the effective channel area is proportional to the depth of the trenches, a large amount of active channel area can be achieved for a given surface area.
摘要翻译：一种横向高压耗尽型器件结构，其中半导体材料的指状物与沟槽栅极交错。由于有效通道面积与沟槽的深度成比例，所以对于给定的表面积可以获得大量的有效沟道面积。

8. 发明申请

WO2008091607A1 CONFIGURATION OF HIGH-VOLTAGE SEMICONDUCTOR POWER DEVICE TO ACHIEVE THREE DIMENSIONALCHARGE COUPLING 审中-公开
标题翻译：配置高压半导体电源器件实现三维尺寸耦合
公开(公告)号：WO2008091607A1
公开(公告)日：2008-07-31
申请号：PCT/US2008/000831
申请日：2008-01-22
申请人： ALPHA & OMEGA SEMICONDUCTOR, LTD. , HEBERT, Francois
发明人： HEBERT, Francois , FENG, Tao
IPC分类号： H01L21/20
CPC分类号： H01L29/7802 , H01L29/0653 , H01L29/66712 , H01L29/7395 , H01L29/7803 , H01L29/861 , H01L29/872
摘要： This invention discloses semiconductor device that includes a top region and a bottom region with an intermediate region disposed between said top region and said bottom region with a controllable current path traversing through the intermediate region. The semiconductor device further includes a trench with padded with insulation layer on sidewalls extended from the top region through the intermediate region toward the bottom region wherein the trench includes randomly and substantially uniformly distributed nano- nodules as charge-islands in contact with a drain region below the trench for electrically coupling with the intermediate region for continuously and uniformly distributing a voltage drop through the current path.
摘要翻译：本发明公开了一种半导体器件，其包括顶部区域和底部区域，其中间区域设置在所述顶部区域和所述底部区域之间，并具有穿过所述中间区域的可控电流通路。所述半导体器件还包括沟槽，该沟槽在从所述顶部区域延伸穿过所述中间区域朝向所述底部区域的侧壁上填充有绝缘层，其中所述沟槽包括随机均匀分布的纳米结节，作为与下面的漏极区域接触的电荷岛用于与中间区域电耦合的沟槽，用于通过电流路径连续均匀地分配电压降。

9. 发明申请

WO2007058799A2 TRANSIENT BLOCKING UNIT HAVING SHUNT FOR OVER-VOLTAGE PROTECTION 审中-公开
标题翻译：具有过压保护的瞬态闭锁单元
公开(公告)号：WO2007058799A2
公开(公告)日：2007-05-24
申请号：PCT/US2006/043102
申请日：2006-11-03
申请人： FULTEC SEMICONDUCTOR, INC. , HARRIS, Richard, A. , HEBERT, Francois
发明人： HARRIS, Richard, A. , HEBERT, Francois
IPC分类号： H02H3/22
CPC分类号： H02H9/025 , H01L27/0266 , H02H9/04
摘要： A transient blocking unit (TBU) having improved damage resistance is provided. A TBU includes two or more depletion mode transistors arranged to provide a low series impedance in normal operation and a high series impedance when the input current exceeds a predetermined threshold. At least one of the TBU transistors is a protecting device having a shunt circuit element connected in parallel with its channel. When the TBU is in its high impedance state, the shunt circuit element provides a current path, thereby decreasing terminal voltages on at least one of the TBU transistors. The shunt element can be a discrete or integrated resistor, a current source including a transistor, or an appropriately engineered device parasitic.
摘要翻译：提供具有改进的抗损伤性的瞬变阻挡单元（TBU）。 TBU包括两个或更多个耗尽型晶体管，其布置成在正常操作中提供低串联阻抗，并且当输入电流超过预定阈值时提供高串联阻抗。至少一个TBU晶体管是具有与其沟道并联连接的分流电路元件的保护装置。当TBU处于其高阻抗状态时，分路电路元件提供电流路径，从而减小至少一个TBU晶体管上的端电压。分流元件可以是分立的或集成的电阻器，包括晶体管的电流源，或适当设计的寄生器件。

10. 发明申请

WO2006053025A2 APPARATUS AND METHOD FOR TEMPERATURE-DEPENDENT TRANSIENT BLOCKING 审中-公开
标题翻译：用于温度依赖性瞬态阻塞的装置和方法
公开(公告)号：WO2006053025A2
公开(公告)日：2006-05-18
申请号：PCT/US2005/040555
申请日：2005-11-09
申请人： FULTEC SEMICONDUCTOR, INC. , HARRIS, Richard, A. , COATES, Stephen , HEBERT, Francois
发明人： HARRIS, Richard, A. , COATES, Stephen , HEBERT, Francois
IPC分类号： H02H1/00
CPC分类号： H02H5/044 , H02H5/042 , H02H9/025
摘要： An apparatus and method for temperature-dependent transient blocking employing a transient blocking unit (TBU) that uses at least one depletion mode n-channel device interconnected with at least one depletion mode p-channel device. The interconnection is performed such that a transient alters a bias voltage V p of the p-channel device and a bias voltage V n of the n-channel device in concert to effectuate their mutual switch off to block the transient. The apparatus has a temperature control unit that is in communication with the TBU and adjusts at least one of the bias voltagesV P, V n in response to a sensed temperature T 5 , thereby enabling the apparatus to also respond to over-temperature. In some embodiments the p-channel device is replaced with a positive temperature coefficient thermistor (PTC). The temperature control unit can use any suitable circuit element, including, among other a PTC, resistor, negative temperature coefficient element, positive temperature coefficient element, transistor, diode.
摘要翻译：一种采用使用与至少一个耗尽型p沟道器件互连的至少一个耗尽型n沟道器件的瞬态阻断单元（TBU）的温度依赖性瞬态阻塞的装置和方法。执行互连，使得瞬态改变p沟道器件的偏置电压V SUB p N和N沟道器件的偏置电压V N n N一致地实现他们的相互关闭来阻止瞬态。该装置具有与TBU通信的温度控制单元，并且响应于感测到的温度T 5 ，从而使得该装置也能够对过温作出响应。在一些实施例中，用正温度系数热敏电阻（PTC）代替p沟道器件。温度控制单元可以使用任何合适的电路元件，包括PTC，电阻器，负温度系数元件，正温度系数元件，晶体管，二极管等。

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