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1. 发明申请

WO2007133612A2 HIGH VOLTAGE SEMICONDUCTOR DEVICE WITH LATERAL SERIES CAPACITIVE STRUCTURE 审中-公开
标题翻译：具有横向串联电容结构的高压半导体器件
公开(公告)号：WO2007133612A2
公开(公告)日：2007-11-22
申请号：PCT/US2007/011263
申请日：2007-05-11
申请人： FULTEC SEMICONDUCTOR, INC. , DARWISH, Mohamed, N. , YANG, Robert, Kuo-Chang
发明人： DARWISH, Mohamed, N. , YANG, Robert, Kuo-Chang
IPC分类号： C09K8/60
CPC分类号： H01L29/7835 , H01L29/0634 , H01L29/0692 , H01L29/407 , H01L29/66659
摘要： According to the present invention, semiconductor device breakdown voltage can be increased by embedding field shaping regions within a drift region of the semiconductor device. A controllable current path extends between two device terminals on the top surface of a planar substrate, and' the controllable current path includes the drift region. Each field shaping region includes two or more electrically conductive regions that are electrically insulated from each other, and which are capacitively coupled to each other to form a voltage divider dividing a potential between the first and second terminals. One or more of the electrically conductive regions are isolated from any external electrical contact. Such field shaping regions can provide enhanced electric field uniformity in current-carrying parts of the drift region, thereby increasing device breakdown voltage.
摘要翻译：根据本发明，可以通过在半导体器件的漂移区域内嵌入场成形区域来增加半导体器件击穿电压。可控电流路径在平面基板的顶表面上的两个器件端子之间延伸，并且“可控电流路径包括漂移区域。每个场整形区域包括彼此电绝缘并且彼此电容耦合以形成分压第一和第二端子之间的电势的分压器的两个或更多个导电区域。一个或多个导电区域与任何外部电触点隔离。这种场成形区域可以在漂移区域的载流部分中提供增强的电场均匀性，从而增加器件击穿电压。

2. 发明申请

WO2006122328A2 INCREASING BREAKDOWN VOLTAGE IN SEMICONDUCTOR DEVICES WITH VERTICAL SERIES CAPACITIVE STRUCTURES 审中-公开
标题翻译：在具有垂直系列电容结构的半导体器件中增加断开电压
公开(公告)号：WO2006122328A2
公开(公告)日：2006-11-16
申请号：PCT/US2006/018922
申请日：2006-05-11
申请人： FULTEC SEMICONDUCTOR, INC. , YANG, Robert, Kuo-Chang , HEBERT, Francois
发明人： YANG, Robert, Kuo-Chang , HEBERT, Francois
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L29/7802 , H01L29/407 , H01L29/4236 , H01L29/7395 , H01L29/74 , H01L29/7803 , H01L29/7811 , H01L29/7813 , H01L29/861
摘要： This invention relates to an apparatus and method for achieving high breakdown voltage and low on-resistance in semiconductor devices that have top, intermediate and bottom regions with a controllable current path traversing any of these regions. The device has an insulating trench that is coextensive with the top and intermediate regions and girds these regions from at least one side and preferably from both or all sides. A series capacitive structure with a biased top element and a number of floating elements is disposed in the insulating trench, and the intermediate region is endowed with a capacitive property that is chosen to establish a capacitive interaction or coupling between the series capacitive structure and the intermediate region so that the breakdown voltage VBD is maximized and on- resistance is minimized. The capacitive property of the intermediate region is established by an appropriately chosen material constitution and is further controlled by a predetermined constitution of the insulating trench. The apparatus and method of invention are useful in any number of semiconductor devices including, among other, transistors, bipolar transistors, MOSFETs, JFETs, thyristors and diodes.
摘要翻译：本发明涉及一种用于实现半导体器件中的高击穿电压和低导通电阻的装置和方法，所述半导体器件具有穿过任何这些区域的可控电流路径的顶部，中间和底部区域。该装置具有与顶部和中间区域共同延伸的绝缘沟槽，并且从至少一个侧面，优选地从两侧或全部侧面将这些区域线化。具有偏置顶部元件和多个浮动元件的串联电容结构设置在绝缘沟槽中，并且中间区域具有被选择用于建立串联电容结构和中间体之间的电容性相互作用或耦合的电容性质使得击穿电压VBD最大化并且导通电阻最小化。通过适当选择的材料结构建立中间区域的电容性质，并通过绝缘沟槽的预定结构进一步控制。本发明的装置和方法可用于任何数量的半导体器件，其中包括晶体管，双极晶体管，MOSFET，JFET，晶闸管和二极管。

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