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1. 发明专利

JPS60198942A REMOTE MAGNETIC TAPE CONTROL SYSTEM 失效
公开(公告)号：JPS60198942A
公开(公告)日：1985-10-08
申请号：JP5342684
申请日：1984-03-22
申请人： NIPPON ELECTRIC CO , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , HITACHI LTD , FUJITSU LTD
发明人： YAMAGUCHI KENJI , KAMEI KIMIAKI , SUZUKI KAZUO , KITAZAWA MITSURU , HONMA TOMOAKI
IPC分类号： H04L29/08 , H04L13/00
摘要： PURPOSE:To improve the operating efficiency and reliability for a system by separating a response signal to command information and a data request signal driving a magnetic tape to retransmit data. CONSTITUTION:A controller 1 of a remote magnetic tape control system and a line terminator 2 are provided to a reception side, the terminator 2 receives a signal from the controller 1 and converts the signal to the signal system suitable for transmission, and then the result is transmitted to a communication line 3 and a signal from the line 3 is restored to the original signal and the result is given to the terminator 2 conversely. A magnetic tape controller 5 connected to a magnetic tape device 6 is connected to the other end of the line 3 via a line terminator 4 at the transmission side to constitute the data transmission side. The terminator 4 converts the transmission signal received via the line 3 into the original signal from the controller 1 and the signal is given to the controller 5, and the signal transmitted from the controller 5 is converted into a signal of the signal system suitable for transmission conversely and the result is transmitted to the line 3. Then the controllers 1, 5 separate the response signal and the signal driving a tape.

2. 发明专利

JPS60134355A SYSTEM STATE DISPLAYING SYSTEM 失效
公开(公告)号：JPS60134355A
公开(公告)日：1985-07-17
申请号：JP23978083
申请日：1983-12-21
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , FUJITSU LTD
发明人： KITAZAWA MITSURU , KANAO SEIICHI , TAKEUCHI AKIHIRO , IGAWA IKUTOSHI , FUKUMOTO KOUICHIROU
IPC分类号： H04Q3/545 , G06F11/32
摘要： PURPOSE:To shorten the time required for a retrieval and a preservation work of a faulty part by providing a flip-flop for holding a system fault at every system fault, and an indicator, and displaying the cause of a falut when an EMA circuit has been started. CONSTITUTION:In case a system fault A is detected, it is converted to a pulse signal by a differentiating circuit 1, held by a flip-flop 11, and the system fault a is displayed by a display device 14. Reset of the flip-flop 11 is generated by a software instruction of a central control device 15 or a key operation, and executed through a reset signal line 16. With regard to system faults B, C and other fault, too, they can be explained in the same way.

3. 发明专利

JPS60236560A AUTOMATIC TEST SYSTEM FOR EMERGENCY CONTROL CIRCUIT 失效
公开(公告)号：JPS60236560A
公开(公告)日：1985-11-25
申请号：JP9324884
申请日：1984-05-10
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , HITACHI LTD , OKI ELECTRIC IND CO LTD
发明人： TACHIKA SHINJI , KAMEI KIMIAKI , HONDA KENICHI , ONOZUKA TOMOJI , KITAZAWA MITSURU
IPC分类号： H04Q3/545 , H04M3/22 , H04M3/24 , H04M3/26
摘要： PURPOSE:To perform an automatic test of an emergency control circuit with high efficiency and with no discontinuance of the call processing, by providing a gate circuit which is separated from a using system, executing the test of the emergency control circuit along a start route by the signal given from a microprogram control circuit and deciding the test result by a deciding circuit. CONSTITUTION:For a test of a start route, either one of signals muDV9 and muDV10 is supplied to the differential pulse generating circuits DP4 and DP5 via gate circuits G21 and G22. The ouput pulses of circuits DP4 and DP5 are supplied to an emergency control EMA clock generating circuit CKG via gate circuits G23 and G6. A deciding circuit JG decides a normal or faulty state. If a using system has a fault during a test start signal given from another system (mate system) is applied to gate circuit G12 and G14. Then flip-flot FF5 is set and this set output is turned into the reset signal of an FF6 via gate circuits G15 and G28 and also applied to an automatic test control circuit ATC. Thus the ATC discontinues its test.

4. 发明专利

JPS60140967A DATA PROCESSOR 失效
公开(公告)号：JPS60140967A
公开(公告)日：1985-07-25
申请号：JP25220883
申请日：1983-12-27
申请人： NIPPON ELECTRIC CO , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , HITACHI LTD , FUJITSU LTD
发明人： YAMAGUCHI KENJI , HATANO HAJIME , SUZUKI TAKAO , KITAZAWA MITSURU , TSUCHIDA SHINOBU
IPC分类号： H04M3/22
摘要： PURPOSE:To collect and classify state information and control information of plural exchange stations into a file memory of one supervisory center by providing a means fetching a transmission/reception data of a terminal device in the supervisory center to a system and a means transmitting the fetched transmission/reception data. CONSTITUTION:When a detection circuit 32 detects an STX code being the start of data, a gate circuit 33 is opened and a data succeeding to the STX code is stored from an output of a serial/parallel converting circuit 31 to a buffer register 34 in the unit of bytes. An information processing system 22 starts a control program by an interruption signal and transmits a read command of data to data processors 21a and 21b. When an ETX code being the end of data is detected by the detection circuit 32, the gate circuit 33 is closed so as to inhibit the succeeding data from being stored in the buffer register 34. The operation is repeated by the detection of the STX so as to store all the data transmitted/received by the terminal devices 14a, 14b to a large capacity file memory 23 of a supervisory center 20.

5. 发明专利

JPS60113560A CONSOLE ADDER 失效
公开(公告)号：JPS60113560A
公开(公告)日：1985-06-20
申请号：JP22069883
申请日：1983-11-25
申请人： OKI ELECTRIC IND CO LTD , NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , HITACHI LTD , FUJITSU LTD
发明人： SUZUKI TAKAO , HATANO HAJIME , IGAWA IKUTOSHI , KITAZAWA MITSURU , KANAZAWA NOBUHARU
IPC分类号： H04M3/22 , H04Q1/26
摘要： PURPOSE:To facilitate trouble countermeasures and to obtain speedy recovery by providing a console adder which transfers automatically trouble data to a normal host station by an emergency control circuit when a central processor of an unmanned electronic switching place is in trouble. CONSTITUTION:While the system of an electronic exchange, etc., is operating on on-line basis, a CPU3 executes the on-line operation under program control by a main storage device 1 and by the self-control operation of a data channel device 5 by setting a file memory device 7 and a typewriter device 8 as I/O devices. When a trouble occurs, the internal condition of the CPU3 is readout by a console adder 11 to the host station maintained by an operator, and the display data is accumulated and editted. The data is transferred through an interface 12 which is connected to the host station regarding the data as I/O data falsely, and are typed out by the host station. In the host station, the rising of an unmanned station is executed by remote-controlling by the data.

6. 发明专利

JPS60199294A TRIP SYSTEM OF OVERCURRENT PROTECTING DEVICE 失效
公开(公告)号：JPS60199294A
公开(公告)日：1985-10-08
申请号：JP5445584
申请日：1984-03-23
申请人： OKI ELECTRIC IND CO LTD , NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , HITACHI LTD , FUJITSU LTD
发明人： TAGUCHI OSAO , KANAO SEIICHI , OSAKABE YOSHITAKA , KITAZAWA MITSURU , TSUCHIDA SHINOBU
IPC分类号： H04Q1/28 , H04M3/18
摘要： PURPOSE:To shut off automatically and sequentially a current protecting device of an electronic exchange by providing a control circuit for controlling an overcurrent protecting device and a timing circuit which drives at every certain interval when it receives a start signal from the outside. CONSTITUTION:A trip action of an overcurrent protecting device (NFB)5 is as follows: when a power source of negative 48V is shut off in a power chamber 4a, or when a key OP is operated; a relay A, a relay B and a relay W are sequentially actuated. A relay C is restored by the action of the relay B. The relays B and C alternately repeat the action and restoration accordingly. Moreover, a relay X is actuated due to the restoration of the relay B. While the relay B performs the action and the restoration twice, the relays W and X act one time. A control of the NFB5 is as follows: the relays W and X act alternately due to the action of the relay B, and operate from a relay 10 to (n) by a certain interval. At this point an earth closed circuit across an exchange 6 of negative 48V, a contact point 10c, the NFB5 and the power chamber 4 is formed by the action of the contact point 10c. A coil of the NFB5 releases a contact point 5a in said circuit. As a result, a power source unit 3 stops supply of a power source to a load circuit 2.

7. 发明专利

JPS6075943A INFORMATION COLLECTING SYSTEM 失效
公开(公告)号：JPS6075943A
公开(公告)日：1985-04-30
申请号：JP18418383
申请日：1983-09-30
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , HITACHI LTD
发明人： INOUE SABUROU , KANAO SEIICHI , TAKEUCHI AKIHIRO , YAMAGUCHI KENJI , KITAZAWA MITSURU
IPC分类号： H04Q3/54 , G06F11/07 , G06F11/20
摘要： PURPOSE:To understand quickly and assuredly the state when a fault is produced by collecting the automatically the fault information from a central processor under the same conditions as a console when an emergency control action is started for the start of a system. CONSTITUTION:An additional adaptor ADP is put between central controllers CC0 and CC1 as well as between consoles CNS0 and CNS1 respectively. The commands are supplied to controllers CC0 and CC1 under the same conditions as consoles CNS0 and CNS1. A fault information collection control circuit SPV receives the information which is extracted from the CC0 and CC1 under the same conditions as the CNS0 and CNS1. The desired fault information showing the state of the inside of a central processor when an emergency control circuit EMA is started are all collected by the circuit SPV while they are reserved by the CC0 and CC1 as well as main memories MM0 and MM1.

8. 发明专利

JPS59132488A Revising system of line name of magnetic bubble 失效
标题翻译：磁性气泡线名称修正系统
公开(公告)号：JPS59132488A
公开(公告)日：1984-07-30
申请号：JP796183
申请日：1983-01-20
申请人： Fujitsu Ltd , Hitachi Ltd , Nec Corp , Nippon Telegr & Teleph Corp , Oki Electric Ind Co Ltd
发明人： TACHIKA SHINJI , KAMEI KIMIAKI , SAKATA HIRONOBU , KITAZAWA MITSURU , NOGUCHI OSAMU
IPC分类号： G11C11/14
CPC分类号： G11C11/14
摘要： PURPOSE:To reduce time required for the processing of write and revision of line name by disconnecting a magnetic bubble storage device and a magnetic bubble storage device controller from other devices, especially a central controller to attain the test of the normality of the devices and to attain write and revision of line name. CONSTITUTION:When a magnetic bubble storage device controller MBCH receives a magnetic bubble storage device controller number from the central controller CC via a line CHN and an instruction from a line ODR, and when the said number is coincident with the own number, the MBCH is operated by the said instruction. The address of a main storage device MM storing the required data is calculated and fed to a line MAD-BUS (memory address bus), a required data is read from the main storage device MM and the MBCH performs prescribed operations such as write of designated data to a designated address of a magnetic bubble storage device MBU, read of data from the designated address and transfer of it to the main storage device by reading the required data transmitted from the main storage device MM based on the data transmitted via gates 2, 51 from the line DATA-BUS.
摘要翻译：目的：通过将磁性气泡存储装置和磁性气泡存储装置控制器与其他装置，特别是中央控制器断开连接，以减少对线路名称的写入和修改所需的时间，以实现对装置的正常性的测试，以及达到线路名称的修改和修改。构成：当磁性气泡存储装置控制器MBCH经由线路CHN从中央控制器CC接收到磁性气泡存储装置控制器号码和来自线路ODR的指令时，并且当所述数量与自身号码一致时，MBCH为由该指令操作。计算存储所需数据的主存储装置MM的地址并将其馈送到线路MAD-BUS（存储器地址总线），从主存储装置MM读取所需的数据，并且MBCH执行诸如指定的写入的规定操作数据到磁性气泡存储装置MBU的指定地址，从指定地址读取数据并通过从主存储装置MM发送的数据读取从主存储装置MM发送的所需数据，将其传送给主存储装置， 51线从DATA-BUS线。

9. 发明专利

JPS58101360A DATA PROCESSOR 失效
公开(公告)号：JPS58101360A
公开(公告)日：1983-06-16
申请号：JP20015881
申请日：1981-12-14
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： KITAZAWA MITSURU , MIKI SHIYUUJI , MASUO KAZUYUKI
IPC分类号： G06F9/48 , G06F9/46 , G06F15/17
摘要： PURPOSE:To simplify the operation and to eliminate the time difference between communications, by providing a means which gives simultaneous interruption from one set of a central processor to other central processors, in a data processor comprising a plurality of central processors. CONSTITUTION:A data processor comprises a plurality of central processors CPUs 11, 12...1n. When simultaneous interruption is provided from a CPU (e.g., 11) to the other CPUs 12-1n, an interruption start circuit 21 is started, and level 1 is set to specific bits 72-7n of interruption registers 62-6n via gates 52-5n of the CPUs 12-1n on an interruption start signal line 31. Thus, interruption processing sections 82-8n of the CPUs 12-1n execute interruption processing. Further, the CPU11 inhibits the input of a gate 51 to an interruption register 61 with a signal on an interruption inhibit line 41. Thus, simultaneous interruption from each CPU to the other CPUs can be done, the operation can be simplified and the communication time can be arranged.

10. 发明专利

JPS58101361A DATA PROCESSOR 失效
公开(公告)号：JPS58101361A
公开(公告)日：1983-06-16
申请号：JP20016181
申请日：1981-12-14
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： KITAZAWA MITSURU , WAKIMURA YOSHIAKI
IPC分类号： G06F15/16 , G06F15/17 , G06F15/177
摘要： PURPOSE:To decrease the number of signal lines between device and to designate the start or stop operation at the same time, by corresponding each bit in a conventional register to other central processors and forming device designating information. CONSTITUTION:A central processor 111 sets 1 to a bit designating a central processor 112 of a conventional data register 121. In executing a start operation instruction for the other device, a start operation circuit 161 of the other device is activated to set a flip-flop 172. Simultaneously, the content of the register 121 is transferred to a conventional data register 122 of the processor 112. The processor 112 collates the register 122 and a fixed pattern generating circuit 142 at a collation circuit 132, and when the contents are coincident, an AND condition with the output of the flip-flop 172 at a gate 182 is established and a start operation circuit 192 is started.

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