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1. 发明专利

JPS57113170A INTERPROCESSOR CONTROL CIRCUIT 失效
公开(公告)号：JPS57113170A
公开(公告)日：1982-07-14
申请号：JP18911580
申请日：1980-12-29
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , HITACHI LTD
发明人： FUKUI TOSHIMASA , SAITOU ISAO , MURATA NAOMITSU , KAJIZUKA SHIYOUJI , AOKI TOSHIROU , DEWA HIROSHI
IPC分类号： G06F15/16 , G06F12/00 , G06F15/17 , G06F15/177
摘要： PURPOSE:To reduce lines and hardware and to achieve economization by writing control contents in the main storage device of a processor to be controlled, and permitting the processor to be controlled to read the control contents by microprogram processing and to exercise specified control. CONSTITUTION:The processors PE1 and PE2 of a data processing system which has the processors with functions by microprogram control are provided with individual main storage devices MEM1 and MEM2, and means of writing data in the main storage device of the other processors. When one processor controls the setting of the internal state of the other processor and the reading operation, said processor writes control contents in a prescribed address of the main storage device MEM of the other processor to be controlled, and starts the microprogram of the processor to be controlled, which reads the control contents written in the prescribed address by microprogram processing and analyzes them to exercise specified control.

2. 发明专利

JPS5687129A EXECUTION ORDER CONTROLLING SYSTEM OF MICROPROGRAM FOR DATA PROCESSOR 失效
公开(公告)号：JPS5687129A
公开(公告)日：1981-07-15
申请号：JP6818780
申请日：1980-05-22
申请人： NIPPON ELECTRIC CO , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , HITACHI LTD , FUJITSU LTD
发明人： ONODERA HIROSHI , AMADA HIROYUKI , KAJIZUKA SHIYOUJI , HIRAI FUMIO , UYAMA KATSUO
IPC分类号： G06F9/26 , G06F3/00 , G06F9/22 , G06F13/12
摘要： PURPOSE:To ensure an extremely efficient execution order control for the microprogram, by securing the conditions between the test pattern of the microprogram word and the state of the circuit to be controlled by utilizing the arithmetic bus for operation of the general data and the general arithmetic circuit. CONSTITUTION:Both the test pattern 11 and the control field are provided to the microprogram word to control the execution order of the microprogram and control each action respectively. Then the test pattern information of the microprogram word plus the state information showing each state of the circuit to be controlled are connected to the arithmetic buses A and B which are used for the general data operation. Then this pattern plus the contents of the FF group 20 holding the circuit state information are given to the general arithmetic circuit 12 via the bus A to carry out the logic arithmetic of the both such as an AND operation. According to the result of the operation, the execution order is controlled for the microprogram. In such way, the execution order control can be carried out for the microprogram in an extremely efficient way.

3. 发明专利

JPS5451438A CONTROL SYSTEM FOR SYSTEM FAILURE DETECTION 失效
公开(公告)号：JPS5451438A
公开(公告)日：1979-04-23
申请号：JP11801277
申请日：1977-09-30
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , HITACHI LTD
发明人： URUSHIBARA TETSUO , USHIKI TATSUO , MASUO KAZUYUKI , KAJIZUKA SHIYOUJI , YAZAWA KATSUHIKO , SHIYOUDA AKIO
IPC分类号： G06F11/20 , G06F11/00 , G06F11/30 , G06F15/16 , G06F15/177
摘要： PURPOSE:To establish the system enabling the detection control of the system failure surely with a simple constitution, by providing two sets of pulses to each of the information processors of a plurality of master and slave relation and by performing the execution of processing with a given program. CONSTITUTION:The pulse counters 30, 70 and the pulse counter 31 are periodically and respectively reset with the program of the unit 10 of the operation system and the signal 90. If program runaway is taken place with the system failure, the counters 30 and 31 are both overflowed and the overflow signals 50 and 51 start the emergency control circuit 6. Simultaneously, the counter 70 is overflown, FF4 of the preparation system is set and the occurrence of failure of the operation system is set and the occurrence of failure of the operation system is displayed. If the failure in the unit of the operation system is taken place, the counter 3 is inoperative, and since no reset signal is fed to the counter 31, overflow is caused. Only the signal 51 is takne place, starting the circuit 6. If the system failure is taken place during operation of the preparation system 11, the display FF40 is set with the signal 81 and the processing is started with the diagnostic program.

4. 发明专利

JPS5425643A DATA CHANNEL CLEAR SYSTEM 失效
公开(公告)号：JPS5425643A
公开(公告)日：1979-02-26
申请号：JP9032077
申请日：1977-07-29
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , FUJITSU LTD
发明人： FURUKAWA KAZUO , HATA MASANARI , KAJIZUKA SHIYOUJI , OOKAWA KAZUMASA , AWAJI TOSHIO
IPC分类号： G06F13/00 , G06F3/00
摘要： PURPOSE:To reduce the clear time to fractions of conventional time, to reduce the programming man-hours, and to make easy for the operation at debugging, by constituting the channel word region clear signal with a hardware.

5. 发明专利

JPS5450248A CONTROL SYSTEM FOR DATA CHANNEL UNIT 失效
公开(公告)号：JPS5450248A
公开(公告)日：1979-04-20
申请号：JP11554877
申请日：1977-09-28
申请人： OKI ELECTRIC IND CO LTD , NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , HITACHI LTD , FUJITSU LTD
发明人： KAJIZUKA SHIYOUJI , MURATA TATSUTOSHI , HANIBUCHI KENICHI , OOKAWA KAZUMASA , SHIYOUDA AKIO , AWAJI TOSHIO
IPC分类号： G06F13/12 , G06F3/00 , G06F13/00
摘要： PURPOSE:To make data transfer high-speed by reading out the first one word of transfer data from a memory to a buffer at an operation start time and correcting the number of transfer words and the address in the main memory of transfer data in the unit which controls data transfer between the main memory and I/O devices. CONSTITUTION:In the control system where data channel unit 4 for controlling data transfer between main memory 3 and plural I/O devices 5 and memory control circuit 2 are provided, the first word of data is loaded to buffer register 6 in data channel unit 4 at an operation start time, and transfer word register 10 and data address register 11 are beforehand corrected. Then, fractional data or look-ahead data is stored in data buffer 15 at a transfer interrupt time, and the complication of update of transfer byte storing register 18 and data address register 11 at a transfer time is canceled. Then, the transfer control is made simple, and the decision processing is reduced to make transfer high-speed.

6. 发明专利

JPS5344132A IO INTERFACE CONTROL SYSTEM 失效
公开(公告)号：JPS5344132A
公开(公告)日：1978-04-20
申请号：JP11969376
申请日：1976-10-04
申请人： NIPPON ELECTRIC CO , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , HITACHI LTD , FUJITSU LTD
发明人： OOKAWA KAZUMASA , AMADA HIROYUKI , KAJIZUKA SHIYOUJI , FURUKAWA KAZUO , YASUI YUTAKA
IPC分类号： G06F9/26 , G06F3/00 , G06F9/22 , G06F13/12
摘要： PURPOSE:Control discrimination signals from a peripheral equipments are tested by a microprogram and then, the control of the peripheral equipments by the microprogram can be carried out to make it possible to connect the peripheral equipments which differ control operations and control signals each other to the same data processing unit, thereby using the system economically efficiently.

7. 发明专利

JPS58112126A INCORPORATING SYSTEM OF CHANNEL WORD MEMORY 失效
公开(公告)号：JPS58112126A
公开(公告)日：1983-07-04
申请号：JP21567181
申请日：1981-12-24
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , HITACHI LTD
发明人： YASUI YUTAKA , ITOU YOSHITAKA , KAJIZUKA SHIYOUJI , OOKAWA KAZUMASA , TAKI YOSHIHARU
IPC分类号： G06F13/12
摘要： PURPOSE:To minimize a data channel, by deleting an unnecessarily excessive storage capacity out of a channel word memory incorporated into a data channel device and setting the channel word memory to a scale that can store the minimum necessary number of channel words for a practical use. CONSTITUTION:A data channel device 3 collates the received device address with a registered device address through a device address registering/collating part 6. If coincidence is obtained with either one of registered device addresses, the channel word CHWJ corresponding to the coincident registered address within an incorporated channel word memory 5 is read out of a control part 7 and fed to an arithmetic part 8 as well as to be stored in a register. The information stored in the register is replaced with another information as the input/output operation proceeds. Then this stored information is stored at a prescribed region of the memory 5 as soon as a series of control operations is over with a data channel device 30 or 31.

8. 发明专利

JPS5356935A PREFERENCE CIRCUIT 失效
公开(公告)号：JPS5356935A
公开(公告)日：1978-05-23
申请号：JP13053876
申请日：1976-11-01
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , FUJITSU LTD
发明人： SHIYOUDA AKIO , WAKABAYASHI HARUO , KAJIZUKA SHIYOUJI , TOJIYAMA TAKASHI , YASUI YUTAKA
IPC分类号： G06F9/48 , G06F3/00 , G06F13/362
摘要： PURPOSE:To obtain a preference circuit performing the priority selection mathced to the actual emergency from the standpoints of micro and macro requirement souces, by adding a small quantity of hardware.

9. 发明专利

JPS5760424A Data transfer controller 失效
标题翻译：数据传输控制器
公开(公告)号：JPS5760424A
公开(公告)日：1982-04-12
申请号：JP13626480
申请日：1980-09-30
申请人： Fujitsu Ltd , Hitachi Ltd , Nec Corp , Nippon Telegr & Teleph Corp , Oki Electric Ind Co Ltd
发明人： AWAJI TOSHIO , HISHINUMA CHIAKI , MIKI SHIYUUJI , KAJIZUKA SHIYOUJI , SEO TOMIHIDE , DEWA HIROSHI
IPC分类号： G06F13/36 , G06F13/40 , G06F15/16 , G06F15/173
CPC分类号： G06F13/4027
摘要： PURPOSE:To increase a data transfer speed, by operating both buses in parallel, when controlling a data transfer of a processor group coupled with a high-speed bus, and a processor group coupled with a low speed bus. CONSTITUTION:Processors CP1-CPn are coupled with a high speed bus IPBH, processors NP1-NPn are coupled with a low-speed bus IPBL, and both the buses are coupled with a data transfer controller IPC, and are divided into two systems by the device IPC. The device IPC is provided with a high-speed bus access control means and a low-speed bus access control means, and when data is transferred between CPi (i=1-n) and NPk (k=1-n), both the bus access control means are operated in parallel. In this way, the transfer time is shortened.
摘要翻译：目的：当控制与高速总线耦合的处理器组的数据传输以及与低速总线耦合的处理器组时，通过并行操作两个总线来提高数据传输速度。规定：处理器CP1-CPn与高速总线IPBH耦合，处理器NP1-NPn与低速总线IPBL耦合，两个总线与数据传输控制器IPC耦合，并被分为两个系统设备IPC。设备IPC设置有高速总线访问控制装置和低速总线访问控制装置，并且当在CPi（i = 1-n）和NPk（k = 1-n）之间传送数据时，总线访问控制装置并行操作。以这种方式，缩短了传送时间。

10. 发明专利

JPS5783837A Information processor 失效
标题翻译：信息处理器
公开(公告)号：JPS5783837A
公开(公告)日：1982-05-25
申请号：JP15827280
申请日：1980-11-12
申请人： Fujitsu Ltd , Hitachi Ltd , Nec Corp , Nippon Telegr & Teleph Corp , Oki Electric Ind Co Ltd
发明人： IKUTA AKIRA , SUYAMA MASATO , KAJIZUKA SHIYOUJI , OKA HIROSHI , ISHIKAWA TAKAHARU
IPC分类号： G06F13/14 , G06F9/46 , G06F13/36 , G06F13/37
CPC分类号： G06F13/36
摘要： PURPOSE:To transmit signals to a control circuit surely, by requesting the access through signal lines of two systems in the information processoring device where access request signals of plural processors are cascaded. CONSTITUTION:Request signals are generated from respective request generating circuits 2-1-2-n of n-number processor 1-1-1-n and are sent to a control circuit 8 from request circuits 3-1-3-n and 4-1-4-n through common signal lines 5-7 and 10-15. When the request signal exists on either of signal lines 7 and 15, a receiving circuit 9 is operated. Consequently, even if any processor, for example, the processor 1-2 becomes faulty and the power source is turned off, signals are transmitted surely to control circuits 3-1 and 4-3-4-n of other processors 1-1 and 1-3-1-n.
摘要翻译：目的：通过请求通过信号处理设备中的两个系统的信号线进行信号传输到控制电路，其中级联多个处理器的访问请求信号。构成：从n号处理器1-1-1-n的各个请求发生电路2-1-2-n生成请求信号，并从请求电路3-1-3-n和4发送到控制电路8 -1-4-n通过公共信号线5-7和10-15。当请求信号存在于信号线7和15中的任何一个时，接收电路9被操作。因此，即使处理器（例如处理器1-2）变得有故障并且电源被断开，也可以将信号可靠地发送到其他处理器1-1和...的控制电路3-1和4-3-4-n， 1-3-1-n。

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