专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JPH09331326A ALARM CELL DETAILED INFORMATION OUTPUT DEVICE 失效
公开(公告)号：JPH09331326A
公开(公告)日：1997-12-22
申请号：JP15082996
申请日：1996-06-12
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NEC CORP , HITACHI LTD
发明人： ONO HIDEAKI , TAKAGI KOJI , NAGATO YUJI , OZAKI TATSU , MORIZAKI SHIGEKI , MIYAO NORIMASA
IPC分类号： H04Q3/00 , H04L12/24 , H04L12/26 , H04L12/28
摘要： PROBLEM TO BE SOLVED: To output detailed information of a fault to an external device on request of a maintenance personnel. SOLUTION: An alarm cell detection section 51 identifies an operation and management (OAM) alarm cell from other cells and stores details information of the alarm cell to a detailed information storage section 53 for each connection. When the detailed information is requested from an external device 40 in this state, an external interface 54 reads the detailed information stored in the detailed information storage section 53 and sends the information to the external device 40 to inform it to the maintenance personnel. When a connection to be captured is instructed from the external device 40 via an external interface 64, an alarm cell detection section 61 extracts an alarm cell (by one cell) of the connection subject to capture instruction and stores it to a latch circuit 63. When the detailed information by one cell is latched in the latch circuit 63, the external interface section 64 sends it to the external device 40 to inform it immediately to the maintenance personnel.

2. 发明专利

JPH09149044A ALARM CELL PROCESSOR 失效
公开(公告)号：JPH09149044A
公开(公告)日：1997-06-06
申请号：JP30750595
申请日：1995-11-27
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NEC CORP , HITACHI LTD
发明人： ONO HIDEAKI , TAKAGI KOJI , ITODA JUN , MISEKI TOMOYUKI , MORIZAKI SHIGEKI , KOBASHI ICHIRO
IPC分类号： H04Q3/00 , H04L12/24 , H04L12/26 , H04L12/28
摘要： PROBLEM TO BE SOLVED: To prevent increase in a load of network processing due to mis- discrimination of an ATM connection state caused by the effect of production of a physical layer fault and due to a notice processing undesired attended with a transmission line fault restored immediately in the fault monitor of the ATM connection with respect to an OAM(operation and maintenance) function in the ATM(asynchronous transmission mode) exchange technology. SOLUTION: This processor 100 monitors an arrival state of an alarm cell as to each ATM connection and discriminates an ATM connection receiving an alarm cell at a time interval within a prescribed time to be an alarm state and an ATM connection not receiving an alarm cell over a prescribed time to be a normal state based on the result of monitor. When a fault of a physical layer with respect to the ATM connection discriminated to be in an alarm state is detected, the ATM connection is discriminated to be in an alarm state regardless of the result of a monitor till the fault is recovered.

3. 发明专利

JPH10336183A ATM CELL SELECTOR AND PACKET SELECTOR 失效
公开(公告)号：JPH10336183A
公开(公告)日：1998-12-18
申请号：JP13819397
申请日：1997-05-28
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： TAKECHI RYUICHI , KATO TSUGIO , ONO HIDEAKI , TAMURA MOTOI , ISHINO FUMIAKI
IPC分类号： H04Q3/00 , H04L12/28
摘要： PROBLEM TO BE SOLVED: To perform directional path selection of an ATM cell for each call or each cell by means of an ATM cell selector that permits only an ATM cell to pass through that is inputted from a specific directional path from among ATM cells that are inputted from plural directional paths. SOLUTION: An extracting means 10 provided in accordance with each directional path extracts selection information that is set to a predetermined position of an ATM cell to be inputted; each selective information storing means 11 stores selective information extracted by each extracting means 10; and also an ATM cell is temporarily stored in a cell buffer 12 which is provided in accordance with the directional path of each input. A decision means determines one directional path that allows an ATM cell to pass through from plural directional paths by comparing selective information of each means 11, a cell buffer 12 of the determined directional path is read, and selector 14 is switched and a cell is outputted.

4. 发明专利

JPH09107362A ALARM CELL INSERT METHOD AND ALARM CELL GENERATOR 失效
公开(公告)号：JPH09107362A
公开(公告)日：1997-04-22
申请号：JP26395795
申请日：1995-10-12
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： ONO HIDEAKI , TAKECHI RYUICHI , EZAKI YUTAKA , TAKAGI KOJI , ITODA JUN
IPC分类号： H04L29/14 , H04L12/24 , H04L12/26 , H04L12/28 , H04L12/70 , H04L12/815 , H04L12/855 , H04L12/863 , H04Q3/00
摘要： PROBLEM TO BE SOLVED: To suppress probability of occurrence of a cell abort on a transmission path by counting a cell slot on the transmission path and detecting an idle cell slot to which an alarm cell is inserted so as to insert the alarm cell to the idle cell slot. SOLUTION: The alarm cell generator 100 is provided with a detection section 101 detecting a fault occurred at an upper stream side of a transmission path 200 and a cell generating section 102 to generate a cell to each connection multiplexed on the transmission path 200 in which the fault is detected, and with a cell buffer 103 storing once the generated cell, and with a cell insert section 104 that calculates a cell slot on the transmission path 260 in which the fault is detected, detects an idle cell slot to which a cell is inserted, extracts a cell from the buffer 103 so that the cell insert interval on the transmission line 200 is a prescribed value or over based on the count of the cell slots and inserts the cell to the detected idle cell slot.

5. 发明专利

JPH10336182A ATM INTRA-NETWORK TIME SYNCHRONIZATION SYSTEM 失效
公开(公告)号：JPH10336182A
公开(公告)日：1998-12-18
申请号：JP13804197
申请日：1997-05-28
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： TAKECHI RYUICHI , KATO TSUGIO , ONO HIDEAKI , NAKANO MASATOMO , MORIKAWA HIROMOTO
IPC分类号： H04L7/00 , H04L12/28 , H04L12/70 , H04Q3/00
摘要： PROBLEM TO BE SOLVED: To realize an ATM intra-network time synchronization system which performs time synchronization between ATM nodes with a simple configuration in an ATM network including plural ATM nodes. SOLUTION: In an ATM network that includes plural ATM nodes, a master station 1a is provided with a cell generating means 1a1 which generates a time transfer cell and a cell inserting means 1a2 which inserts a time transfer cell into a transmission line at a prescribed time when time correction should be executed; and a slave station 2a is provided with a cell extracting means 2a1 which extracts a time transfer cell from a multiplexed cell that is fetched from the transmission line and a setting means 2a2 that sets receiving time of an extracted time transfer cell as reference time of the slave station.

6. 发明专利

DE69839754D1 未知
公开(公告)号：DE69839754D1
公开(公告)日：2008-09-04
申请号：DE69839754
申请日：1998-03-24
申请人： FUJITSU LTD
发明人： ONO HIDEAKI , TAKECHI RYUICHI , KATO TSUGUO , SASAKI HIROSHI , SASAKI TAKAYUKI
IPC分类号： H04Q3/00 , H04Q11/04 , H04J3/16 , H04L47/22 , H04L47/43 , H04L47/6275
摘要： A short cell multiplexer includes a sequence designating unit, in which reading intervals corresponding to QOS classes are set in respective reading interval setting registers. A counter memory is stored with the number of timings at which the short cells can be read. The sequence designating unit specifies the QOS class in which the number of timings reaches the reading interval on the basis of the reading interval and the number of timings, and gives to a reading unit an indication of reading the short cell belonging to this class.

7. 发明专利

DE69835488T2 未知
公开(公告)号：DE69835488T2
公开(公告)日：2007-07-19
申请号：DE69835488
申请日：1998-03-24
申请人： FUJITSU LTD
发明人： ONO HIDEAKI , TAKECHI RYUICHI , KATO TSUGUO , SASAKI HIROSHI , SASAKI TAKAYUKI
IPC分类号： H04Q3/00 , H04Q11/04 , H04L47/43 , H04L47/52 , H04L47/6275
摘要： The quality classes of arriving short cells and the ATM virtual connections to be multiplexed are identified based on the CIDs of those short cells. Those short cells are written into FIFO memories corresponding to the ATM virtual connections and quality classes. A VC specification control section specifies one ATM virtual connection for each ATM cell sending timing. At this time, a sequence specification control section specifies one or more quality classes in sequence. A readout control section reads one or more short cells out from the FIFO memory in accordance with the specified ATM virtual connection and quality class, stores them in one ATM cell and sends the ATM cell to the ATM virtual connection specified by the VC specification control section.

8. 发明专利

DE69833712T2 未知
公开(公告)号：DE69833712T2
公开(公告)日：2007-01-11
申请号：DE69833712
申请日：1998-09-11
申请人： FUJITSU LTD
发明人： ONO HIDEAKI , TAKECHI RYUICHI , FUJISAWA TORU
IPC分类号： H04Q3/00 , H04Q11/04 , H04L47/43
摘要： A first header converting section outputs, when partial fill cells are inputted to the first header converting section , the partial fill cells, while converting a VPI of each of the partial fill cells into a value that is a unit of a multiplexing process at a short cell multiplexing section and converting a VCI of each of the partial fill cells into a value to be a CID which is to be stored in a short cell at the short cell multiplexing section. The short cell multiplexing section receives a plurality of the partial fill cells from the first header converting section to multiplex a plurality of the short cells within the partial fill cells for every VPI of the partial fill cells, and produces an AAL Type 2 cell in which the VCIs of the partial fill cells are stored as CIDs and the VPIs of the partial fill cells are stored as VCIs. A second header converting section receives the AAL Type 2 cell from the short cell multiplexing section and outputs the AAL Type 2 cell while converting the VPI/VCI of the AAL Type 2 cell into given values.

9. 发明专利

DE69837750D1 未知
公开(公告)号：DE69837750D1
公开(公告)日：2007-06-21
申请号：DE69837750
申请日：1998-09-24
申请人： FUJITSU LTD
发明人： ONO HIDEAKI , TAKECHI RYUICHI , FUJISAWA TORU
IPC分类号： H04Q3/00 , H04L47/43 , H04Q11/04
摘要： An ATM switching apparatus applicable to a short cell comprises an ATM-SW outputting a cell from an output path corresponding to a identifier of the cell, an interface unit, a demultiplexer, and a multiplexer connected to the ATM-SW. The interface unit sets, when a cell storing a plurality of short cells are inputted, the identifier of the cell so that the cell is transmitted from ATM-SW to the demultiplexer, and outputts the cell toward the ATM-SW. The demultiplexer receives the cell outputted from the interface unit through the ATM-SW, produces a plurality of partial fill cells, and outputs the partial fill cells, while setting an identifier of each partial fill cell so that the partial fill is outputted to the multiplexer. The multiplexier receives a plurality of the partial fill cells outputted from the demultiplexer through the ATM-SW, produces a cell storing a plurality of the short cells in accordance with the identifiers of the partial fill cells, and outputs the cell to the ATM-SW.

10. 发明专利

DE69835488D1 未知
公开(公告)号：DE69835488D1
公开(公告)日：2006-09-21
申请号：DE69835488
申请日：1998-03-24
申请人： FUJITSU LTD
发明人： ONO HIDEAKI , TAKECHI RYUICHI , KATO TSUGUO , SASAKI HIROSHI , SASAKI TAKAYUKI
IPC分类号： H04Q3/00 , H04Q11/04 , H04L47/43 , H04L47/52 , H04L47/6275
摘要： The quality classes of arriving short cells and the ATM virtual connections to be multiplexed are identified based on the CIDs of those short cells. Those short cells are written into FIFO memories corresponding to the ATM virtual connections and quality classes. A VC specification control section specifies one ATM virtual connection for each ATM cell sending timing. At this time, a sequence specification control section specifies one or more quality classes in sequence. A readout control section reads one or more short cells out from the FIFO memory in accordance with the specified ATM virtual connection and quality class, stores them in one ATM cell and sends the ATM cell to the ATM virtual connection specified by the VC specification control section.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式