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1. 发明专利

JPS54133849A DATA TRANSFER CONTROL SYSTEM 失效
公开(公告)号：JPS54133849A
公开(公告)日：1979-10-17
申请号：JP4158278
申请日：1978-04-08
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： YASUI YUTAKA , HANIBUCHI KENICHI
IPC分类号： G06F13/42 , G06F3/00
摘要： PURPOSE:To make it possible to transfer efficiently data between a data channel unit and an input-output unit through small hardware. CONSTITUTION:Once a service-in signal is inputted, FF17 is set and internal processing circuit 24 starts operating. When FF17 is set newly to complete the operation, internal processing circuit 24 outputs a pulse of logic [1], so that FF18 will be set. The set output of FF18 is sent out as a service-out signal via cable driver 2-1. With the service-in signal reset, AND gate 7 outputs logic [1], which is transmitted to AND circuit 11 via OR circuit 15. Then, AND gate 11 generates a pulse output, by which FFs 17, 18 and 19 are all reset. In case of a data-in signal, nearly the same operation is carried out.

2. 发明专利

JPS5450248A CONTROL SYSTEM FOR DATA CHANNEL UNIT 失效
公开(公告)号：JPS5450248A
公开(公告)日：1979-04-20
申请号：JP11554877
申请日：1977-09-28
申请人： OKI ELECTRIC IND CO LTD , NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , HITACHI LTD , FUJITSU LTD
发明人： KAJIZUKA SHIYOUJI , MURATA TATSUTOSHI , HANIBUCHI KENICHI , OOKAWA KAZUMASA , SHIYOUDA AKIO , AWAJI TOSHIO
IPC分类号： G06F13/12 , G06F3/00 , G06F13/00
摘要： PURPOSE:To make data transfer high-speed by reading out the first one word of transfer data from a memory to a buffer at an operation start time and correcting the number of transfer words and the address in the main memory of transfer data in the unit which controls data transfer between the main memory and I/O devices. CONSTITUTION:In the control system where data channel unit 4 for controlling data transfer between main memory 3 and plural I/O devices 5 and memory control circuit 2 are provided, the first word of data is loaded to buffer register 6 in data channel unit 4 at an operation start time, and transfer word register 10 and data address register 11 are beforehand corrected. Then, fractional data or look-ahead data is stored in data buffer 15 at a transfer interrupt time, and the complication of update of transfer byte storing register 18 and data address register 11 at a transfer time is canceled. Then, the transfer control is made simple, and the decision processing is reduced to make transfer high-speed.

3. 发明专利

JPS54130847A PRECEDENCE CHANGE SYSTEM 失效
公开(公告)号：JPS54130847A
公开(公告)日：1979-10-11
申请号：JP3857578
申请日：1978-04-01
申请人： NIPPON TELEGRAPH & TELEPHONE , FUJITSU LTD
发明人： HANIBUCHI KENICHI , YASUI YUTAKA
IPC分类号： G06F9/26 , G06F9/22 , G06F9/48
摘要： PURPOSE:To facilitate precedence and multiplexing change by providing a next instruction execution control field in a micro instruction and registering a priority state and an execution state there and weighting according to processing unit dependent upon a program itself. CONSTITUTION:In the multiplex unit which multi-controls plural controlled units S0 to S2 in time division in the micro program control system, the multiplex unit is provided with control memory peripheral part 3 to store a program, micro instruction execution control part 1 to hold the execution request of instructions for every unit of S0 to S2, and micro instruction execution part 9. Further, priority indication part 2 having preference circuit 20 to prefer the signal from control part 1 is provided, and the precedence of micro instruction execution objects is changed according to the indication of a micro instruction or the indication from units S0 to S2 by execution part 1 having a function to read out successively instructions for the execution request of units S0 to S2, which are selected by circuit 20, into micro instruction register 70.

4. 发明专利

JPS54133854A PREEFETCH BUFFER CONTROL SYSTEM FOR CHANNEL COMMAND WORD 失效
公开(公告)号：JPS54133854A
公开(公告)日：1979-10-17
申请号：JP4158578
申请日：1978-04-08
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： YASUI YUTAKA , HANIBUCHI KENICHI
IPC分类号： G06F13/12 , G06F3/00 , G06F9/06 , G06F9/38
摘要： PURPOSE:To improve the performance of a data unit system by making a buffer display unit display which buffer is stored with a channel command word in process of execution and by reading out channel command word from both buffers. CONSTITUTION:By an input-output instruction from a CPU, the data channel equipment reads out a string of channel command words in sequence and controls the data transfer between input and output devices. Here, either one of buffers 1 and 2 is stored with a pre-fetched channel command word and the other is with a channel command word in process of execution; and buffer display unit 5 displays which buffer, 1 or 2, is stored with the channel command word in process of execution, and reads out the channel command words from buffers 1 and 2. Consequently, the capacities of buffers stored with channel command words are reduced and the processing performance of the data processing system can be improved.

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