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1. 发明申请

WO2013030624A1 INTEGRATED CIRCUIT PACKAGE 审中-公开
标题翻译：集成电路封装
公开(公告)号：WO2013030624A1
公开(公告)日：2013-03-07
申请号：PCT/IB2011/053811
申请日：2011-08-31
申请人： FREESCALE SEMICONDUCTOR, INC. , REUTER, Ralf , TROTTA, Saverio
发明人： REUTER, Ralf , TROTTA, Saverio
IPC分类号： H01L23/48 , H01L21/60 , H01L23/12
CPC分类号： H01L23/66 , H01L23/49822 , H01L24/13 , H01L24/16 , H01L2223/6627 , H01L2223/6677 , H01L2224/131 , H01L2224/16225 , H01L2924/19032 , H01L2924/19051 , H01P3/003 , H01P5/10 , H01L2924/014
摘要： An integrated circuit package (10 comprising a substrate (6) and at least one semiconductor die (26) is described. A connection unit (8) may provide electrical connections between the substrate (6) and the semiconductor die (26). The connection unit (8) may comprise a stack of conduction layers and isolation layers stacked atop each other. The stack may include a microstrip line or a coplanar waveguide. The microstrip line or the coplanar waveguide may be part of a balun, a power divider, or a directional coupler.
摘要翻译：描述了集成电路封装（10，包括衬底和至少一个半导体管芯），连接单元（8）可以在衬底（6）和半导体管芯（26）之间提供电连接，连接单元（8）可以包括彼此顶层堆叠的导电层和隔离层，堆叠可以包括微带线或共面波导，微带线或共面波导可以是平衡 - 不平衡变换器，功率分配器或定向耦合器。

2. 发明申请

WO2011007199A1 INTEGRATED CIRCUIT, TRANSCEIVER AND METHOD FOR LEAKAGE CANCELLATION IN A RECEIVE PATH 审中-公开
标题翻译：集成电路，收发器和接收路径中泄漏消除的方法
公开(公告)号：WO2011007199A1
公开(公告)日：2011-01-20
申请号：PCT/IB2009/053082
申请日：2009-07-16
申请人： FREESCALE SEMICONDUCTOR, INC. , TROTTA, Saverio , DEHLINK, Bernhard , REUTER, Ralf
发明人： TROTTA, Saverio , DEHLINK, Bernhard , REUTER, Ralf
IPC分类号： H04B15/00 , H04B1/40
CPC分类号： H04B1/525 , G01S7/023
摘要： An integrated circuit for cancelling a radio frequency transmit leakage signal comprises: a transmitter portion comprising at least one amplifier stage for transmitting a radio frequency signal to an antenna port; and a first coupler arranged to operably couple the transmitter portion, the antenna port and a receiver portion. The receiver portion is arranged to receive a first composite signal that comprises a received radio frequency signal from the antenna port and the transmit leakage signal. The receiver portion comprises: a first down-conversion circuit arranged to receive the first composite signal and a local oscillator signal such that the first down-conversion circuit outputs a down-converted composite signal at a first intermediate frequency signal; and a second coupler arranged to receive the down-converted first composite signal at the first intermediate frequency signal and a phase shifted version of the local oscillator signal such that the phase shifted version of the local oscillator signal is arranged to cancel at least a portion of the transmit leakage signal from the down-converted first composite signal.
摘要翻译：一种用于消除射频发射泄漏信号的集成电路包括：发射机部分，包括至少一个用于向天线端口发送射频信号的放大器级; 以及第一耦合器，被布置成可操作地耦合所述发射器部分，所述天线端口和接收器部分。接收器部分被布置为接收包括来自天线端口的接收的射频信号和发射泄漏信号的第一复合信号。接收器部分包括：第一下变频电路，布置成接收第一复合信号和本地振荡器信号，使得第一下变频电路以第一中频信号输出经下变频的复合信号; 以及第二耦合器，被布置为接收第一中频信号的下变频的第一复合信号和本地振荡器信号的相移版本，使得本地振荡器信号的相移版本被布置为消除至少一部分来自下变频的第一复合信号的发送泄漏信号。

3. 发明申请

WO2010010425A1 HETERODYNE RECEIVER 审中-公开
标题翻译：异位接收器
公开(公告)号：WO2010010425A1
公开(公告)日：2010-01-28
申请号：PCT/IB2008/053000
申请日：2008-07-25
申请人： FREESCALE SEMICONDUCTOR, INC. , TROTTA, Saverio , REUTER, Ralf
发明人： TROTTA, Saverio , REUTER, Ralf
IPC分类号： H03D7/16
CPC分类号： H03D7/163
摘要： A down-conversion module (300, 400) for a heterodyne receiver comprises a first mixer circuit (Mixer 1 ), a second mixer circuit (Mixer 2) and an interconnection (302). The first mixer circuit includes first and second differential control terminals (304, 306) and is arranged to produce a first down-converted differential voltage signal (IF 1 ) at a first down-converted frequency ( fI F 1 ) as a function of a first RF differential input signal applied to the first differential control terminals (304) and of a first RF differential reference frequency signal (LO) applied to the second differential control terminals (306). The second mixer circuit includes two differential pairs (318, 320) of second amplifier elements and the second amplifier elements comprise second differential control terminals and cross-connected pairs of second amplifier output paths for producing a second down-converted differential voltage signal (IF 2 ) at a second down-converted frequency as a function of the first down-converted differential voltage signal (IF 1 ) and of a second RF differential reference frequency signal applied to the second differential control terminals. The interconnection (302) includes transmission line elements (Z L1 , Z L2 ) and is arranged to apply a differential current signal which is a function of the first down-converted differential voltage signal (IF 1 ) to differential input terminals of the second mixer circuit common to respective pairs (318, 320) of the second amplifier elements.
摘要翻译：用于外差接收机的下变频模块（300,400）包括第一混频器电路（混频器1），第二混频器电路（混频器2）和互连（302）。第一混频器电路包括第一和第二差分控制端子（304,306），并且被布置成作为第一RF差分的函数以第一下变频频率（fIF1）产生第一下变频差分电压信号（IF1）施加到第一差分控制端子（304）的输入信号和施加到第二差分控制端子（306）的第一RF差分参考频率信号（LO）。第二混频器电路包括第二放大器元件的两个差分对（318,320），并且第二放大器元件包括用于产生第二下变频差分电压信号（IF2）的第二差分控制端子和交叉连接的第二放大器输出路径对，以第二下变频频率作为第一下变频差分电压信号（IF1）的函数和施加到第二差分控制端的第二RF差分参考频率信号的函数。互连（302）包括传输线路元件（ZL1，ZL2），并且被布置成将作为第一下变频差分电压信号（IF1）的函数的差分电流信号施加到第二混频器电路的公共的差分输入端子第二放大器元件的相应对（318,320）。

4. 发明申请

WO2012014013A3 Latch circuit, flip-flop circuit and frequency divider 审中-公开
公开(公告)号：WO2012014013A3
公开(公告)日：2012-02-02
申请号：PCT/IB2010/053408
申请日：2010-07-27
申请人： FREESCALE SEMICONDUCTOR, INC. , TROTTA, Saverio
发明人： TROTTA, Saverio
IPC分类号： H03K3/00 , H03K21/00
摘要： The invention pertains to a latch circuit (10) comprising a sensing arrangement (12) with one or more sensing transistors (T 1, T 2 ) adapted to sense an input signal (D, D n ) and to provide a first signal based on the sensed input signal (D, D n ), and a sensing arrangement switch device (16) connected or connectable to a first current source (18), the sensing arrangement switch device (16) being adapted to switch on or off a current to the one or more sensing transistors (T 1, T 2 ) based on a first clock signal (CLK). The latch circuit (10) further comprises a storage arrangement (14) with one or more storage transistors (T 3, T 4 ) adapted to store the first signal and to provide a second signal based on the first signal, and a storage arrangement switching device (20) connected or connectable to the first current source (18) or a second current source, the storage arrangement switching device (20) being adapted to switch on or off a current to the storage transistors (T 3, T 4 ) based on a second clock signal (CLK n ), as well as a tuning arrangement (24) connected or connectable to a temperature sensor (106, 108), the tuning arrangement (24) being adapted to bias a current of the sensing arrangement (12) and/or the storage arrangement (14) based on a temperature signal provided by the temperature sensor (106, 108). The invention also pertains to a flip-flop circuit with two or more latch circuits and a frequency divider (100) comprising at least one latch circuit (10) as described.

5. 发明申请

WO2010076670A1 OSCILLATOR CIRCUIT 审中-公开
标题翻译：振荡器电路
公开(公告)号：WO2010076670A1
公开(公告)日：2010-07-08
申请号：PCT/IB2009/050014
申请日：2009-01-05
申请人： FREESCALE SEMICONDUCTOR, INC. , TROTTA, Saverio
发明人： TROTTA, Saverio
IPC分类号： H03B5/12 , H03B5/18
CPC分类号： H03B5/1847 , H03B2200/007 , H03B2200/0098
摘要： An oscillator circuit (10) comprises a push-push oscillator (12) and a differential output (14, 15), comprising a first (16) and a second (18) output circuit. The push-push oscillator (12) has a first (20) and a second (22) branch. Each of the first (20) and second (22) branch comprises an own voltage divider branch (24, 26) of a common bridge circuit (28). Each of the first (24) and second (26) voltage divider branches comprises an own pair of micro-strip lines (30, 32; 34, 36) connected in series. Each of the first (24) and second (26) voltage divider branches has an own tap (C, D). Both taps (C, D) are connected to each other by at least one of a first capacity (42) and a micro-strip line. The differential output comprises a first (14) and a second (15) output terminal. The first output terminal (14) is connected via the first output circuit (16) to a first node (A). The second output terminal (15) is connected via the second output circuit (18) to a second node (B). Each of the first (A) and second (B) nodes of the push-push oscillator (12) is a common node (A, B) of both of the first (20) and the second branches (22).
摘要翻译：振荡器电路（10）包括推挽振荡器（12）和差分输出（14,15），包括第一输入（16）和第二输出电路（18）。推压振荡器（12）具有第一（20）和第二（22）分支。第一（20）和第二（22）分支中的每一个分支包括共用电桥电路（28）的自己的分压器分支（24,26）。第一（24）和第二（26）分压器分支中的每一个分别包括串联连接的自己的一对微带线（30,32; 34,36）。第一（24）和第二（26）分压器分支中的每一个具有自己的抽头（C，D）。两个抽头（C，D）通过第一容量（42）和微带线中的至少一个相互连接。差分输出包括第一输入端（14）和第二输出端子（15）。第一输出端子（14）经由第一输出电路（16）连接到第一节点（A）。第二输出端子（15）经由第二输出电路（18）连接到第二节点（B）。推挽振荡器（12）的第一（A）和第二（B）节点中的每一个是第一（20）和第二分支（22）两者的公共节点（A，B）。

6. 发明申请

WO2012143761A1 ANTENNA DEVICE, AMPLIFIER AND RECEIVER CIRCUIT, AND RADAR CIRCUIT 审中-公开
标题翻译：天线设备，放大器和接收器电路以及雷达电路
公开(公告)号：WO2012143761A1
公开(公告)日：2012-10-26
申请号：PCT/IB2011/051737
申请日：2011-04-20
申请人： FREESCALE SEMICONDUCTOR, INC. , TROTTA, Saverio
发明人： TROTTA, Saverio
IPC分类号： G01S7/03
CPC分类号： H01Q3/34 , G01S7/032 , G01S13/426 , G01S13/931 , G01S2013/9375 , H01Q1/3233 , H01Q3/00 , H01Q21/065
摘要： An antenna device (1i) comprises a first chain (301 ) of at least two antenna components (31i), wherein each of the antenna components (31i) comprises a transmit antenna (2i) having a line of antenna patches (92) for emitting radar waves (22i); and a receive antenna (4i) having a line of antenna patches (92) for receiving radar response waves (320); wherein the line of antenna patches (92) of the receive antenna (4i) is aligned with the line of antenna patches (92) of the transmit antenna (2i). An amplifier and receiver circuit (3i) for amplifying radar signals (20) and for receiving radar response signals (320), the amplifier and receiver circuit (3i) comprises a phase shifter (323) for shifting a phase of the radar signals (20) to be amplified and for synchronously shifting the received radar response signals (320). A radar circuit (310) comprises a first chain (301 ) of at least two radar components (39i), wherein each of the radar components (39i) comprises: an amplifier and receiver circuit (3i) as described above; and a transmit antenna (2i) for emitting radar waves (20); and a receive antenna (4i) for receiving radar response waves (320).
摘要翻译：天线装置（1i）包括至少两个天线部件（31i）的第一链（301），其中每个天线部件（31i）包括具有用于发射的天线贴片线（92）的发射天线（2i）雷达波（22i）; 以及具有用于接收雷达响应波（320）的天线贴片线（92）的接收天线（4i）; 其中所述接收天线（4i）的所述天线贴片（92）的线与所述发射天线（2i）的天线贴片（92）的线对齐。一种用于放大雷达信号（20）并用于接收雷达响应信号（320）的放大器和接收器电路（3i），所述放大器和接收器电路（3i）包括移相器（323），用于将雷达信号（20 ）被放大并且用于同步地移位所接收的雷达响应信号（320）。雷达电路（310）包括至少两个雷达部件（39i）的第一链（301），其中每个雷达部件（39i）包括：如上所述的放大器和接收器电路（3i）; 和用于发射雷达波的发射天线（2i）; 以及用于接收雷达响应波（320）的接收天线（4i）。

7. 发明申请

WO2014006447A1 PHASE SWITCHABLE BISTABLE MEMORY DEVICE, A FREQUENCY DIVIDER AND A RADIO FREQUENCY TRANSCEIVER 审中-公开
标题翻译：相位可切换的双向存储器件，频率分配器和无线电频率收发器
公开(公告)号：WO2014006447A1
公开(公告)日：2014-01-09
申请号：PCT/IB2012/053371
申请日：2012-07-03
申请人： FREESCALE SEMICONDUCTOR, INC. , GHAZINOUR, Akbar , TROTTA, Saverio
发明人： GHAZINOUR, Akbar , TROTTA, Saverio
IPC分类号： H03K23/00 , H03K3/356 , H04B1/40
CPC分类号： H03K3/2885 , H03K23/425
摘要： A phase switchable bistable memory device comprising a bistable memory component and a phase switching component is described. The bistable memory component comprises a bistable memory stage arranged to receive an input signal and a state transition stage arranged to receive a state transition signal and to cause the bistable memory stage to capture a logical state of the received input signal upon a transition from a first logical state of the state transition signal to a second logical state of the state transition signal. The phase switching component is arranged to receive a clock input signal and a phase control signal, and to output the state transition signal comprising transitions between logical states corresponding to transitions between logical states of the clock input signal and comprising a phase relative to the clock input signal based at least partly on the received phase control signal.
摘要翻译：描述了包括双稳态存储器部件和相位切换部件的相位可切换双稳态存储器件。双稳态存储器组件包括双稳态存储器级，被布置为接收输入信号和状态转移级，布置成接收状态转换信号，并且使得双稳态存储器级在从第一存储器转换到第一存储器级时，捕获所接收的输入信号的逻辑状态状态转换信号的逻辑状态变为状态转换信号的第二逻辑状态。相位切换部件被布置为接收时钟输入信号和相位控制信号，并且输出状态转换信号，该状态转换信号包括对应于时钟输入信号的逻辑状态之间的转换的逻辑状态之间的转变，并且包括相对于时钟输入的相位信号至少部分地基于所接收的相位控制信号。

8. 发明申请

WO2013060376A1 RECEIVER CIRCUIT, PHASED-ARRAY RECEIVER AND RADAR SYSTEM 审中-公开
标题翻译：接收器电路，相位阵列接收器和雷达系统
公开(公告)号：WO2013060376A1
公开(公告)日：2013-05-02
申请号：PCT/EP2011/068916
申请日：2011-10-27
申请人： FREESCALE SEMICONDUCTOR, INC. , TROTTA, Saverio
发明人： TROTTA, Saverio
IPC分类号： H03F3/45 , H03F1/56 , H03F3/60 , H03F1/02 , H03F3/195 , H03D7/14
CPC分类号： G01S7/282 , G01S7/285 , H01Q3/34 , H03D7/1433 , H03D7/1458 , H03D7/165 , H03F1/0205 , H03F1/56 , H03F3/189 , H03F3/195 , H03F3/45085 , H03F3/60 , H03F2200/06 , H03F2200/09 , H03F2200/216 , H03F2200/222 , H03F2200/255 , H03F2200/294 , H03F2200/336 , H03F2200/411 , H03F2200/423 , H03F2200/555 , H03F2203/45544 , H03F2203/45554 , H03F2203/45594 , H03F2203/45596 , H03F2203/45622 , H03F2203/45631 , H04B1/16
摘要： A receiver circuit (30), comprises an input balun circuit (32) comprising a balanced balun output (34) and being capable of receiving RF signals, an input amplification circuit (36) comprising a balanced amplifier input (38) and a balanced amplifier output (40), a single balanced in-phase mixing circuit (42) comprising a first unbalanced RF mixer input (44) and a balanced in-phase mixing frequency input (46), and a single balanced quadrature mixing circuit (48) comprising a second unbalanced RF mixer input (50) and a balanced quadrature mixing frequency input (52). The balanced amplifier input is connected to the balanced balun output, a first terminal (54) of the balanced amplifier output is connected to provide an amplified RF signal to the first unbalanced RF mixer input and a second terminal (56) of the balanced amplifier output is connected to provide a phase-shifted amplified RF signal to the second unbalanced RF mixer input.
摘要翻译：一种接收器电路（30），包括：输入平衡 - 不平衡变换电路（32），包括平衡不平衡转换器输出（34）并且能够接收RF信号;输入放大电路（36），包括平衡放大器输入（38）和平衡放大器输出（40），包括第一不平衡RF混频器输入（44）和平衡同相混合频率输入（46）的单个平衡同相混合电路（42），以及单个平衡正交混合电路（48），包括第二不平衡RF混频器输入（50）和平衡正交混频输入（52）。平衡放大器输入连接到平衡 - 不平衡转换器输出，平衡放大器输出的第一端（54）被连接以提供放大的RF信号到第一不平衡RF混频器输入端和平衡放大器输出端的第二端（56）被连接以向第二不平衡RF混频器输入提供相移放大RF信号。

9. 发明申请

WO2012098438A1 TRANSMITTER AND METHOD OF OPERATING A TRANSMITTER 审中-公开
标题翻译：发射机和操作发射机的方法
公开(公告)号：WO2012098438A1
公开(公告)日：2012-07-26
申请号：PCT/IB2011/050280
申请日：2011-01-21
申请人： FREESCALE SEMICONDUCTOR, INC. , TROTTA, Saverio , LI, Hao
发明人： TROTTA, Saverio , LI, Hao
IPC分类号： H04B1/04
CPC分类号： H04B1/04 , H04B1/036
摘要： A transmitter (10) comprises an oscillator (12), a power amplifier (24), and a heating element (34). The power amplifier (24) generates a high power signal (26, 28) according to the low power signal (14, 16). The transmitter (10) may be operated such that a heat production rate of the group consisting of the power amplifier (24) and the heating element (34) is substantially constant. The heating element (34) may be a dummy power amplifier. A method of operating a transmitter (10) is also disclosed.
摘要翻译：发射机（10）包括振荡器（12），功率放大器（24）和加热元件（34）。功率放大器（24）根据低功率信号（14,16）产生高功率信号（26,28）。发射器（10）可以被操作，使得由功率放大器（24）和加热元件（34）组成的组的发热量基本上是恒定的。加热元件（34）可以是虚拟功率放大器。还公开了一种操作发射机（10）的方法。

10. 发明申请

WO2012025791A1 Push-push oscillator circuit 审中-公开
标题翻译：推挽式振荡电路
公开(公告)号：WO2012025791A1
公开(公告)日：2012-03-01
申请号：PCT/IB2010/053850
申请日：2010-08-26
申请人： FREESCALE SEMICONDUCTOR, INC. , YIN, Yi , LI, Hao , TROTTA, Saverio
发明人： YIN, Yi , LI, Hao , TROTTA, Saverio
IPC分类号： H03B5/18 , H01P7/08 , H03F3/45
CPC分类号： H02M7/53835 , H03B5/1209 , H03B5/1218 , H03B5/1231 , H03B5/124 , H03B5/1847 , H03B25/00 , H03B2200/007
摘要： The invention pertains to a push-push oscillator circuit (10) with a first oscillation branch with a first active device (12) and a first tank (16, 20) adapted to provide a signal having a fundamental frequency f 0 , a second oscillation branch with a second active device (14) and a second tank (18, 22) symmetrical to the first oscillation branch and adapted to provide a signal having the fundamental frequency f 0 . Output branches (24, 28, 50, 60) are coupled to the first oscillation branch and the second oscillation branch to provide signals having the second harmonic frequency 2f0 of the fundamental signal based on the signals having the fundamental frequency f 0 and/or to provide signals having the fundamental frequency f 0 . The push-push oscillator circuit (10) further comprises at least one terminal branch (36, 58, 68, 78) with a terminal (42, 82, 94, 100) adapted to provide a component of a differential signal having the second harmonic frequency 2f0 or the fundamental frequency f 0 . The at least one terminal branch (36, 58, 68, 78) comprises a RF stub (44, 84) comprising a quarter-wavelength transmission line (46, 86, 102, 106) and a corresponding capacitor (48, 88, 104, 108) for a signal having the second harmonic frequency 2f 0 or the fundamental frequency f 0 . The invention also pertains to a push-push oscillator circuit (10) having output branches (24, 28, 50, 60) coupled to the first oscillation branch and the second oscillation branch to provide signals having the fundamental frequency f 0 . One of the output branches (50) comprises two coupling inductors (52, 54) and a first fundamental frequency branch (58) having a first fundamental frequency terminal (94), the first fundamental frequency branch (58) being coupled in series with one of the coupling inductors (54), the two coupling inductors being coupled to each other in series via a first connection point. Another one of the output branches (60) comprises two coupling inductors (62, 64) and a second fundamental frequency branch (68) with a second fundamental frequency terminal (100), the second fundamental frequency branch (68) being coupled in series to one of the coupling inductors (54) of this output branch (6), and the two coupling inductors (62, 64) of this output branch (60) being coupled to each other in series via a second connection point. The push-push-oscillator circuit (10) is adapted to provide a differential signal having the fundamental frequency f 0 at the first and second fundamental frequency terminals.
摘要翻译：本发明涉及具有第一振荡分支的推挽式振荡电路（10），第一振荡分支具有第一有源器件（12）和适于提供具有基频f0的信号的第一容器（16,20），第二振荡分支具有与第一振荡分支对称的第二有源装置（14）和第二罐（18,22），并且适于提供具有基频f0的信号。输出分支（24,28,50,60）耦合到第一振荡分支和第二振荡分支，以基于具有基频f0的信号提供具有基波信号的二次谐波频率2f0的信号和/或提供具有基频f0的信号。推挽振荡器电路（10）还包括至少一个端子分支（36,58,68,78），其具有适于提供具有二次谐波的差分信号的分量的端子（42,82,94,100）频率2f0或基频f0。所述至少一个端子支路（36,58,68,78）包括RF短截线（44,84），其包括四分之一波长传输线（46,86,102,106）和相应的电容器（48,88,104），108），用于具有二次谐波频率2f0或基频f0的信号。本发明还涉及一种具有耦合到第一振荡分支和第二振荡分支的输出分支（24,28,50,60）的推压振荡器电路（10），以提供具有基频f0的信号。输出分支（50）中的一个包括两个耦合电感器（52,54）和具有第一基频端子（94）的第一基频分支（58），第一基频分支（58）与一个的耦合电感器（54），两个耦合电感器通过第一连接点彼此串联连接。输出分支（60）中的另一个包括具有第二基频终端（100）的两个耦合电感（62,64）和第二基频分支（68），第二基频分支（68）串联耦合该输出支路（6）的耦合电感器（54）和该输出支路（60）的两个耦合电感器（62,64）之一经由第二连接点彼此串联连接。推压振荡器电路（10）适于提供在第一和第二基频端子处具有基频f0的差分信号。

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