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1. 发明专利

GB2421377B Signal Processing System Having an ADC Delta-Sigma Modulator with Single-Ended Input and Feedback Signal Inputs 未知
公开(公告)号：GB2421377B
公开(公告)日：2006-12-06
申请号：GB0525487
申请日：2005-12-14
申请人： FEI XIAOFAN , GABORIAU JOHANN , MELANSON JOHN L , CIRRUS LOGIC INC
发明人： FEI XIAOFAN , GABORIAU JOHANN , MELANSON JOHN L
IPC分类号： H03M3/04 , H03M3/00

2. 发明专利

GB2421377A Delta-sigma modulator with single-ended input and feedback signal 未知
公开(公告)号：GB2421377A
公开(公告)日：2006-06-21
申请号：GB0525487
申请日：2005-12-14
申请人： FEI XIAOFAN , GABORIAU JOHANN , MELANSON JOHN L , CIRRUS LOGIC INC
发明人： FEI XIAOFAN , GABORIAU JOHANN , MELANSON JOHN L
IPC分类号： H03M3/02 , H03M3/00 , H03M3/04
摘要： Signal processing systems described herein include an analog-to-digital delta sigma modulator to process a single-ended input signal using a single-ended analog feedback reference signal. The delta sigma modulator includes a switched capacitor circuit that integrates a difference between the single-ended input signal and the single-ended analog feedback signal derived from a quantization output of the delta sigma modulator. Embodiments of the switched capacitor circuit allow the delta sigma modulator to be implemented with fewer switches, less complicated reference signal generators, and smaller capacitors relative to conventional counterparts. Thus, embodiments of the delta sigma modulator described herein can cost less to build and use less power. Embodiments of the signal processing systems can be implemented in single and multi-bit delta sigma modulators and various sampling topologies, including single and double sampling topologies.

3. 发明申请

WO2012083222A2 SWITCHING PARAMETER BASED DISCONTINUOUS MODE-CRITICAL CONDUCTION MODE TRANSITION 审中-公开
标题翻译：基于开关参数的不连续模式临界导通模式转换
公开(公告)号：WO2012083222A2
公开(公告)日：2012-06-21
申请号：PCT/US2011065593
申请日：2011-12-16
申请人： CIRRUS LOGIC INC , MELANSON JOHN L , HE ZHAOHUI
发明人： MELANSON JOHN L , HE ZHAOHUI
IPC分类号： H02M1/00
CPC分类号： H02M3/33507 , H02M3/33523 , H02M2001/0003 , H02M2001/007 , H05B33/0815 , Y02B20/346
摘要： An electronic system includes a controller to provide at least dual-mode conduction control of a switching power converter. In at least one embodiment, the controller is capable to control transitions between discontinuous conduction mode (DCM) and critical conduction mode (CRM) of the switching power converter using a measured switching time parameter having a value corresponding with an approximately peak voltage of a time-varying supply voltage supplied to the switching power converter. In at least one embodiment, the controller dynamically compensates for changing parameters of the electronic system by dynamically determining a minimum non-conductive time of the control switch of the switching power converter using the measured switching time parameter value at approximately the peak of the supply voltage of the supply voltage.
摘要翻译：电子系统包括控制器，以提供开关功率转换器的至少双模式导通控制。在至少一个实施例中，控制器能够使用具有与时间的近似峰值电压相对应的值的测量开关时间参数来控制开关功率转换器的不连续导通模式（DCM）和临界导通模式（CRM）之间的转变提供给开关电源转换器的不同电源电压。在至少一个实施例中，控制器通过动态确定开关功率变换器的控制开关的最小非导通时间，使用测量的开关时间参数值在动态电压的峰值附近动态补偿电子系统的变化参数的电源电压。

4. 发明申请

WO2010126765A3 CALIBRATION OF LAMPS USING POWER LINE COMMUNICATION FOR SENDING CALIBRATION DATA 审中-公开
标题翻译：使用电源线通信对发送校准数据进行校准
公开(公告)号：WO2010126765A3
公开(公告)日：2011-04-14
申请号：PCT/US2010031978
申请日：2010-04-22
申请人： CIRRUS LOGIC INC , DRAPER WILLIAM A , GRISAMORE ROBERT T , MELANSON JOHN L
发明人： DRAPER WILLIAM A , GRISAMORE ROBERT T , MELANSON JOHN L
IPC分类号： H05B37/02
CPC分类号： H05B37/0263 , H05B37/0218 , Y02B20/46
摘要： In at least one embodiment, a lamp (204) includes a controller (214) configured to generate power control signals for a lamp (204) is also configured to receive lamp calibration data received via one or more power terminals (206, 208) of the lamp (204). The controller (214) is configured to process the calibration data to calibrate the lamp (204). In at least one embodiment, the lamp (204) includes one or more light emitting diodes.
摘要翻译：在至少一个实施例中，灯（204）包括被配置为产生用于灯（204）的功率控制信号的控制器（214），其还被配置为接收经由一个或多个电源端子（206,208）接收的灯校准数据灯（204）。控制器（214）被配置为处理校准数据以校准灯（204）。在至少一个实施例中，灯（204）包括一个或多个发光二极管。

5. 发明申请

WO2004066540A3 SIGNAL PROCESSING SYSTEM WITH BASEBAND NOISE MODULATION AND NOISE FOLD BACK REDUCTION 审中-公开
标题翻译：信号处理系统，具有基带噪声调制和噪声缩减功能
公开(公告)号：WO2004066540A3
公开(公告)日：2004-11-11
申请号：PCT/US2004001514
申请日：2004-01-21
申请人： CIRRUS LOGIC INC , PLISCH MARJORIE R , MELANSON JOHN L , HODAPP STEPHEN T , RANGAN GIRI N K
发明人： PLISCH MARJORIE R , MELANSON JOHN L , HODAPP STEPHEN T , RANGAN GIRI N K
IPC分类号： H03F1/02 , H03F1/26 , H03F3/21 , H03F3/217 , H03F3/38 , H03M3/04 , H04B14/06
CPC分类号： H03M3/34 , H03F1/02 , H03F1/26 , H03F3/211 , H03F3/217 , H03F3/2175 , H03F3/38 , H03F2200/331 , H03M3/50
摘要： A digital-to-analog converter ("DAC") system utilized chopping modulation technology to remove 1/f and other baseband noise from a baseband of a signal of interest. Chopping modulation and demodulation circuitry of the DAC operate at a chopping frequency equal to approximately one-half of a digital input signal sampling frequency. Chopping at one-half the sampling frequency allows fold back into the baseband of the input signal's frequency components and reduces fold back of noise, such as quantization noise, residing outside the baseband. In a further embodiment, a notch filter attenuates signals having frequencies around the chopping frequency prior to chopping to reduce fold back of noise into the baseband due to parasitic modulation. Coordination of chopping timing also reduces noises in the output of the DAC system.
摘要翻译：数模转换器（“DAC”）系统利用斩波调制技术从感兴趣信号的基带去除1 / f和其它基带噪声。 DAC的斩波调制和解调电路以等于数字输入信号采样频率的大约一半的斩波频率工作。以采样频率的一半斩波允许折回到输入信号的频率分量的基带，并减少驻留在基带外的诸如量化噪声的噪声的折返。在另一实施例中，陷波滤波器在斩波之前衰减具有围绕斩波频率的频率的信号，以减少由于寄生调制而导致的基带的噪声折回。斩波定时的协调还可以降低DAC系统输出的噪声。

6. 发明申请

WO2013090777A3 ISOLATION OF SECONDARY TRANSFORMER WINDING CURRENT DURING AUXILIARY POWER SUPPLY GENERATION 审中-公开
标题翻译：在辅助电源发电期间分离二次变压器绕组电流
公开(公告)号：WO2013090777A3
公开(公告)日：2014-08-07
申请号：PCT/US2012069843
申请日：2012-12-14
申请人： CIRRUS LOGIC INC , MELANSON JOHN L , DRAKSHAPALLI PRASHANTH , MARU SIDDHARTH
发明人： MELANSON JOHN L , MARU SIDDHARTH
IPC分类号： H02M3/335 , H02M1/00
CPC分类号： H02M3/33507 , H02M1/4258 , H02M1/44 , H02M3/33523 , H02M3/33561 , H02M3/33576 , H02M5/2576 , H02M7/217 , H02M2001/0006 , H02M2001/0048 , H05B33/0815 , H05B33/0845 , H05B37/02 , Y02B20/346 , Y02B20/347 , Y02B70/126 , Y02B70/1491
摘要： An electronic system and method include a controller (206) to actively control power transfer from a primary winding (110) of a switching power converter to an auxiliary-winding (212) of an auxiliary power supply 214). The switching power converter is controlled and configured such that during transfer of power to the auxiliary-winding (212), the switching power converter does not transfer charge to one or more secondary-windings (116) of the switching power converter. Thus, the switching power converter isolates one or more secondary transformer winding currents (is) from an auxiliary-winding current. By isolating the charge delivered to the one or more secondary-windings (116) from charge delivered to the auxiliary-winding (212), the controller can accurately determine an amount of charge delivered to the secondary-windings (116) and, thus, to a load (108).
摘要翻译：电子系统和方法包括控制器（206），用于主动地控制从开关功率转换器的初级绕组（110）到辅助电源214的辅助绕组（212）的功率传输。开关电源转换器被控制和配置为使得在向辅助绕组（212）传递电力期间，开关功率转换器不将电荷传送到开关功率转换器的一个或多个次级绕组（116）。因此，开关功率转换器将一个或多个次级变压器绕组电流与辅助绕组电流隔离。通过将递送到一个或多个次级绕组（116）的电荷从输送到辅助绕组（212）的电荷中分离出来，控制器可以精确地确定输送到次级绕组（116）的电荷量，到负载（108）。

7. 发明申请

WO2012061774A3 CONTROLLED ENERGY DISSIPATION IN A SWITCHING POWER CONVERTER 审中-公开
标题翻译：开关电源转换器中的控制能量消耗
公开(公告)号：WO2012061774A3
公开(公告)日：2012-11-08
申请号：PCT/US2011059447
申请日：2011-11-04
申请人： CIRRUS LOGIC INC , MELANSON JOHN L , KING ERIC J
发明人： MELANSON JOHN L , KING ERIC J
IPC分类号： H02M3/00 , H05B33/08 , H05B37/02
CPC分类号： H05K1/0203 , H05B33/08 , H05B33/0809 , H05B33/0812 , H05B33/0815 , H05B33/0818 , H05B33/0824 , H05B33/0827 , H05B33/0845 , H05B33/0851 , H05B33/0854 , H05B37/02 , Y02B20/19 , Y02B20/346 , Y02B20/347
摘要： In at least one embodiment, a lighting system includes one, some, or all of a switch path, link path, and flyback path power dissipation circuits to actively and selectively control power dissipation of excess energy in a switching power converter of the lighting system. The flyback path power dissipation circuit dissipates power through a flyback path of the switching power converter. In at least one embodiment, the lighting system controls power dissipation through the flyback path by controlling a transformer primary current in the flyback path and, for example, limiting the primary current with a current source and dissipating power in the flyback switch and the current source.
摘要翻译：在至少一个实施例中，照明系统包括开关路径，链路路径和反激路径功率耗散电路中的一个，一个或全部，以有源和选择性地控制照明系统的开关功率转换器中的多余能量的功率耗散。反激路径功耗电路通过开关电源转换器的反激路径耗散功率。在至少一个实施例中，照明系统通过控制回扫路径中的变压器初级电流来控制通过回扫路径的功率耗散，并且例如，利用电流源限制初级电流并且在回扫开关和电流源中消耗功率。

8. 发明申请

WO2012061784A3 SWITCHING POWER CONVERTER INPUT VOLTAGE APPROXIMATE ZERO CROSSING DETERMINATION 审中-公开
标题翻译：切换电源转换器输入电压近似零交叉测量
公开(公告)号：WO2012061784A3
公开(公告)日：2012-07-05
申请号：PCT/US2011059462
申请日：2011-11-04
申请人： CIRRUS LOGIC INC , KING ERIC J , MELANSON JOHN L
发明人： KING ERIC J , MELANSON JOHN L
IPC分类号： H02M1/08
CPC分类号： H03K17/13 , H05B33/0815 , H05B33/0845 , Y02B20/346
摘要： In at least one embodiment, the controller senses a leading edge, phase cut AC input voltage value to a switching power converter during a cycle of the AC input voltage. The controller senses the voltage value at a time prior to a zero crossing of the AC input voltage and utilizes the voltage value to determine the approximate zero crossing. In at least one embodiment, by determining an approximate zero crossing of the AC input voltage, the controller is unaffected by any disturbances of the dimmer that could otherwise make detecting the zero crossing problematic. The particular way of determining an approximate zero crossing is a matter of design choice. In at least one embodiment, the controller approximates the AC input voltage using a function that estimates a waveform of the AC input voltage and determines the approximate zero crossing of the AC input voltage from the approximation of the AC input voltage.
摘要翻译：在至少一个实施例中，控制器在交流输入电压的周期期间感测到开关功率转换器的前沿，相切割AC输入电压值。控制器感测交流输入电压过零之前的电压值，并利用电压值来确定近似过零点。在至少一个实施例中，通过确定AC输入电压的近似零交叉，控制器不受调光器的任何干扰影响，否则可能会使检测到零交叉问题。确定近似过零点的具体方法是设计选择的问题。在至少一个实施例中，控制器使用估计AC输入电压的波形的函数来近似AC输入电压，并根据AC输入电压的近似确定AC输入电压的近似过零点。

9. 发明申请

WO2012016221A3 COORDINATED DIMMER COMPATIBILITY FUNCTIONS 审中-公开
标题翻译：协调调光器兼容性功能
公开(公告)号：WO2012016221A3
公开(公告)日：2012-03-29
申请号：PCT/US2011046027
申请日：2011-07-29
申请人： CIRRUS LOGIC INC , MELANSON JOHN L , KING ERIC J
发明人： MELANSON JOHN L , KING ERIC J
IPC分类号： H02M1/36 , H02M1/00 , H05B33/08
CPC分类号： H02M3/33507 , H02M1/36 , H02M7/06 , H02M2001/0006 , H05B33/0815 , Y02B20/346 , Y10T307/352 , Y10T307/50
摘要： A system and method includes a controller that is configured to coordinate (i) a low impedance path for a dimmer current, (ii), control of switch mode power conversion and (iii) an inactive state to, for example, to allow a dimmer to function normally from cycle to cycle of an alternating current (AC) supply voltage. In at least one embodiment, the dimmer functions normally when the dimmer conducts at a correct phase angle indicated by a dimmer input setting and avoids prematurely resetting while conducting. In at least one embodiment, by coordinating functions (i), (ii), and (iii), the controller controls a power converter system that is compatible with a triac-based dimmer. In at least one embodiment, the controller coordinates functions (i), (ii), and (iii) in response to a particular dimming level indicated by a phase cut, rectified input voltage supplied to the power converter system.
摘要翻译：一种系统和方法包括控制器，其被配置为协调（i）用于调光器电流的低阻抗路径，（ii）开关模式功率转换的控制和（iii）非活动状态，以例如允许调光器在交流（AC）电源电压的周期到周期之间正常工作。在至少一个实施例中，当调光器以由调光器输入设置指示的正确相位角传导时，调光器正常工作，并避免在导通时过早复位。在至少一个实施例中，通过协调功能（i），（ii）和（iii），控制器控制与基于三端双向可控硅的调光器兼容的功率转换器系统。在至少一个实施例中，控制器响应由提供给功率转换器系统的相位切断的整流输入电压指示的特定调光电平来对功能（i），（ii）和（iii）进行协调。

10. 发明申请

WO2007112190A3 DELTA SIGMA MODULATOR ANALOG-TO-DIGITAL CONVERTERS WITH QUANTIZER OUTPUT PREDICTION AND COMPARATOR REDUCTION 审中-公开
标题翻译：具有量子输出预测和减少比较器的DELTA SIGMA调制器模拟到数字转换器
公开(公告)号：WO2007112190A3
公开(公告)日：2007-12-06
申请号：PCT/US2007063667
申请日：2007-03-09
申请人： CIRRUS LOGIC INC , MELANSON JOHN L
发明人： MELANSON JOHN L
IPC分类号： H03M3/04
CPC分类号： H03M3/39 , H03M3/424
摘要： The quantizers of delta sigma modulators in the signal processing systems described herein use a reduced set of comparators for quantization by predetermining and maintaining a maximum per cycle deviation d between a loop filter output signal V LF (t) and a predicted quantizer output signal q est . In at least one embodiment, a maximum quantizer level deviation d is defined in terms of a number of quantization levels. Thus, the number of comparators in a quantizer needed to quantize the quantizer input signal V in (t) is based on the maximum quantizer level deviation d. In addition to using fewer comparators than available quantization output levels N, the quantizers can use an even number of comparators M, in contrast to comparable conventional reduced comparator ADC tracking quantizer designs using M+1 number of comparators, where N and Mare integers and M
摘要翻译：本文描述的信号处理系统中的Δ-Σ调制器的量化器通过预先确定和维持环路滤波器输出信号V LF（t）和预测量化器输出信号Q 。在至少一个实施例中，根据量化级数来定义最大量化器电平偏差d。因此，量化器中量化器（t）中的量化器输入信号V SUB所需的比较器的数量是基于最大量化器电平偏差d。除了使用比可用的量化输出电平N更少的比较器之外，量化器可以使用偶数个比较器M，与使用M + 1个比较器的可比较的传统缩减比较器ADC跟踪量化器设计相反，其中N和Mare整数和M

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