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1. 发明授权

US5999479A Row decoder for nonvolatile memory having a low-voltage power supply 失效
标题翻译：具有低压电源的非易失性存储器的行解码器
公开(公告)号：US5999479A
公开(公告)日：1999-12-07
申请号：US10202
申请日：1998-01-21
申请人： Eungjoon Park , Hsi-Hsien Hung
发明人： Eungjoon Park , Hsi-Hsien Hung
IPC分类号： G11C8/10 , G11C16/08 , G11C8/00
CPC分类号： G11C8/10 , G11C16/08
摘要： A row decoder for a nonvolatile memory having a low-voltage power supply that minimizes the load capacitance presented to a high voltage source without requiring additional circuitry. The row decoder accomplishes this by providing a local decoder having only one input requiring a boosted voltage higher than the power supply voltage. Further, predecoders are used to reduce the number of local decoders that receive the boosted voltage.
摘要翻译：一种用于具有低电压电源的非易失性存储器的行解码器，其将呈现给高电压源的负载电容最小化，而不需要额外的电路。行解码器通过提供仅需要一个高于电源电压的升高电压的输入的本地解码器来实现这一点。此外，预解码器用于减少接收升压电压的本地解码器的数量。

2. 发明授权

US5886566A High voltage charge transfer stage 失效
标题翻译：高电压电荷转移级
公开(公告)号：US5886566A
公开(公告)日：1999-03-23
申请号：US917008
申请日：1997-08-21
申请人： Eungjoon Park , Hsi-Hsien Hung
发明人： Eungjoon Park , Hsi-Hsien Hung
IPC分类号： G05F3/24 , G11C5/14 , H02M3/07 , G05F3/02
CPC分类号： G11C5/145 , H02M3/073 , G05F3/247
摘要： An improved charge transfer stage with an expanded output voltage range and high charge transfer efficiency is described. The charge transfer stage can be implemented as an output stage in a four phase clock negative charge pump system. The charge transfer stage comprises a PMOS pass transistor coupling the transfer stage input and output, a resistor between the transfer stage input and the pass transistor gate, a clock terminal, a capacitor configured PMOS transistor coupling the clock terminal to the gate of the pass transistor, and a diode from the transfer stage output to ground. When the transfer stage input goes low, charge is coupled through the resistor to pre-charge the gate of the pass transistor. The resistor has a higher junction breakdown voltage than a transistor which allows the gate of the pass transistor to be driven to a larger voltage. To provide sufficient charge to turn on the pass transistor, a logic high level greater than the power supply, such as 2 VCC, can be used for the clock signal coupled through the capacitor configured transistor to the gate of the pass transistor. To prevent the 2 VCC logic high level from forward biasing the p-n junction formed by the source and drain of the PMOS capacitor configured transistor with the well, the source, drain and well are coupled together. The charge transfer stage also includes a p-n junction diode coupled from the output of the stage to ground.
摘要翻译：描述了具有扩展的输出电压范围和高电荷转移效率的改进的电荷转移级。电荷转移阶段可以实现为四相时钟负电荷泵系统中的输出级。电荷传输级包括耦合传输级输入和输出的PMOS传输晶体管，传输级输入和传输晶体管栅极之间的电阻器，时钟端子，将时钟端子耦合到传输晶体管的栅极的电容器配置的PMOS晶体管，以及从转移级输出到地的二极管。当传输级输入变为低电平时，电荷通过电阻耦合来对传输晶体管的栅极进行预充电。电阻器具有比允许传输晶体管的栅极被驱动到更大电压的晶体管更高的结击穿电压。为了提供足够的电荷来接通传输晶体管，可以将大于电源的逻辑高电平（例如2 VCC）用于通过电容器配置的晶体管耦合到传输晶体管的栅极的时钟信号。为了防止2 VCC逻辑高电平正向偏置由PMOS电容器配置晶体管的源极和漏极与阱形成的p-n结，源极，漏极和阱耦合在一起。电荷转移级还包括从级的输出端耦合到地的p-n结二极管。

3. 发明授权

US5729551A Space efficient column decoder for flash memory redundant columns 失效
标题翻译：空间高效的列解码器，用于闪存冗余列
公开(公告)号：US5729551A
公开(公告)日：1998-03-17
申请号：US768914
申请日：1996-12-17
申请人： Eung Joon Park , Hsi-Hsien Hung
发明人： Eung Joon Park , Hsi-Hsien Hung
IPC分类号： G11C29/00
CPC分类号： G11C29/789 , G11C29/80
摘要： The present invention is a space efficient redundant column decoder circuit for use in a non-volatile memory device. The redundant column decoder compares a n-bit stored defective address with a n-bit presented address. Based on this comparison, an output signal is generated. This output signal is used both to specify the redundant column (or set of columns) associated with the redundant column decoder circuit, and to de-activate all of the other column decoders in the device. The redundant column decoder has a pull-up path and a parallel combination of n pairs of complementary pull-down paths. The pull-up path is connected to the pull-down paths at an output node, and the output signal is taken at this output node. Each pair of complementary pull-down paths has a first pull-down path and a second pull-down path. The first pull down path has a first non-volatile memory cell in series with and connected to a first address transistor. The first address transistor is also connected to the output node. The second pull-down path has a second non-volatile memory cell in series with and connected to a second address transistor. The second address transistor is also connected to the output node. At least one of the pull-down paths is conductive when the stored defective address does not match the presented address. Conversely, all of the pull-down paths are non-conductive when the stored defective address matches the presented address.
摘要翻译：本发明是一种用于非易失性存储器件的空间高效冗余列解码器电路。冗余列解码器将n位存储的缺陷地址与n位呈现的地址进行比较。基于该比较，生成输出信号。该输出信号用于指定与冗余列解码器电路相关联的冗余列（或列），并且去激活器件中的所有其他列解码器。冗余列解码器具有上拉路径和n对互补下拉路径的并行组合。上拉路径在输出节点处连接到下拉路径，并在该输出节点处获取输出信号。每对互补下拉路径具有第一下拉路径和第二下拉路径。第一下拉通路具有与第一地址晶体管串联连接的第一非易失性存储单元。第一个地址晶体管也连接到输出节点。第二下拉路径具有与第二地址晶体管串联并连接到其的第二非易失性存储单元。第二地址晶体管也连接到输出节点。当存储的缺陷地址与所呈现的地址不匹配时，至少一个下拉路径是导通的。相反，当存储的缺陷地址与所呈现的地址匹配时，所有下拉路径都是不导通的。

4. 发明授权

US06404268B1 Circuit for simulating zero cut-in voltage diode and rectifier having zero cut-in voltage characteristic 失效
标题翻译：用于模拟零截止电压二极管和具有零切断电压特性的整流器的电路
公开(公告)号：US06404268B1
公开(公告)日：2002-06-11
申请号：US09739704
申请日：2000-12-20
申请人： Hsi-Hsien Hung , Hsin Chou Lee
发明人： Hsi-Hsien Hung , Hsin Chou Lee
IPC分类号： H02M700
CPC分类号： H02M7/217 , H02M7/219 , H02M2007/2195 , Y02B70/1408
摘要： There is disclosed a circuit for simulating zero cut-in voltage diode and a rectifier having zero cut-in voltage characteristic. The MOS transistors manufactured by the CMOS process are used as circuit components and are properly biased so as to provide the rectifying capability, and thus are used as a rectifying diode. Furthermore, with a proper bias, the rectifying diode has zero cut-in voltage and a low current loss, and thus a high efficient rectifier can be implement.
摘要翻译：公开了一种用于模拟零截止电压二极管和具有零切断电压特性的整流器的电路。由CMOS工艺制造的MOS晶体管用作电路元件，并被适当地偏置以提供整流能力，因此被用作整流二极管。此外，通过适当的偏置，整流二极管具有零截止电压和低电流损耗，因此可以实现高效整流器。

5. 发明授权

US5982223A Charge pump system with improved programming current distribution 失效
标题翻译：电荷泵系统具有改进的编程电流分布
公开(公告)号：US5982223A
公开(公告)日：1999-11-09
申请号：US879340
申请日：1997-06-20
申请人： Eung Joon Park , Hsi-Hsien Hung
发明人： Eung Joon Park , Hsi-Hsien Hung
IPC分类号： G11C5/14 , H02M3/07 , H03L1/00
CPC分类号： G11C5/145 , H02M3/073
摘要： A voltage pump circuit includes a native MOS device coupled as a charge transfer device (M1) between input and output stage nodes. A parallel-coupled MOS pair (M2, M3) is coupled between drain (input node) and source (output node) of the charge transfer device, in which M3 is configured as a diode. A clock generator outputs at least three non-overlapping phase signals: .phi.1 (which goes high at t1 and low at t6), .phi.2 (which goes high at t3 and low at t4), .phi.3 (which goes low qt t2 and high at t5). The t1 .phi.1 positive transient is AC-coupled to M1's drain, and a smaller fraction of the transient is coupled to M1's gate, precharging M1, which begins to turn-on. The .phi.3 t2 negative transient is AC-coupled to M1's source, increasing M1 gate-source potential, which more fully turns-on M1. The .phi.2 t3 positive transient is coupled to M1's gate, turning-on M1 very hard. A phase clock generator outputting square-wave, same-frequency signals having respective 90.degree. phase shifts that are frequency independent can be used to drive pump circuits and sequentially operated groups of pump circuits.
摘要翻译：电压泵电路包括作为输入和输出级节点之间的电荷转移装置（M1）耦合的原生MOS器件。并联耦合MOS对（M2，M3）耦合在电荷转移装置的漏极（输入节点）和源极（输出节点）之间，其中M3被配置为二极管。时钟发生器输出至少三个非重叠相位信号：phi 1（在t1处为高，在t6为低电平），phi 2（在t3为高，在t4为高电平），phi 3（其变为低qt t2和高在t5）。 t1 phi 1正瞬变与M1的漏极交流耦合，较小部分的瞬态耦合到M1的门，预充电M1开始导通。 phi 3 t2负瞬变与M1的源极交流耦合，增加M1栅极源极电位，更加完全导通M1。 phi 2 t3正瞬变与M1的门相连，非常困难。输出具有频率无关的相应90°相移的方波同频信号的相位时钟发生器可用于驱动泵电路和顺序操作的泵电路组。

6. 发明授权

US5973961A Divided bit line system for non-volatile memory devices 失效
标题翻译：用于非易失性存储器件的分立位线系统
公开(公告)号：US5973961A
公开(公告)日：1999-10-26
申请号：US7398
申请日：1998-01-15
申请人： Fungioon Park , Hsi-Hsien Hung , Ker-Ching Liu
发明人： Fungioon Park , Hsi-Hsien Hung , Ker-Ching Liu
IPC分类号： G11C7/18 , G11C16/04 , G11C16/10 , G11G11/34
CPC分类号： G11C7/18 , G11C16/0416 , G11C16/10
摘要： A sub-bit line architecture for non-volatile memory devices. Four sub-bit lines are coupled to each main bit line. The sub-bit lines are approximately one half the length of the main bit lines in each sector. This sub-bit line length provides low parasitic capacitance and high signal integrity. Each sub-bit line is coupled to a main bit line through a select transistor. A column latch is coupled to each main bit line to provide program data. Data is programmed to the memory array in a page program mode. In page program mode, the selected sub-bit line applies a programming voltage to the memory cell transistor drain terminals. The drain voltage is applied to all of the memory cell transistor drains coupled to the selected sub-bit line. Since the sub-bit lines are only half the length of the main bit lines in each sector, the number of memory cell transistors coupled to each sub-bit line is about half the number coupled to sub-bit lines that are the length of the main bit line. As a result, the number of times memory cell transistors are disturbed due to increases in drain voltage caused by the sub-bit line being selected is reduced. A further advantage of the present invention is that program disturb is reduced.
摘要翻译：非易失性存储器件的子位线架构。四个子位线耦合到每个主位线。子位线大约是每个扇区中主位线长度的一半。该子位线长度提供低寄生电容和高信号完整性。每个子位线通过选择晶体管耦合到主位线。列锁存器耦合到每个主位线以提供程序数据。数据以页面程序模式编程到存储器阵列。在页面编程模式下，所选择的子位线将编程电压施加到存储单元晶体管漏极端子。漏极电压被施加到耦合到所选择的子位线的所有存储单元晶体管漏极。由于子位线仅是每个扇区中的主位线的长度的一半，所以耦合到每个子位线的存储单元晶体管的数量是耦合到子位线的数量的一半，主位线结果，由于由选择的子位线引起的漏极电压的增加而使存储单元晶体管受到干扰的次数减少。本发明的另一个优点是减少了程序干扰。

7. 发明授权

US5886923A Local row decoder for sector-erase fowler-nordheim tunneling based flash memory 失效
标题翻译：用于扇区擦除fowler-nordheim隧道基闪存的本地行解码器
公开(公告)号：US5886923A
公开(公告)日：1999-03-23
申请号：US958289
申请日：1997-10-27
申请人： Hsi-Hsien Hung
发明人： Hsi-Hsien Hung
IPC分类号： G11C16/08 , G11C16/04
CPC分类号： G11C16/08
摘要： A semiconductor non-volatile memory device is disclosed which is based on the use of Fowler Nordheim electron tunneling to charge and discharge the isolated gates of the storage cells. The disclosed memory device includes global decoder circuitry capable of passing either positive or negative voltages to a set of global word lines controlling, local decoder circuitry. The local decoder includes a set of word line drivers, each of which sets the voltage level of a corresponding local word line in response to the voltage levels of its associated global word line and a collection of control signals. Each word line driver includes one p-channel transistor and two n-channel transistors. These three transistors collectively establish selected local word lines at appropriate voltages for erase, program and read operations. The three transistors also establish unselected local word lines at solid bias voltages that prevent disturbance of memory cells that are not the target of a memory operation.
摘要翻译：公开了一种半导体非易失性存储器件，其基于使用Fowler Nordheim电子隧道来对存储单元的隔离栅极进行充电和放电。所公开的存储器件包括能够将正电压或负电压传送到控制本地解码器电路的一组全局字线的全局解码器电路。本地解码器包括一组字线驱动器，每个字线驱动器响应于其相关联的全局字线的电压电平和控制信号的集合而设置对应的本地字线的电压电平。每个字线驱动器包括一个p沟道晶体管和两个n沟道晶体管。这三个晶体管以合适的电压共同建立选定的本地字线，用于擦除，编程和读取操作。三个晶体管还建立固定偏置电压的未选择的本地字线，以防止不是存储器操作目标的存储器单元的干扰。

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