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1. 发明授权

US5973961A Divided bit line system for non-volatile memory devices 失效
标题翻译：用于非易失性存储器件的分立位线系统
公开(公告)号：US5973961A
公开(公告)日：1999-10-26
申请号：US7398
申请日：1998-01-15
申请人： Fungioon Park , Hsi-Hsien Hung , Ker-Ching Liu
发明人： Fungioon Park , Hsi-Hsien Hung , Ker-Ching Liu
IPC分类号： G11C7/18 , G11C16/04 , G11C16/10 , G11G11/34
CPC分类号： G11C7/18 , G11C16/0416 , G11C16/10
摘要： A sub-bit line architecture for non-volatile memory devices. Four sub-bit lines are coupled to each main bit line. The sub-bit lines are approximately one half the length of the main bit lines in each sector. This sub-bit line length provides low parasitic capacitance and high signal integrity. Each sub-bit line is coupled to a main bit line through a select transistor. A column latch is coupled to each main bit line to provide program data. Data is programmed to the memory array in a page program mode. In page program mode, the selected sub-bit line applies a programming voltage to the memory cell transistor drain terminals. The drain voltage is applied to all of the memory cell transistor drains coupled to the selected sub-bit line. Since the sub-bit lines are only half the length of the main bit lines in each sector, the number of memory cell transistors coupled to each sub-bit line is about half the number coupled to sub-bit lines that are the length of the main bit line. As a result, the number of times memory cell transistors are disturbed due to increases in drain voltage caused by the sub-bit line being selected is reduced. A further advantage of the present invention is that program disturb is reduced.
摘要翻译：非易失性存储器件的子位线架构。四个子位线耦合到每个主位线。子位线大约是每个扇区中主位线长度的一半。该子位线长度提供低寄生电容和高信号完整性。每个子位线通过选择晶体管耦合到主位线。列锁存器耦合到每个主位线以提供程序数据。数据以页面程序模式编程到存储器阵列。在页面编程模式下，所选择的子位线将编程电压施加到存储单元晶体管漏极端子。漏极电压被施加到耦合到所选择的子位线的所有存储单元晶体管漏极。由于子位线仅是每个扇区中的主位线的长度的一半，所以耦合到每个子位线的存储单元晶体管的数量是耦合到子位线的数量的一半，主位线结果，由于由选择的子位线引起的漏极电压的增加而使存储单元晶体管受到干扰的次数减少。本发明的另一个优点是减少了程序干扰。

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