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    • 3. 发明申请
    • SECONDARY BATTERY
    • 二次电池
    • US20130164585A1
    • 2013-06-27
    • US13540893
    • 2012-07-03
    • Eun-Ok KwakJeong-Deok ByunJong-Wook YoonByoung-Ju KimKyung-Won Seo
    • Eun-Ok KwakJeong-Deok ByunJong-Wook YoonByoung-Ju KimKyung-Won Seo
    • H01M2/10
    • H01M2/20H01M2/1077H01M2/202H01M2/266H01M2/30
    • A secondary battery including: a battery unit including a battery cell and a lead tab that protrudes from the battery cell; a frame case for supporting the battery unit and including a first support portion for supporting the battery cell and a second support portion for supporting the lead tab; and a connection member for perforating a connection hole formed in the lead tab and extending in a direction of the second support unit, wherein the connection hole of the lead tab includes: a first connection hole that is spaced apart from a first edge of the lead tab by a first width; and a second connection hole that is spaced apart from a second edge of the lead tab by a second width. The secondary battery may reduce electrical resistance of a charge/discharge path and has improved efficiency.
    • 一种二次电池,包括:电池单元,其包括从所述电池单元突出的电池单元和引线片; 用于支撑电池单元并包括用于支撑电池单元的第一支撑部分和用于支撑引线片的第二支撑部分的框架壳体; 以及连接构件,用于对形成在所述引线片中并沿所述第二支撑单元的方向延伸的连接孔进行穿孔,其中所述引线片的所述连接孔包括:与所述引线的第一边缘间隔开的第一连接孔 标签以第一宽度; 以及第二连接孔,其与所述引线片的第二边缘间隔开第二宽度。 二次电池可以降低充电/放电路径的电阻并且提高效率。
    • 4. 发明授权
    • Secondary battery
    • 二次电池
    • US09520584B2
    • 2016-12-13
    • US13540893
    • 2012-07-03
    • Eun-Ok KwakJeong-Deok ByunJong-Wook YoonByoung-Ju KimKyung-Won Seo
    • Eun-Ok KwakJeong-Deok ByunJong-Wook YoonByoung-Ju KimKyung-Won Seo
    • H01M2/20H01M2/26H01M2/30H01M2/10
    • H01M2/20H01M2/1077H01M2/202H01M2/266H01M2/30
    • A secondary battery including: a battery unit including a battery cell and a lead tab that protrudes from the battery cell; a frame case for supporting the battery unit and including a first support portion for supporting the battery cell and a second support portion for supporting the lead tab; and a connection member for perforating a connection hole formed in the lead tab and extending in a direction of the second support unit, wherein the connection hole of the lead tab includes: a first connection hole that is spaced apart from a first edge of the lead tab by a first width; and a second connection hole that is spaced apart from a second edge of the lead tab by a second width. The secondary battery may reduce electrical resistance of a charge/discharge path and has improved efficiency.
    • 一种二次电池,包括:电池单元,其包括从所述电池单元突出的电池单元和引线片; 用于支撑电池单元并包括用于支撑电池单元的第一支撑部分和用于支撑引线片的第二支撑部分的框架壳体; 以及连接构件,用于对形成在所述引线片中并沿所述第二支撑单元的方向延伸的连接孔进行穿孔,其中所述引线片的所述连接孔包括:与所述引线的第一边缘间隔开的第一连接孔 标签以第一宽度; 以及第二连接孔,其与所述引线片的第二边缘间隔开第二宽度。 二次电池可以降低充电/放电路径的电阻并且提高效率。
    • 7. 发明授权
    • Semiconductor memory device
    • 半导体存储器件
    • US06785171B2
    • 2004-08-31
    • US10237665
    • 2002-09-10
    • Hi-Choon LeeByoung-Ju Kim
    • Hi-Choon LeeByoung-Ju Kim
    • G11C700
    • G11C29/808G11C29/785
    • A semiconductor memory device includes a plurality of sub-wordlines, a plurality of sub-wordlines corresponding a redundancy main wordline, a plurality of redundancy memory cells each being coupled to each of the redundancy sub-wordlines, and a redundancy control circuit for disabling the main wordline selector when among the sub-wordlines, a sub-wordline to which a defective memory cell is coupled is addressed, and for controlling the sub-wordline to be replaced by the redundancy main wordline. The number of the redundancy sub-wordlines coupled to the redundancy main wordline is smaller than the number of the sub-wordlines coupled to the main wordline. Therefore, when among the sub-wordlines coupled to the main wordline, a sub-wordline to which a normal main memory cell is coupled is addressed, the main wordline selector is enabled to improve a redundancy flexibility and reduce a circuit area.
    • 半导体存储器件包括多个子字线,对应于冗余主字线的多个子字线,每个冗余存储器单元分别耦合到每个冗余子字线,以及冗余控制电路,用于禁用 主字线选择器在子字线之间寻址与缺陷存储器单元耦合的子字线,并且用于控制副字线被冗余主字线替代。 耦合到冗余主字线的冗余子字线的数量小于耦合到主字线的子字线的数量。 因此,当耦合到主字线的子字线中,寻址与正常主存储器单元耦合的子字线时,主字选择器能够提高冗余灵活性并减少电路面积。
    • 8. 发明授权
    • Circuits and methods for generating internal signals for integrated
circuits by dynamic inversion and resetting
    • 通过动态反转和复位产生集成电路的内部信号的电路和方法
    • US6122220A
    • 2000-09-19
    • US396870
    • 1999-09-15
    • Byoung-Ju KimHi-Choon Lee
    • Byoung-Ju KimHi-Choon Lee
    • G11C11/407G11C7/22G11C11/413G11C7/00G11C8/00
    • G11C7/22
    • Internal signals for integrated circuits are generated by a reset circuit that is responsive to an input signal to generate a reset signal pulse a predetermined time after the input signal is activated, and a dynamic inversion circuit that inverts the input signal in the absence of the reset signal pulse and that assumes an inactive state in response to the reset signal pulse, to thereby produce an output pulse that is activated by the input signal and that is deactivated by the reset circuit as a function of the predetermined time. Methods of operating integrated circuits generate a reset signal pulse a predetermined time after an input signal is activated. The input signal is inverted until the reset pulse is generated, to thereby produce an output pulse that is activated by the input signal and that is deactivated by the reset circuit as a function of the predetermined time. Accordingly, circuits and methods for generating internal clock signals for integrated circuits by dynamic inversion and resetting can rapidly generate internal clock signals from external clock signals and can have reduced susceptibility to noise.
    • 用于集成电路的内部信号由复位电路产生,复位电路响应于输入信号在输入信号被激活之后的预定时间产生复位信号脉冲;以及动态反相电路,在没有复位的情况下使输入信号反相 信号脉冲,并且响应于复位信号脉冲而呈现无效状态,从而产生由输入信号激活并由复位电路停用的输出脉冲作为预定时间的函数。 操作集成电路的方法在输入信号被激活之后的预定时间产生复位信号脉冲。 输入信号被反相,直到产生复位脉冲,从而产生由输入信号激活并被复位电路取消的输出脉冲作为预定时间的函数。 因此,用于通过动态反转和复位产生用于集成电路的内部时钟信号的电路和方法可以快速地从外部时钟信号产生内部时钟信号,并且可以降低对噪声的敏感性。