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1. 发明申请

US20080160753A1 Method of forming metal wire in semiconductor device 有权
标题翻译：在半导体器件中形成金属线的方法
公开(公告)号：US20080160753A1
公开(公告)日：2008-07-03
申请号：US11801498
申请日：2007-05-10
申请人： Eun Soo Kim , Jung Geun Kim , Suk Joong Kim
发明人： Eun Soo Kim , Jung Geun Kim , Suk Joong Kim
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , H01L21/76844 , H01L21/76846 , H01L21/76882 , H01L23/53223 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a metal wire in a semiconductor device is disclosed The method includes the steps of etching an insulating layer formed on a semiconductor substrate to form a dual damascene pattern, forming a barrier metal layer in the dual damascene pattern, forming a metal layer on the barrier metal layer, and filling the dual damascene pattern with a conductive material to form a metal wire.
摘要翻译：公开了一种在半导体器件中形成金属线的方法。该方法包括以下步骤：蚀刻在半导体衬底上形成的绝缘层，以形成双镶嵌图案，在双镶嵌图案中形成阻挡金属层，形成金属层在阻挡金属层上，并用导电材料填充双镶嵌图案以形成金属线。

2. 发明申请

US20090004817A1 METHOD OF FORMING ISOLATION LAYER OF SEMICONDUCTOR DEVICE 失效
标题翻译：形成半导体器件隔离层的方法
公开(公告)号：US20090004817A1
公开(公告)日：2009-01-01
申请号：US11955881
申请日：2007-12-13
申请人： Jung Geun Kim , Eun Soo Kim , Seung Hee Hong , Suk Joong Kim
发明人： Jung Geun Kim , Eun Soo Kim , Seung Hee Hong , Suk Joong Kim
IPC分类号： H01L21/76
CPC分类号： H01L21/76232
摘要： A method of forming an isolation layer of a semiconductor device is disclosed herein, the method comprising the steps of providing a semiconductor substrate in which a tunnel insulating layer and a charge storage layer are formed on an active area and a trench is formed on an isolation area; forming a first insulating layer for filling a lower portion of the trench; forming a porous second insulating layer on the first insulating layer for filling a space between the charge storage layers; forming a third insulating layer on a side wall of the trench and the second insulating layer, the third insulating layer having a density higher than that of the second insulating layer; and forming a porous fourth insulating layer for filling the trench.
摘要翻译：本文公开了形成半导体器件的隔离层的方法，该方法包括以下步骤：提供在有源区上形成隧道绝缘层和电荷存储层的半导体衬底，并且在隔离层上形成沟槽区; 形成用于填充沟槽的下部的第一绝缘层; 在所述第一绝缘层上形成多孔第二绝缘层，用于填充所述电荷存储层之间的空间; 在所述沟槽和所述第二绝缘层的侧壁上形成第三绝缘层，所述第三绝缘层的密度高于所述第二绝缘层的密度; 以及形成用于填充所述沟槽的多孔第四绝缘层。

3. 发明申请

US20090023279A1 METHOD OF FABRICATING FLASH MEMORY DEVICE 失效
标题翻译：制造闪存存储器件的方法
公开(公告)号：US20090023279A1
公开(公告)日：2009-01-22
申请号：US12131626
申请日：2008-06-02
申请人： Eun Soo Kim , Jung Geun Kim , Suk Joong Kim
发明人： Eun Soo Kim , Jung Geun Kim , Suk Joong Kim
IPC分类号： H01L21/311 , H01L21/28
CPC分类号： H01L21/764 , H01L27/115 , H01L27/11521
摘要： The present invention relates to a method of fabricating a flash memory device and includes forming an air-gap having a low dielectric constant between word lines and floating gates. Further, a tungsten nitride (WN) layer is formed on sidewalls of a tungsten (W) layer for a control gate. Hence, the cross section of the control gate that is finally formed can be increased while preventing abnormal oxidization of the tungsten layer in a subsequent annealing process. The method of the present invention can improve interference between neighboring word lines and, thus improve the reliability of a device. Accordingly, a robust high-speed device can be implemented.
摘要翻译：本发明涉及一种制造闪速存储器件的方法，包括在字线和浮栅之间形成具有低介电常数的气隙。此外，在用于控制栅极的钨（W）层的侧壁上形成氮化钨（WN）层。因此，可以提高最终形成的控制栅极的横截面，同时防止随后的退火工艺中钨层的异常氧化。本发明的方法可以改善相邻字线之间的干扰，从而提高设备的可靠性。因此，可以实现鲁棒的高速设备。

4. 发明授权

US08163627B2 Method of forming isolation layer of semiconductor device 失效
标题翻译：形成半导体器件隔离层的方法
公开(公告)号：US08163627B2
公开(公告)日：2012-04-24
申请号：US11955881
申请日：2007-12-13
申请人： Jung Geun Kim , Eun Soo Kim , Seung Hee Hong , Suk Joong Kim
发明人： Jung Geun Kim , Eun Soo Kim , Seung Hee Hong , Suk Joong Kim
IPC分类号： H01L21/76
CPC分类号： H01L21/76232
摘要： A method of forming an isolation layer of a semiconductor device is disclosed herein, the method comprising the steps of providing a semiconductor substrate in which a tunnel insulating layer and a charge storage layer are formed on an active area and a trench is formed on an isolation area; forming a first insulating layer for filling a lower portion of the trench; forming a porous second insulating layer on the first insulating layer for filling a space between the charge storage layers; forming a third insulating layer on a side wall of the trench and the second insulating layer, the third insulating layer having a density higher than that of the second insulating layer; and forming a porous fourth insulating layer for filling the trench.
摘要翻译：本文公开了形成半导体器件的隔离层的方法，该方法包括以下步骤：提供在有源区上形成隧道绝缘层和电荷存储层的半导体衬底，并且在隔离层上形成沟槽区; 形成用于填充沟槽的下部的第一绝缘层; 在所述第一绝缘层上形成多孔第二绝缘层，用于填充所述电荷存储层之间的空间; 在所述沟槽和所述第二绝缘层的侧壁上形成第三绝缘层，所述第三绝缘层的密度高于所述第二绝缘层的密度; 以及形成用于填充所述沟槽的多孔第四绝缘层。

5. 发明授权

US07682967B2 Method of forming metal wire in semiconductor device 有权
标题翻译：在半导体器件中形成金属线的方法
公开(公告)号：US07682967B2
公开(公告)日：2010-03-23
申请号：US11801498
申请日：2007-05-10
申请人： Eun Soo Kim , Jung Geun Kim , Suk Joong Kim
发明人： Eun Soo Kim , Jung Geun Kim , Suk Joong Kim
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , H01L21/76844 , H01L21/76846 , H01L21/76882 , H01L23/53223 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a metal wire in a semiconductor device is disclosed The method includes the steps of etching an insulating layer formed on a semiconductor substrate to form a dual damascene pattern, forming a barrier metal layer in the dual damascene pattern, forming a metal layer on the barrier metal layer, and filling the dual damascene pattern with a conductive material to form a metal wire.
摘要翻译：公开了一种在半导体器件中形成金属线的方法。该方法包括以下步骤：蚀刻在半导体衬底上形成的绝缘层，以形成双镶嵌图案，在双镶嵌图案中形成阻挡金属层，形成金属层在阻挡金属层上，并用导电材料填充双镶嵌图案以形成金属线。

6. 发明授权

US07682904B2 Method of fabricating flash memory device 失效
标题翻译：制造闪存设备的方法
公开(公告)号：US07682904B2
公开(公告)日：2010-03-23
申请号：US12131626
申请日：2008-06-02
申请人： Eun Soo Kim , Jung Geun Kim , Suk Joong Kim
发明人： Eun Soo Kim , Jung Geun Kim , Suk Joong Kim
IPC分类号： H01L21/8234
CPC分类号： H01L21/764 , H01L27/115 , H01L27/11521
摘要： The present invention relates to a method of fabricating a flash memory device and includes forming an air-gap having a low dielectric constant between word lines and floating gates. Further, a tungsten nitride (WN) layer is formed on sidewalls of a tungsten (W) layer for a control gate. Hence, the cross section of the control gate that is finally formed can be increased while preventing abnormal oxidization of the tungsten layer in a subsequent annealing process. The method of the present invention can improve interference between neighboring word lines and, thus improve the reliability of a device. Accordingly, a robust high-speed device can be implemented.
摘要翻译：本发明涉及一种制造闪速存储器件的方法，包括在字线和浮栅之间形成具有低介电常数的气隙。此外，在用于控制栅极的钨（W）层的侧壁上形成氮化钨（WN）层。因此，可以提高最终形成的控制栅极的横截面，同时防止随后的退火工艺中钨层的异常氧化。本发明的方法可以改善相邻字线之间的干扰，从而提高设备的可靠性。因此，可以实现鲁棒的高速设备。

7. 发明申请

US20080102579A1 METHOD OF FORMING ISOLATION LAYER OF SEMICONDUCTOR DEVICE 失效
标题翻译：形成半导体器件隔离层的方法
公开(公告)号：US20080102579A1
公开(公告)日：2008-05-01
申请号：US11617690
申请日：2006-12-28
申请人： Cha Deok Dong , Whee Won Cho , Jung Geun Kim , Cheol Mo Jeong , Suk Joong Kim , Jung Gu Lee
发明人： Cha Deok Dong , Whee Won Cho , Jung Geun Kim , Cheol Mo Jeong , Suk Joong Kim , Jung Gu Lee
IPC分类号： H01L21/8242
CPC分类号： H01L27/11521 , H01L21/76232
摘要： A method of forming an isolation layer of a semiconductor device includes forming first trenches in an isolation region of a semiconductor substrate. A spacer is formed on sidewalls of each of the first trenches. Second trenches are formed in the isolation region below the corresponding first trenches. Each second trench is narrower and deeper than the corresponding first trench. A first oxide layer is formed on sidewalls and a bottom surface of each of the second trenches. The first trench is filled with an insulating layer.
摘要翻译：形成半导体器件的隔离层的方法包括在半导体衬底的隔离区域中形成第一沟槽。间隔件形成在每个第一沟槽的侧壁上。第二沟槽形成在对应的第一沟槽下方的隔离区域中。每个第二沟槽比相应的第一沟槽更窄和更深。第一氧化物层形成在每个第二沟槽的侧壁和底表面上。第一沟槽填充有绝缘层。

8. 发明授权

US07977205B2 Method of forming isolation layer of semiconductor device 失效
标题翻译：形成半导体器件隔离层的方法
公开(公告)号：US07977205B2
公开(公告)日：2011-07-12
申请号：US12815317
申请日：2010-06-14
申请人： Cha Deok Dong , Whee Won Cho , Jung Geun Kim , Cheol Mo Jeong , Suk Joong Kim , Jung Gu Lee
发明人： Cha Deok Dong , Whee Won Cho , Jung Geun Kim , Cheol Mo Jeong , Suk Joong Kim , Jung Gu Lee
IPC分类号： H01L21/76
CPC分类号： H01L27/11521 , H01L21/76232
摘要： A method of forming an isolation layer of a semiconductor device includes forming first trenches in an isolation region of a semiconductor substrate. Sidewalls and a bottom surface of each of the first trenches are oxidized by a radical oxidization process to form a first oxide layer. An oxidization-prevention spacer is formed on the sidewalls of each of the first trenches. Second trenches are formed in the isolation region below the corresponding first trenches, wherein each second trench is narrower and deeper than the corresponding first trench. The second trenches are filled with a second oxide layer. The first trenches are filled with an insulating layer.
摘要翻译：形成半导体器件的隔离层的方法包括在半导体衬底的隔离区域中形成第一沟槽。每个第一沟槽的侧壁和底表面被自由基氧化过程氧化以形成第一氧化物层。在每个第一沟槽的侧壁上形成防氧化间隔物。第二沟槽形成在对应的第一沟槽下方的隔离区域中，其中每个第二沟槽比相应的第一沟槽更窄和更深。第二沟槽填充有第二氧化物层。第一沟槽填充有绝缘层。

9. 发明授权

US07736991B2 Method of forming isolation layer of semiconductor device 失效
标题翻译：形成半导体器件隔离层的方法
公开(公告)号：US07736991B2
公开(公告)日：2010-06-15
申请号：US11617690
申请日：2006-12-28
申请人： Cha Deok Dong , Whee Won Cho , Jung Geun Kim , Cheol Mo Jeong , Suk Joong Kim , Jung Gu Lee
发明人： Cha Deok Dong , Whee Won Cho , Jung Geun Kim , Cheol Mo Jeong , Suk Joong Kim , Jung Gu Lee
IPC分类号： H01L21/76
CPC分类号： H01L27/11521 , H01L21/76232
摘要： A method of forming an isolation layer of a semiconductor device includes forming first trenches in an isolation region of a semiconductor substrate. A spacer is formed on sidewalls of each of the first trenches. Second trenches are formed in the isolation region below the corresponding first trenches. Each second trench is narrower and deeper than the corresponding first trench. A first oxide layer is formed on sidewalls and a bottom surface of each of the second trenches. The first trench is filled with an insulating layer.
摘要翻译：形成半导体器件的隔离层的方法包括在半导体衬底的隔离区域中形成第一沟槽。间隔件形成在每个第一沟槽的侧壁上。第二沟槽形成在对应的第一沟槽下方的隔离区域中。每个第二沟槽比相应的第一沟槽更窄和更深。第一氧化物层形成在每个第二沟槽的侧壁和底表面上。第一沟槽填充有绝缘层。

10. 发明申请

US20100304549A1 METHOD OF FORMING ISOLATION LAYER OF SEMICONDUCTOR DEVICE 失效
标题翻译：形成半导体器件隔离层的方法
公开(公告)号：US20100304549A1
公开(公告)日：2010-12-02
申请号：US12815317
申请日：2010-06-14
申请人： Cha Deok DONG , Whee Won Cho , Jung Geun Kim , Cheol Mo Jeong , Suk Joong Kim , Jung Gu Lee
发明人： Cha Deok DONG , Whee Won Cho , Jung Geun Kim , Cheol Mo Jeong , Suk Joong Kim , Jung Gu Lee
IPC分类号： H01L21/76
CPC分类号： H01L27/11521 , H01L21/76232
摘要： A method of forming an isolation layer of a semiconductor device includes forming first trenches in an isolation region of a semiconductor substrate. Sidewalls and a bottom surface of each of the first trenches are oxidized by a radical oxidization process to form a first oxide layer. An oxidization-prevention spacer is formed on the sidewalls of each of the first trenches. Second trenches are formed in the isolation region below the corresponding first trenches, wherein each second trench is narrower and deeper than the corresponding first trench. The second trenches are filled with a second oxide layer. The first trenches are filled with an insulating layer.
摘要翻译：形成半导体器件的隔离层的方法包括在半导体衬底的隔离区域中形成第一沟槽。每个第一沟槽的侧壁和底表面被自由基氧化过程氧化以形成第一氧化物层。在每个第一沟槽的侧壁上形成防氧化间隔物。第二沟槽形成在对应的第一沟槽下方的隔离区域中，其中每个第二沟槽比相应的第一沟槽更窄和更深。第二沟槽填充有第二氧化物层。第一沟槽填充有绝缘层。

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