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1. 发明授权

US08008133B2 Chip package with channel stiffener frame 有权
标题翻译：带通道加强筋的芯片封装
公开(公告)号：US08008133B2
公开(公告)日：2011-08-30
申请号：US12029305
申请日：2008-02-11
申请人： Eric Tosaya , Jun Zhai , Chia-Ken Leong , Tom Ley
发明人： Eric Tosaya , Jun Zhai , Chia-Ken Leong , Tom Ley
IPC分类号： H01L21/00
CPC分类号： H01L23/16 , H01L23/04 , H01L2224/16225 , H01L2224/48227 , H01L2224/73253 , H01L2924/15312 , H01L2924/15313 , H01L2924/19041 , H01L2924/19105
摘要： Various semiconductor chip packages and methods of making the same are provided. In one aspect, a method of manufacturing is provided that includes providing a substrate that has a first side and a first plurality of passive devices on the first side. A stiffener frame is coupled on the first side. The stiffener frame has first and second spaced apart opposing walls that define a channel in which the first plurality of passive devices is positioned, and a central opening that does not cover a central portion of the first side of the substrate.
摘要翻译：提供各种半导体芯片封装及其制造方法。一方面，提供一种制造方法，其包括提供在第一侧上具有第一侧和第一多个无源器件的衬底。加强框架连接在第一侧上。加强框架具有第一和第二间隔开的相对的壁，其限定了第一多个无源器件定位在其中的通道，以及不覆盖衬底的第一侧的中心部分的中心开口。

2. 发明申请

US20110241161A1 CHIP PACKAGE WITH CHANNEL STIFFENER FRAME 有权
标题翻译：带通道强化器框架的芯片包装
公开(公告)号：US20110241161A1
公开(公告)日：2011-10-06
申请号：US13158048
申请日：2011-06-10
申请人： Eric Tosaya , Jun Zhai , Chia-Ken Leong , Tom Ley
发明人： Eric Tosaya , Jun Zhai , Chia-Ken Leong , Tom Ley
IPC分类号： H01L27/02
CPC分类号： H01L23/16 , H01L23/04 , H01L2224/16225 , H01L2224/48227 , H01L2224/73253 , H01L2924/15312 , H01L2924/15313 , H01L2924/19041 , H01L2924/19105
摘要： Various semiconductor chip packages and methods of making the same are provided. In one aspect, a method of manufacturing is provided that includes providing a substrate that has a first side and a first plurality of passive devices on the first side. A stiffener frame is coupled on the first side. The stiffener frame has first and second spaced apart opposing walls that define a channel in which the first plurality of passive devices is positioned, and a central opening that does not cover a central portion of the first side of the substrate.
摘要翻译：提供各种半导体芯片封装及其制造方法。一方面，提供一种制造方法，其包括提供在第一侧上具有第一侧和第一多个无源器件的衬底。加强框架连接在第一侧上。加强框架具有第一和第二间隔开的相对的壁，其限定了第一多个无源器件定位在其中的通道，以及不覆盖衬底的第一侧的中心部分的中心开口。

3. 发明授权

US08405187B2 Chip package with channel stiffener frame 有权
标题翻译：带通道加强筋的芯片封装
公开(公告)号：US08405187B2
公开(公告)日：2013-03-26
申请号：US13158048
申请日：2011-06-10
申请人： Eric Tosaya , Jun Zhai , Chia-Ken Leong , Tom Ley
发明人： Eric Tosaya , Jun Zhai , Chia-Ken Leong , Tom Ley
IPC分类号： H01L29/00
CPC分类号： H01L23/16 , H01L23/04 , H01L2224/16225 , H01L2224/48227 , H01L2224/73253 , H01L2924/15312 , H01L2924/15313 , H01L2924/19041 , H01L2924/19105
摘要： Various semiconductor chip packages and methods of making the same are provided. In one aspect, a method of manufacturing is provided that includes providing a substrate that has a first side and a first plurality of passive devices on the first side. A stiffener frame is coupled on the first side. The stiffener frame has first and second spaced apart opposing walls that define a channel in which the first plurality of passive devices is positioned, and a central opening that does not cover a central portion of the first side of the substrate.
摘要翻译：提供各种半导体芯片封装及其制造方法。一方面，提供一种制造方法，其包括提供在第一侧上具有第一侧和第一多个无源器件的衬底。加强框架连接在第一侧上。加强框架具有第一和第二间隔开的相对的壁，其限定了第一多个无源器件定位在其中的通道，以及不覆盖衬底的第一侧的中心部分的中心开口。

4. 发明申请

US20090200659A1 Chip Package with Channel Stiffener Frame 有权
标题翻译：芯片封装与通道加强框架
公开(公告)号：US20090200659A1
公开(公告)日：2009-08-13
申请号：US12029305
申请日：2008-02-11
申请人： Eric Tosaya , Jun Zhai , Chia-Ken Leong , Tom Ley
发明人： Eric Tosaya , Jun Zhai , Chia-Ken Leong , Tom Ley
IPC分类号： H01L21/52 , H01L23/02
CPC分类号： H01L23/16 , H01L23/04 , H01L2224/16225 , H01L2224/48227 , H01L2224/73253 , H01L2924/15312 , H01L2924/15313 , H01L2924/19041 , H01L2924/19105
摘要： Various semiconductor chip packages and methods of making the same are provided. In one aspect, a method of manufacturing is provided that includes providing a substrate that has a first side and a first plurality of passive devices on the first side. A stiffener frame is coupled on the first side. The stiffener frame has first and second spaced apart opposing walls that define a channel in which the first plurality of passive devices is positioned, and a central opening that does not cover a central portion of the first side of the substrate.
摘要翻译：提供各种半导体芯片封装及其制造方法。一方面，提供一种制造方法，其包括提供在第一侧上具有第一侧和第一多个无源器件的衬底。加强框架连接在第一侧上。加强框架具有第一和第二间隔开的相对的壁，其限定了第一多个无源器件定位在其中的通道，以及不覆盖衬底的第一侧的中心部分的中心开口。

5. 发明申请

US20080284047A1 Chip Package with Stiffener Ring 审中-公开
标题翻译：芯片封装加强环
公开(公告)号：US20080284047A1
公开(公告)日：2008-11-20
申请号：US11748618
申请日：2007-05-15
申请人： Eric Tosaya , Jun Zhai , Chia-Ken Leong , Tom Ley
发明人： Eric Tosaya , Jun Zhai , Chia-Ken Leong , Tom Ley
IPC分类号： H01L23/28 , H01L21/00
CPC分类号： H01L23/16 , H01L23/053 , H01L23/10 , H01L2224/16225 , H01L2224/73253 , H01L2924/00011 , H01L2924/00014 , H01L2924/15312 , H01L2924/19105 , H01L2224/0401
摘要： Various semiconductor chip packages and methods of making the same are provided. In one aspect, a method of manufacturing is provided that includes providing a substrate that has a first side and a first plurality of passive devices in the first side. A polymeric stiffener ring is formed on the first side. The stiffener ring embeds the first plurality of passive devices without covering a central portion of the first surface of the substrate. A semiconductor chip is mounted on the central portion of the first surface of the substrate.
摘要翻译：提供各种半导体芯片封装及其制造方法。一方面，提供一种制造方法，其包括提供在第一侧具有第一侧和第一多个无源器件的衬底。在第一侧上形成聚合物加强环。加强环嵌入第一多个无源器件而不覆盖衬底的第一表面的中心部分。半导体芯片安装在基板的第一表面的中心部分上。

6. 发明授权

US06362522B1 Cool frame for protecting packaged electronic devices 有权
标题翻译：用于保护封装的电子设备的冷却框架
公开(公告)号：US06362522B1
公开(公告)日：2002-03-26
申请号：US09612589
申请日：2000-07-10
申请人： Tom Ley
发明人： Tom Ley
IPC分类号： H01L2312
CPC分类号： H01L23/562 , H01L23/36 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit arrangement having an integrated circuit package contains an integrated circuit device mounted to a surface of the package. A flat frame is placed on the package surface and substantially surrounds the device. The flat frame has a central opening that receives the integrated circuit device. The height of the flat frame is relative to the height of the circuit device. A heat sink is mounted to the circuit device such that the bottom of the heat sink contacts the upper surface of the integrated circuit device but, does not contact the flat frame.
摘要翻译：具有集成电路封装的集成电路装置包含安装到封装表面的集成电路装置。扁平框架放置在包装表面上并且基本上围绕该装置。扁平框架具有接收集成电路装置的中心开口。扁平框架的高度相对于电路装置的高度。散热器安装到电路装置，使得散热器的底部接触集成电路装置的上表面，但不接触平面框架。

7. 发明授权

US5249098A Semiconductor device package with solder bump electrical connections on an external surface of the package 失效
标题翻译：半导体器件封装，在封装的外表面具有焊料凸点电连接
公开(公告)号：US5249098A
公开(公告)日：1993-09-28
申请号：US922118
申请日：1992-07-28
申请人： Michael D. Rostoker , Tom Ley
发明人： Michael D. Rostoker , Tom Ley
IPC分类号： H01L23/64 , H05K1/03 , H05K1/18
CPC分类号： H05K1/183 , H01L23/642 , H01L2924/09701 , H01L2924/15311 , H05K1/0306
摘要： Wells are formed in an external surface of a semiconductor device package body. Capacitors are disposed within the wells at least partially, and preferably fully within the body. Cleaning channels are formed underneath the capacitors, for removing residual flux and/or solder.
摘要翻译：阱形成在半导体器件封装主体的外表面中。电容器至少部分地，优选地完全在身体内设置在孔内。清洁通道形成在电容器下面，用于去除残留的焊剂和/或焊料。

8. 发明授权

US06417563B1 Spring frame for protecting packaged electronic devices 有权
标题翻译：用于保护封装电子设备的弹簧框架
公开(公告)号：US06417563B1
公开(公告)日：2002-07-09
申请号：US09617102
申请日：2000-07-14
申请人： Jonathan Halderman , Mohammad Khan , Alexander C. Tain , Tom Ley
发明人： Jonathan Halderman , Mohammad Khan , Alexander C. Tain , Tom Ley
IPC分类号： H05K720
CPC分类号： H01L23/4093 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit arrangement comprising an integrated circuit package having a package board. An integrated circuit die is mounted to a surface of the package board. A spring frame is mounted to the package board surface at a pair of opposite frame bends. The spring frame has a central opening that receives the integrated circuit die. Sides of the spring frame away from the bends are raised from the package surface. A heat sink is mounted to the spring frame such that a bottom of the heat sink contacts an upper surface of the integrated circuit die as the heat sink pushes the sides of the spring frame toward the package surface.
摘要翻译：一种集成电路装置，包括具有封装板的集成电路封装。集成电路管芯安装到封装板的表面。弹簧框架以一对相对的框架弯曲部安装到封装板表面。弹簧框架具有接收集成电路管芯的中心开口。弹簧框架远离弯头的侧面从包装表面升高。散热器安装到弹簧框架上，使得当散热器将弹簧框架的侧面朝向封装表面推动时，散热器的底部接触集成电路管芯的上表面。

9. 发明授权

US5500555A Multi-layer semiconductor package substrate with thermally-conductive prepeg layer 失效
标题翻译：具有导热性预浸层的多层半导体封装基板
公开(公告)号：US5500555A
公开(公告)日：1996-03-19
申请号：US225860
申请日：1994-04-11
申请人： Tom Ley
发明人： Tom Ley
IPC分类号： H01L23/367 , H01L23/373 , H05K1/02 , H05K3/46 , H01L23/053 , H01L23/12 , H01L23/14
CPC分类号： H05K3/4641 , H01L23/367 , H01L23/3735 , H01L2224/48091 , H01L2224/48227 , H01L2224/49109 , H05K1/0203 , H05K1/0207 , H05K2201/0281 , H05K2201/029 , H05K2201/09681
摘要： Improved thermal characteristics are obtained in a multi-layer substrate for mounting a semiconductor device. A prepeg layer disposed in close proximity to or immediately adjacent to a semiconductor device is formed incorporating an integral, thermally-conductive mesh or screen. The prepeg layer is preferably a sandwich structure of two BT-resin layers (films), between which is disposed a copper screen. In this manner, heat is conducted away from an operating device by an integral part of the substrate, without the need for additional slugs or heat sink structures. Utility for multichip modules is also disclosed.
摘要翻译：在用于安装半导体器件的多层基板中获得改进的热特性。设置在靠近或紧邻半导体器件的预成型层被形成为包括一体的导热网或筛网。预成型层优选为两个BT-树脂层（膜）的夹层结构，其间设置有铜屏。以这种方式，通过衬底的整体部分将热量从操作装置传导出来，而不需要额外的s块或散热器结构。还公开了用于多芯片模块的实用程序。

10. 发明授权

US5210683A Recessed chip capacitor wells with cleaning channels on integrated circuit packages 失效
标题翻译：集成电路封装中带有清洁通道的残留芯片电容器
公开(公告)号：US5210683A
公开(公告)日：1993-05-11
申请号：US749128
申请日：1991-08-22
申请人： Tom Ley
发明人： Tom Ley
IPC分类号： H01L23/12 , H01L23/64 , H05K1/03 , H05K1/18
CPC分类号： H05K1/183 , H01L23/642 , H01L2924/0002 , H01L2924/09701 , H05K1/0306
摘要： Wells are formed in an external surface of a semiconductor device package body. Capacitors are disposed within the wells at least partially, and preferably fully within the body. Cleaning channels are formed underneath the capacitors, for removing residual flux and/or solder.

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