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    • 2. 发明授权
    • Orientation-independent multi-layer BEOL capacitor
    • 取向无关多层BEOL电容
    • US07701037B2
    • 2010-04-20
    • US11831208
    • 2007-07-31
    • Anil K. ChinthakindiEric Thompson
    • Anil K. ChinthakindiEric Thompson
    • H01L29/00
    • H01L27/0805H01L23/5223H01L2924/0002H01L2924/00
    • A plurality of interdigitized conductive fingers are arranged to form a substantially square configuration in each of a plurality of layers separated by a high dielectric constant material, wherein each of the plurality of interdigitized conductive fingers includes at least one bend of substantially ninety degrees. The plurality of interdigitized conductive fingers includes a first set of fingers that are connected to an anode terminal, and a second set of fingers that are connected to a cathode terminal. The plurality of layers includes a bottommost layer that is in closest proximity to a substrate relative to other layers of the plurality of layers. The bottommost layer does not include any fingers connected to the anode terminal.
    • 多个交叉指状的导电指状物被布置成在由高介电常数材料分离的多个层中的每一层中形成基本上正方形的构造,其中多个交叉指状导电指状物中的每一个包括至少一个基本上90度的弯曲部。 多个交叉指状的导电指状物包括连接到阳极端子的第一组指状物和连接到阴极端子的第二组指状物。 多个层包括相对于多个层中的其它层最靠近衬底的最底层。 最底层不包括连接到阳极端子的任何手指。
    • 3. 发明申请
    • ON-CHIP DECOUPLING CAPACITOR STRUCTURES
    • 片上解耦电容器结构
    • US20090039467A1
    • 2009-02-12
    • US11834956
    • 2007-08-07
    • Anil K. ChinthakindiEric Thompson
    • Anil K. ChinthakindiEric Thompson
    • H01L29/94
    • H01L29/945H01L23/5223H01L27/0805H01L2924/0002H01L2924/00
    • The present disclosure provides on-chip decoupling capacitor structures having trench capacitors integrated with planar capacitors to provide an improved overall capacitance density. In some embodiments, the structure includes at least one deep trench capacitor, at least one planar capacitor, and a metal layer interconnecting said deep trench and planar capacitors. In other embodiments, the structure includes at least one deep trench capacitor and a metal layer in electrical communication with the at least one deep trench capacitor. The at least one deep trench capacitor has a shallow trench isolation region, a doped region, an inner electrode, and a dielectric between the doped region and the inner electrode. The dielectric has an upper edge that terminates at a lower surface of the shallow trench isolation region.
    • 本公开提供具有与平面电容器集成的沟槽电容器的片上去耦电容器结构,以提供改进的总电容密度。 在一些实施例中,该结构包括至少一个深沟槽电容器,至少一个平面电容器和互连所述深沟槽和平面电容器的金属层。 在其他实施例中,该结构包括至少一个深沟槽电容器和与至少一个深沟槽电容器电连通的金属层。 所述至少一个深沟槽电容器在所述掺杂区域和所述内部电极之间具有浅沟槽隔离区域,掺杂区域,内部电极和电介质。 电介质具有终止在浅沟槽隔离区的下表面处的上边缘。
    • 7. 发明授权
    • On-chip decoupling capacitor structures
    • 片上去耦电容结构
    • US07968929B2
    • 2011-06-28
    • US11834961
    • 2007-08-07
    • Anil K. ChinthakindiEric Thompson
    • Anil K. ChinthakindiEric Thompson
    • H01L27/108H01L29/94
    • H01L29/945H01L23/5223H01L27/0805H01L2924/0002H01L2924/00
    • The present disclosure provides on-chip decoupling capacitor structures having trench capacitors integrated with a passive capacitor formed in the back-end-of-line wiring to provide an improved overall capacitance density. In some embodiments, the structure includes at least one deep trench capacitor and a passive capacitor formed in at least two back-end-of-line wiring levels. The trench and passive capacitors are in electrical communication through one of the wiring levels. In other embodiments, the structure includes at least one deep trench capacitor, a first back-end-of-line wiring level, and a second back-end-of-line wiring level. The deep trench capacitor with a dielectric that has an upper edge that terminates at a lower surface of a shallow trench isolation region. The first wiring level is in electrical communication with the trench capacitor. The second wiring level is vertically electrically connected to the first wiring level by vertical connectors so as to form a passive capacitor.
    • 本公开提供了片上去耦电容器结构,其具有与形成在后端线路布线中的无源电容集成的沟槽电容器,以提供改进的总电容密度。 在一些实施例中,该结构包括至少一个深沟槽电容器和形成在至少两个后端线路布线层中的无源电容器。 沟槽和无源电容器通过其中一个布线层进行电连接。 在其它实施例中,该结构包括至少一个深沟槽电容器,第一后端线路接线电平和第二后端线路布线电平。 具有电介质的深沟槽电容器,其具有终止于浅沟槽隔离区域的下表面处的上边缘。 第一布线电平与沟槽电容器电连通。 第二布线电平通过垂直连接器垂直电连接到第一布线层,以便形成无源电容器。
    • 8. 发明授权
    • On-chip decoupling capacitor structures
    • 片上去耦电容结构
    • US07816762B2
    • 2010-10-19
    • US11834956
    • 2007-08-07
    • Anil K. ChinthakindiEric Thompson
    • Anil K. ChinthakindiEric Thompson
    • H01L29/00
    • H01L29/945H01L23/5223H01L27/0805H01L2924/0002H01L2924/00
    • The present disclosure provides on-chip decoupling capacitor structures having trench capacitors integrated with planar capacitors to provide an improved overall capacitance density. In some embodiments, the structure includes at least one deep trench capacitor, at least one planar capacitor, and a metal layer interconnecting said deep trench and planar capacitors. In other embodiments, the structure includes at least one deep trench capacitor and a metal layer in electrical communication with the at least one deep trench capacitor. The at least one deep trench capacitor has a shallow trench isolation region, a doped region, an inner electrode, and a dielectric between the doped region and the inner electrode. The dielectric has an upper edge that terminates at a lower surface of the shallow trench isolation region.
    • 本公开提供具有与平面电容器集成的沟槽电容器的片上去耦电容器结构,以提供改进的总电容密度。 在一些实施例中,该结构包括至少一个深沟槽电容器,至少一个平面电容器和互连所述深沟槽和平面电容器的金属层。 在其他实施例中,该结构包括至少一个深沟槽电容器和与至少一个深沟槽电容器电连通的金属层。 所述至少一个深沟槽电容器在所述掺杂区域和所述内部电极之间具有浅沟槽隔离区域,掺杂区域,内部电极和电介质。 电介质具有终止在浅沟槽隔离区的下表面处的上边缘。
    • 9. 发明申请
    • ON-CHIP DECOUPLING CAPACITOR STRUCTURES
    • 片上解耦电容器结构
    • US20090039465A1
    • 2009-02-12
    • US11834961
    • 2007-08-07
    • Anil K. ChinthakindiEric Thompson
    • Anil K. ChinthakindiEric Thompson
    • H01L29/92
    • H01L29/945H01L23/5223H01L27/0805H01L2924/0002H01L2924/00
    • The present disclosure provides on-chip decoupling capacitor structures having trench capacitors integrated with a passive capacitor formed in the back-end-of-line wiring to provide an improved overall capacitance density. In some embodiments, the structure includes at least one deep trench capacitor and a passive capacitor formed in at least two back-end-of-line wiring levels. The trench and passive capacitors are in electrical communication through one of the wiring levels. In other embodiments, the structure includes at least one deep trench capacitor, a first back-end-of-line wiring level, and a second back-end-of-line wiring level. The deep trench capacitor with a dielectric that has an upper edge that terminates at a lower surface of a shallow trench isolation region. The first wiring level is in electrical communication with the trench capacitor. The second wiring level is vertically electrically connected to the first wiring level by vertical connectors so as to form a passive capacitor.
    • 本公开提供了片上去耦电容器结构,其具有与形成在后端线路布线中的无源电容集成的沟槽电容器,以提供改进的总电容密度。 在一些实施例中,该结构包括形成在至少两个后端线路布线层中的至少一个深沟槽电容器和无源电容器。 沟槽和无源电容器通过其中一个布线层进行电连接。 在其它实施例中,该结构包括至少一个深沟槽电容器,第一后端线路接线电平和第二后端线路布线电平。 具有电介质的深沟槽电容器,其具有终止于浅沟槽隔离区域的下表面处的上边缘。 第一布线电平与沟槽电容器电连通。 第二布线电平通过垂直连接器垂直电连接到第一布线层,以便形成无源电容器。