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    • 4. 发明授权
    • Level shifter design
    • 电平移位器设计
    • US08324955B2
    • 2012-12-04
    • US13051343
    • 2011-03-18
    • Alan RothYing-Chih HsuJustin ShiEric Soenen
    • Alan RothYing-Chih HsuJustin ShiEric Soenen
    • H03L5/00
    • H03K19/018507H03K3/037
    • A level shifter receives an input voltage signal and produces an output voltage signal. The level shifter includes a first inverter, configured to operate at a potential difference between a first voltage V1 and a second voltage V2. The output from the invert is capacitively coupled to an input of a latch circuit via a capacitor. The capacitor has a first terminal connected to the output terminal of the first inverter, and further has a second terminal. The level shifter has a resistor connected to a third voltage V3 and to the capacitor for tying the input to the latch circuit to a desired voltage. The latch circuit is configured to operate at a potential difference between a fourth voltage V4 and a fifth voltage V5. The latch has an input node connected to the resistor and the capacitor, and further has an output node connected to an output node of the level shifter.
    • 电平移位器接收输入电压信号并产生输出电压信号。 电平移位器包括第一反相器,其被配置为在第一电压V1和第二电压V2之间的电位差下工作。 反相器的输出通过电容电容耦合到锁存电路的输入端。 电容器具有连接到第一反相器的输出端子的第一端子,并且还具有第二端子。 电平移位器具有连接到第三电压V3的电阻器和用于将输入端连接到锁存电路的电容器以达到期望的电压。 闩锁电路被配置为在第四电压V4和第五电压V5之间的电位差下工作。 锁存器具有连接到电阻器和电容器的输入节点,并且还具有连接到电平移位器的输出节点的输出节点。
    • 7. 发明申请
    • Class D Amplifier Control Circuit and Method
    • D类放大器控制电路及方法
    • US20110006844A1
    • 2011-01-13
    • US12858310
    • 2010-08-17
    • Eric SoenenAlan RothJustin ShiMartin Kinyua
    • Eric SoenenAlan RothJustin ShiMartin Kinyua
    • H03F3/217
    • H03F3/2173
    • Circuit and method for a Class D amplifier. In one exemplary embodiment, an audio amplifier is disclosed. A closed loop configuration for driving high and low side driver transistors is provided, each circuit is compatible with advanced sub micron semiconductor processes. The analog time varying input is coupled to one input of a sigma delta analog to digital converter. A feedback signal from the output is also input to the analog to digital converter. A bit stream is output by the analog to digital converter. A decimator receives this bit stream and downconverts the samples to digital values at a lower frequency. A digital filter with adaptable coefficients is used to filter that signal and a digital pulse width modulator then develops an analog differential PWM signal. A predriver inputs the PWM signal and derives the output gating signals to control the high and low side drivers of a Class D amplifier.
    • D类放大器的电路和方法。 在一个示例性实施例中,公开了一种音频放大器。 提供用于驱动高侧和低侧驱动晶体管的闭环配置,每个电路与先进的亚微米半导体工艺兼容。 模拟时变输入耦合到Σ-Δ模数转换器的一个输入端。 来自输出的反馈信号也被输入到模数转换器。 位流由模数转换器输出。 抽取器接收该位流,并以较低的频率将样本下变频为数字值。 使用具有适应系数的数字滤波器来对该信号进行滤波,并且数字脉宽调制器然后开发模拟差分PWM信号。 预驱动器输入PWM信号并导出输出门控信号以控制D类放大器的高侧和低侧驱动器。
    • 9. 发明申请
    • CLASS D AMPLIFIER CONTROL CIRCUIT AND METHOD
    • 等级放大器控制电路和方法
    • US20100045376A1
    • 2010-02-25
    • US12197967
    • 2008-08-25
    • Eric SoenenAlan RothJustin Shi
    • Eric SoenenAlan RothJustin Shi
    • H03F3/217
    • H03F3/2173
    • Circuit and method for a Class D amplifier. In one exemplary embodiment, an audio amplifier is disclosed. A closed loop configuration for driving high and low side driver transistors is provided, each circuit is compatible with advanced sub micron semiconductor processes. The analog time varying input is coupled to one input of a sigma delta analog to digital converter. A feedback signal from the output is also input to the analog to digital converter. A bit stream is output by the analog to digital converter. A decimator receives this bit stream and downconverts the samples to digital values at a lower frequency. A digital filter with adaptable coefficients is used to filter that signal and a digital pulse width modulator then develops an analog differential PWM signal. A predriver inputs the PWM signal and derives the output gating signals to control the high and low side drivers of a Class D amplifier.
    • D类放大器的电路和方法。 在一个示例性实施例中,公开了一种音频放大器。 提供用于驱动高侧和低侧驱动晶体管的闭环配置,每个电路与先进的亚微米半导体工艺兼容。 模拟时变输入耦合到Σ-Δ模数转换器的一个输入端。 来自输出的反馈信号也被输入到模数转换器。 位流由模数转换器输出。 抽取器接收该位流,并以较低的频率将样本下变频为数字值。 使用具有适应系数的数字滤波器来对该信号进行滤波,并且数字脉宽调制器然后开发模拟差分PWM信号。 预驱动器输入PWM信号并导出输出门控信号以控制D类放大器的高侧和低侧驱动器。