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1. 发明授权

US06981128B2 Atomic quad word storage in a simultaneous multithreaded system 失效
标题翻译：原子四字存储在同时多线程系统中
公开(公告)号：US06981128B2
公开(公告)日：2005-12-27
申请号：US10422664
申请日：2003-04-24
申请人： Eric J. Fluhr , Joaquin Hinojosa , Ronald N. Kalla , Bruce J. Ronchetti , Balaram Sinharoy
发明人： Eric J. Fluhr , Joaquin Hinojosa , Ronald N. Kalla , Bruce J. Ronchetti , Balaram Sinharoy
IPC分类号： G06F9/312 , G06F9/38 , G06F9/40 , G06F9/46
CPC分类号： G06F9/3834 , G06F9/30036 , G06F9/3004 , G06F9/30087 , G06F9/3824 , G06F9/3851
摘要： In a system with multiple execution units, instructions are queued to allow efficient dispatching. One load/store unit (LSU) may have a store instruction pending to a real address and a second LSU may have a load instruction pending to the same real address. An SMT system has an atomic store quad word (SQW) instruction with a data path that is only double wide and the SQW requires two cycles to complete. The SMT system requires a method to prevent between collisions in a store reorder queue (SRQ) STQ. The real address of a load word (LW) one thread is compared to the real addresses in the SRQ of the second thread. If the SQW with a real address matching the real address of the LW has not committed both of its double words, then the LW of the second thread is rejected.
摘要翻译：在具有多个执行单元的系统中，排队等待指令进行高效的调度。一个加载/存储单元（LSU）可以具有等待到实际地址的存储指令，并且第二LSU可以具有等待到同一实际地址的加载指令。 SMT系统具有原子存储四字（SQW）指令，数据路径仅为双倍宽，SQW需要两个周期才能完成。 SMT系统需要一种方法来防止存储重新排序队列（SRQ）STQ中的冲突。一个线程的加载字（LW）的真实地址与第二个线程的SRQ中的实际地址进行比较。如果具有与LW的实际地址匹配的实际地址的SQW没有提交两个双字，则第二个线程的LW被拒绝。

2. 发明授权

US07660965B2 Method to optimize effective page number to real page number translation path from page table entries match resumption of execution stream 有权
标题翻译：从页表条目优化有效页码到实际页码转换路径的方法匹配恢复执行流
公开(公告)号：US07660965B2
公开(公告)日：2010-02-09
申请号：US11969988
申请日：2008-01-07
申请人： Joaquin Hinojosa , Sheldon B. Levenstein , Bruce Joseph Ronchetti
发明人： Joaquin Hinojosa , Sheldon B. Levenstein , Bruce Joseph Ronchetti
IPC分类号： G06F12/10 , G06F13/28
CPC分类号： G06F12/1027 , G06F2212/681
摘要： A method, system and computer program product for optimizing EPN to RPN translation when a data miss occurs. The method, system and computer program product take advantage of the high-likelihood of finding the matching PTE in the first half of the PTEG and utilize early data-coming signals from the L2 cache to prime the data-flow pipe to the D-ERAT arrays and requesting a joint steal cycle for executing the write into the D-ERAT and a restart request for re-dispatching the next-to-complete instruction.
摘要翻译：一种在数据丢失发生时优化EPN到RPN转换的方法，系统和计算机程序产品。该方法，系统和计算机程序产品利用在PTEG的前半部分找到匹配的PTE的高似然性，并利用来自L2缓存的早期数据来信号将数据流管道引导到D-ERAT 阵列并请求执行对D-ERAT的写入的联合窃取循环以及重新发送下一条完整指令的重新启动请求。

3. 发明授权

US5502732A Method for testing ECC logic 失效
标题翻译： ECC逻辑测试方法
公开(公告)号：US5502732A
公开(公告)日：1996-03-26
申请号：US123829
申请日：1993-09-20
申请人： Ronald X. Arroyo , William E. Burky , Tricia A. Gruwell , Joaquin Hinojosa
发明人： Ronald X. Arroyo , William E. Burky , Tricia A. Gruwell , Joaquin Hinojosa
IPC分类号： G06F11/10 , G06F11/22 , G06F11/267 , H03M13/01 , H03M13/00
CPC分类号： G11C29/02 , G06F11/2215 , G06F11/2284 , H03M13/01 , G06F11/1044
摘要： A system and method for checking the test logic contained in a computer memory system during POST such that any errors can be determined and made available to the system software prior to beginning processing operations. Single and double bit errors are induced which the ECC logic must identify and correct. The CPU compares the data that is written to memory with the data that is read back. Thus, since it is known that an error occurred, due to the induced error provided by the present invention, identical data will verify that the ECC correction logic is working properly. More specifically, a multiplexer is provided in the data write path which substitutes a constant set of identical bits for the actual data generated by the CPU. ECC bits are generated based on the actual generated test data, rather than the inserted identical bits. The substituted data bits and generated ECC bits are then stored in memory. An error condition is identified when the data and ECC code is read back from memory. The correction logic then corrects the data, in the case of a single bit error, such that the data read by the CPU is the same as the originally generated data.
摘要翻译：一种用于在POST期间检查包含在计算机存储器系统中的测试逻辑的系统和方法，使得可以在开始处理操作之前确定任何错误并使系统软件可用。引起ECC逻辑必须识别和纠正的单位和双位错误。 CPU将写入内存的数据与读回的数据进行比较。因此，由于已知发生错误，由于本发明提供的感应错误，相同的数据将验证ECC校正逻辑是否正常工作。更具体地，在数据写入路径中提供多路复用器，其将由CPU产生的实际数据替换为相同位的常数集合。基于实际产生的测试数据而不是插入的相同位产生ECC位。然后将取代的数据位和生成的ECC位存储在存储器中。当从存储器读取数据和ECC代码时，会识别出错误条件。然后，校正逻辑在单个位错误的情况下校正数据，使得CPU读取的数据与原始生成的数据相同。

4. 发明授权

US07389400B2 Apparatus and method for selectively invalidating entries in an address translation cache 有权
标题翻译：用于选择性地使地址转换高速缓存中的条目无效的装置和方法
公开(公告)号：US07389400B2
公开(公告)日：2008-06-17
申请号：US11304136
申请日：2005-12-15
申请人： Michael J. Corrigan , Paul LuVerne Godtland , Joaquin Hinojosa , Cathy May , Naresh Nayar , Edward John Silha
发明人： Michael J. Corrigan , Paul LuVerne Godtland , Joaquin Hinojosa , Cathy May , Naresh Nayar , Edward John Silha
IPC分类号： G06F12/00
CPC分类号： G06F12/1036 , G06F12/126 , G06F2212/1016 , G06F2212/683
摘要： An apparatus and method selectively invalidate entries in an address translation cache instead of invalidating all, or nearly all, entries. One or more translation mode bits are provided in each entry in the address translation cache. These translation mode bits may be set according to the addressing mode used to create the cache entry. One or more “hint bits” are defined in an instruction that allow specifying which of the entries in the address translation cache are selectively preserved during an invalidation operation according to the value(s) of the translation mode bit(s). In the alternative, multiple instructions may be defined to preserve entries in the address translation cache that have specified addressing modes. In this manner, more intelligence is used to recognize that some entries in the address translation cache may be valid after a task or partition switch, and may therefore be retained, while other entries in the address translation cache are invalidated.
摘要翻译：一种装置和方法选择性地使地址转换高速缓存中的条目无效，而不是使所有或几乎所有条目无效。在地址转换高速缓存中的每个条目中提供一个或多个翻译模式位。可以根据用于创建高速缓存条目的寻址模式来设置这些转换模式位。在指令中定义一个或多个“提示位”，该指令允许根据翻译模式位的值来指定在无效操作期间选择性地保留地址转换高速缓存中的哪些条目。在替代方案中，可以定义多个指令以保留具有指定寻址模式的地址转换高速缓存中的条目。以这种方式，使用更多的智能来识别地址转换高速缓存中的一些条目在任务或分区切换之后可能是有效的，并且因此可以被保留，而地址转换高速缓存中的其他条目是无效的。

5. 发明授权

US07350051B2 Method to optimize effective page number to real page number translation path from page table entries match resumption of execution stream 有权
标题翻译：从页表条目优化有效页码到实际页码转换路径的方法匹配恢复执行流
公开(公告)号：US07350051B2
公开(公告)日：2008-03-25
申请号：US11054277
申请日：2005-02-09
申请人： Joaquin Hinojosa , Sheldon B. Levenstein , Bruce Joseph Ronchetti
发明人： Joaquin Hinojosa , Sheldon B. Levenstein , Bruce Joseph Ronchetti
IPC分类号： G06F12/10 , G06F13/28
CPC分类号： G06F12/1027 , G06F2212/681
摘要： A method, system and computer program product for optimizing EPN to RPN translation when a data miss occurs. The method, system and computer program product take advantage of the high-likelihood of finding the matching PTE in the first half of the PTEG and utilize early data-coming signals from the L2 cache to prime the data-flow pipe to the D-ERAT arrays and requesting a joint steal cycle for executing the write into the D-ERAT and a restart request for re-dispatching the next-to-complete instruction.
摘要翻译：一种在数据丢失发生时优化EPN到RPN转换的方法，系统和计算机程序产品。该方法，系统和计算机程序产品利用在PTEG的前半部分找到匹配的PTE的高似然性，并利用来自L2缓存的早期数据来信号将数据流管道引导到D-ERAT 阵列并请求执行对D-ERAT的写入的联合窃取循环以及重新发送下一条完整指令的重新启动请求。

6. 发明授权

US07822942B2 Selectively invalidating entries in an address translation cache 有权
标题翻译：选择性地使地址转换缓存中的条目无效
公开(公告)号：US07822942B2
公开(公告)日：2010-10-26
申请号：US12054538
申请日：2008-03-25
申请人： Michael J. Corrigan , Paul LuVerne Godtland , Joaquin Hinojosa , Cathy May , Naresh Nayar , Edward John Silha
发明人： Michael J. Corrigan , Paul LuVerne Godtland , Joaquin Hinojosa , Cathy May , Naresh Nayar , Edward John Silha
IPC分类号： G06F13/00
CPC分类号： G06F12/1036 , G06F12/126 , G06F2212/1016 , G06F2212/683
摘要： An apparatus and method selectively invalidate entries in an address translation cache instead of invalidating all, or nearly all, entries. One or more translation mode bits are provided in each entry in the address translation cache. These translation mode bits may be set according to the addressing mode used to create the cache entry. One or more “hint bits” are defined in an instruction that allow specifying which of the entries in the address translation cache are selectively preserved during an invalidation operation according to the value(s) of the translation mode bit(s). In the alternative, multiple instructions may be defined to preserve entries in the address translation cache that have specified addressing modes. In this manner, more intelligence is used to recognize that some entries in the address translation cache may be valid after a task or partition switch, and may therefore be retained, while other entries are invalidated.
摘要翻译：一种装置和方法选择性地使地址转换高速缓存中的条目无效，而不是使所有或几乎所有条目无效。在地址转换高速缓存中的每个条目中提供一个或多个翻译模式位。可以根据用于创建高速缓存条目的寻址模式来设置这些转换模式位。在指令中定义一个或多个“提示位”，该指令允许根据翻译模式位的值来指定在无效操作期间选择性地保留地址转换高速缓存中的哪些条目。在替代方案中，可以定义多个指令以保留具有指定寻址模式的地址转换高速缓存中的条目。以这种方式，使用更多的智能来识别地址转换高速缓存中的一些条目在任务或分区切换之后可能是有效的，并且因此可以被保留，而其他条目无效。

7. 发明申请

US20060179264A1 Method to optimize effective page number to real page number translation path from page table entries match resumption of execution stream 有权
标题翻译：从页表条目优化有效页码到实际页码转换路径的方法匹配恢复执行流
公开(公告)号：US20060179264A1
公开(公告)日：2006-08-10
申请号：US11054277
申请日：2005-02-09
申请人： Joaquin Hinojosa , Sheldon Levenstein , Bruce Ronchetti
发明人： Joaquin Hinojosa , Sheldon Levenstein , Bruce Ronchetti
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F2212/681
摘要： A method, system and computer program product for optimizing EPN to RPN translation when a data miss occurs. The method, system and computer program product take advantage of the high-likelihood of finding the matching PTE in the first half of the PTEG and utilize early data-coming signals from the L2 cache to prime the data-flow pipe to the D-ERAT arrays and requesting a joint steal cycle for executing the write into the D-ERAT and a restart request for re-dispatching the next-to-complete instruction.
摘要翻译：一种在数据丢失发生时优化EPN到RPN转换的方法，系统和计算机程序产品。该方法，系统和计算机程序产品利用在PTEG的前半部分找到匹配的PTE的高似然性，并利用来自L2缓存的早期数据来信号将数据流管道引导到D-ERAT 阵列并请求执行对D-ERAT的写入的联合窃取循环以及重新发送下一条完整指令的重新启动请求。

8. 发明授权

US07752354B2 Auxiliary mechanism to manage instruction restart and restart coming in a lookahead processor 有权
标题翻译：辅助机制，用于管理指令重新启动和重新启动进入前瞻处理器
公开(公告)号：US07752354B2
公开(公告)日：2010-07-06
申请号：US11055844
申请日：2005-02-11
申请人： Miles Robert Dooley , Joaquin Hinojosa , Bruce Joseph Ronchetti , Anthony Saporito
发明人： Miles Robert Dooley , Joaquin Hinojosa , Bruce Joseph Ronchetti , Anthony Saporito
IPC分类号： G06F3/00 , G06F12/00
CPC分类号： G06F9/3861 , G06F9/3842 , G06F11/141
摘要： A management system that controls a restart interface in a data processing system. The management system switches control of the interface from a distributed network managed by the caches to the management system. The management system is capable of detecting errors and seizing control of the interface in order to remedy any errors that occur within the interface.
摘要翻译：控制数据处理系统中的重启界面的管理系统。管理系统将接口控制从高速缓存管理的分布式网络切换到管理系统。管理系统能够检测错误并占用接口的控制，以补救接口内发生的任何错误。

9. 发明申请

US20080168254A1 SELECTIVELY INVALIDATING ENTRIES IN AN ADDRESS TRANSLATION CACHE 有权
标题翻译：在地址翻译缓存中选择无效的入口
公开(公告)号：US20080168254A1
公开(公告)日：2008-07-10
申请号：US12054538
申请日：2008-03-25
申请人： Michael J. Corrigan , Paul LuVerne Godtland , Joaquin Hinojosa , Cathy May , Naresh Nayar , Edward John Silha
发明人： Michael J. Corrigan , Paul LuVerne Godtland , Joaquin Hinojosa , Cathy May , Naresh Nayar , Edward John Silha
IPC分类号： G06F9/34
CPC分类号： G06F12/1036 , G06F12/126 , G06F2212/1016 , G06F2212/683
摘要： An apparatus and method selectively invalidate entries in an address translation cache instead of invalidating all, or nearly all, entries. One or more translation mode bits are provided in each entry in the address translation cache. These translation mode bits may be set according to the addressing mode used to create the cache entry. One or more “hint bits” are defined in an instruction that allow specifying which of the entries in the address translation cache are selectively preserved during an invalidation operation according to the value(s) of the translation mode bit(s). In the alternative, multiple instructions may be defined to preserve entries in the address translation cache that have specified addressing modes. In this manner, more intelligence is used to recognize that some entries in the address translation cache may be valid after a task or partition switch, and may therefore be retained, while other entries are invalidated.
摘要翻译：一种装置和方法选择性地使地址转换高速缓存中的条目无效，而不是使所有或几乎所有条目无效。在地址转换高速缓存中的每个条目中提供一个或多个翻译模式位。可以根据用于创建高速缓存条目的寻址模式来设置这些转换模式位。在指令中定义一个或多个“提示位”，该指令允许根据翻译模式位的值来指定在无效操作期间选择性地保留地址转换高速缓存中的哪些条目。在替代方案中，可以定义多个指令以保留具有指定寻址模式的地址转换高速缓存中的条目。以这种方式，使用更多的智能来识别地址转换高速缓存中的一些条目在任务或分区切换之后可能是有效的，并且因此可以被保留，而其他条目无效。

10. 发明申请

US20080104599A1 METHOD TO OPTIMIZE EFFECTIVE PAGE NUMBER TO REAL PAGE NUMBER TRANSLATION PATH FROM PAGE TABLE ENTRIES MATCH RESUMPTION OF EXECUTION STREAM 有权
标题翻译：将有效页数优化到实际页码的方法从页表转换路径执行步骤的恢复
公开(公告)号：US20080104599A1
公开(公告)日：2008-05-01
申请号：US11969988
申请日：2008-01-07
申请人： Joaquin Hinojosa , Sheldon Levenstein , Bruce Ronchetti
发明人： Joaquin Hinojosa , Sheldon Levenstein , Bruce Ronchetti
IPC分类号： G06F9/46
CPC分类号： G06F12/1027 , G06F2212/681
摘要： A method, system and computer program product for optimizing EPN to RPN translation when a data miss occurs. The method, system and computer program product take advantage of the high-likelihood of finding the matching PTE in the first half of the PTEG and utilize early data-coming signals from the L2 cache to prime the data-flow pipe to the D-ERAT arrays and requesting a joint steal cycle for executing the write into the D-ERAT and a restart request for re-dispatching the next-to-complete instruction.
摘要翻译：一种在数据丢失发生时优化EPN到RPN转换的方法，系统和计算机程序产品。该方法，系统和计算机程序产品利用在PTEG的前半部分找到匹配的PTE的高似然性，并利用来自L2缓存的早期数据来信号将数据流管道引导到D-ERAT 阵列并请求执行对D-ERAT的写入的联合窃取循环以及重新发送下一条完整指令的重新启动请求。

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