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1. 发明授权

US07822942B2 Selectively invalidating entries in an address translation cache 有权
标题翻译：选择性地使地址转换缓存中的条目无效
公开(公告)号：US07822942B2
公开(公告)日：2010-10-26
申请号：US12054538
申请日：2008-03-25
申请人： Michael J. Corrigan , Paul LuVerne Godtland , Joaquin Hinojosa , Cathy May , Naresh Nayar , Edward John Silha
发明人： Michael J. Corrigan , Paul LuVerne Godtland , Joaquin Hinojosa , Cathy May , Naresh Nayar , Edward John Silha
IPC分类号： G06F13/00
CPC分类号： G06F12/1036 , G06F12/126 , G06F2212/1016 , G06F2212/683
摘要： An apparatus and method selectively invalidate entries in an address translation cache instead of invalidating all, or nearly all, entries. One or more translation mode bits are provided in each entry in the address translation cache. These translation mode bits may be set according to the addressing mode used to create the cache entry. One or more “hint bits” are defined in an instruction that allow specifying which of the entries in the address translation cache are selectively preserved during an invalidation operation according to the value(s) of the translation mode bit(s). In the alternative, multiple instructions may be defined to preserve entries in the address translation cache that have specified addressing modes. In this manner, more intelligence is used to recognize that some entries in the address translation cache may be valid after a task or partition switch, and may therefore be retained, while other entries are invalidated.
摘要翻译：一种装置和方法选择性地使地址转换高速缓存中的条目无效，而不是使所有或几乎所有条目无效。在地址转换高速缓存中的每个条目中提供一个或多个翻译模式位。可以根据用于创建高速缓存条目的寻址模式来设置这些转换模式位。在指令中定义一个或多个“提示位”，该指令允许根据翻译模式位的值来指定在无效操作期间选择性地保留地址转换高速缓存中的哪些条目。在替代方案中，可以定义多个指令以保留具有指定寻址模式的地址转换高速缓存中的条目。以这种方式，使用更多的智能来识别地址转换高速缓存中的一些条目在任务或分区切换之后可能是有效的，并且因此可以被保留，而其他条目无效。

2. 发明申请

US20080168254A1 SELECTIVELY INVALIDATING ENTRIES IN AN ADDRESS TRANSLATION CACHE 有权
标题翻译：在地址翻译缓存中选择无效的入口
公开(公告)号：US20080168254A1
公开(公告)日：2008-07-10
申请号：US12054538
申请日：2008-03-25
申请人： Michael J. Corrigan , Paul LuVerne Godtland , Joaquin Hinojosa , Cathy May , Naresh Nayar , Edward John Silha
发明人： Michael J. Corrigan , Paul LuVerne Godtland , Joaquin Hinojosa , Cathy May , Naresh Nayar , Edward John Silha
IPC分类号： G06F9/34
CPC分类号： G06F12/1036 , G06F12/126 , G06F2212/1016 , G06F2212/683
摘要： An apparatus and method selectively invalidate entries in an address translation cache instead of invalidating all, or nearly all, entries. One or more translation mode bits are provided in each entry in the address translation cache. These translation mode bits may be set according to the addressing mode used to create the cache entry. One or more “hint bits” are defined in an instruction that allow specifying which of the entries in the address translation cache are selectively preserved during an invalidation operation according to the value(s) of the translation mode bit(s). In the alternative, multiple instructions may be defined to preserve entries in the address translation cache that have specified addressing modes. In this manner, more intelligence is used to recognize that some entries in the address translation cache may be valid after a task or partition switch, and may therefore be retained, while other entries are invalidated.
摘要翻译：一种装置和方法选择性地使地址转换高速缓存中的条目无效，而不是使所有或几乎所有条目无效。在地址转换高速缓存中的每个条目中提供一个或多个翻译模式位。可以根据用于创建高速缓存条目的寻址模式来设置这些转换模式位。在指令中定义一个或多个“提示位”，该指令允许根据翻译模式位的值来指定在无效操作期间选择性地保留地址转换高速缓存中的哪些条目。在替代方案中，可以定义多个指令以保留具有指定寻址模式的地址转换高速缓存中的条目。以这种方式，使用更多的智能来识别地址转换高速缓存中的一些条目在任务或分区切换之后可能是有效的，并且因此可以被保留，而其他条目无效。

3. 发明授权

US07389400B2 Apparatus and method for selectively invalidating entries in an address translation cache 有权
标题翻译：用于选择性地使地址转换高速缓存中的条目无效的装置和方法
公开(公告)号：US07389400B2
公开(公告)日：2008-06-17
申请号：US11304136
申请日：2005-12-15
申请人： Michael J. Corrigan , Paul LuVerne Godtland , Joaquin Hinojosa , Cathy May , Naresh Nayar , Edward John Silha
发明人： Michael J. Corrigan , Paul LuVerne Godtland , Joaquin Hinojosa , Cathy May , Naresh Nayar , Edward John Silha
IPC分类号： G06F12/00
CPC分类号： G06F12/1036 , G06F12/126 , G06F2212/1016 , G06F2212/683
摘要： An apparatus and method selectively invalidate entries in an address translation cache instead of invalidating all, or nearly all, entries. One or more translation mode bits are provided in each entry in the address translation cache. These translation mode bits may be set according to the addressing mode used to create the cache entry. One or more “hint bits” are defined in an instruction that allow specifying which of the entries in the address translation cache are selectively preserved during an invalidation operation according to the value(s) of the translation mode bit(s). In the alternative, multiple instructions may be defined to preserve entries in the address translation cache that have specified addressing modes. In this manner, more intelligence is used to recognize that some entries in the address translation cache may be valid after a task or partition switch, and may therefore be retained, while other entries in the address translation cache are invalidated.
摘要翻译：一种装置和方法选择性地使地址转换高速缓存中的条目无效，而不是使所有或几乎所有条目无效。在地址转换高速缓存中的每个条目中提供一个或多个翻译模式位。可以根据用于创建高速缓存条目的寻址模式来设置这些转换模式位。在指令中定义一个或多个“提示位”，该指令允许根据翻译模式位的值来指定在无效操作期间选择性地保留地址转换高速缓存中的哪些条目。在替代方案中，可以定义多个指令以保留具有指定寻址模式的地址转换高速缓存中的条目。以这种方式，使用更多的智能来识别地址转换高速缓存中的一些条目在任务或分区切换之后可能是有效的，并且因此可以被保留，而地址转换高速缓存中的其他条目是无效的。

4. 发明授权

US07844781B2 Method, apparatus, and computer program product for accessing process local storage of another process 有权
标题翻译：用于访问另一进程的本地存储的方法，装置和计算机程序产品
公开(公告)号：US07844781B2
公开(公告)日：2010-11-30
申请号：US11360351
申请日：2006-02-23
申请人： Michael J. Corrigan , Paul LuVerne Godtland , Richard Karl Kirkman , Wade Byron Ouren , George David Timms, Jr.
发明人： Michael J. Corrigan , Paul LuVerne Godtland , Richard Karl Kirkman , Wade Byron Ouren , George David Timms, Jr.
IPC分类号： G06F12/06
CPC分类号： G06F9/544
摘要： An operating system kernel includes an attach mechanism and a detach mechanism. In addition, processes are tagged with an access attribute identifying the process as either a client process or a server process. Based on the access attribute, the operating system kernel lays out the process local address space differently depending on whether the process is a client process or a server process. A server process can “attach” to a client process and reference all of the client process' local storage as though it were its own. The server process continues to reference its own process local storage, but in addition, it can reference the other storage, using the client process' local addresses. When access to the other storage is no longer needed, the server process can “detach” from the client process. Once detached, the other storage can no longer be referenced.
摘要翻译：操作系统内核包括连接机构和分离机构。此外，进程用标识进程的访问属性标记为客户端进程或服务器进程。基于访问属性，操作系统内核会根据进程是客户端进程还是服务器进程来区分进程本地地址空间。服务器进程可以“附加”到客户端进程，并引用所有客户端进程的本地存储，就像它是自己的。服务器进程继续引用其自身的进程本地存储，但另外也可以引用其他存储，使用客户端进程的本地地址。当不再需要访问其他存储时，服务器进程可以从客户端进程“脱离”。一旦分离，其他存储就不能再被引用了。

5. 发明授权

US06574721B1 Apparatus and method for providing simultaneous local and global addressing using software to distinguish between local and global addresses 失效
公开(公告)号：US06574721B1
公开(公告)日：2003-06-03
申请号：US09387343
申请日：1999-08-31
申请人： Patrick James Christenson , Brian Eldridge Clark , Michael J. Corrigan , Paul LuVerne Godtland , Richard Karl Kirkman , Donald Arthur Morrison , Scott Alan Plaetzer
发明人： Patrick James Christenson , Brian Eldridge Clark , Michael J. Corrigan , Paul LuVerne Godtland , Richard Karl Kirkman , Donald Arthur Morrison , Scott Alan Plaetzer
IPC分类号： G06F1206
CPC分类号： G06F12/0284 , G06F12/1036 , G06F12/109
摘要： An apparatus and method provide simultaneous local and global addressing capabilities in a computer system. A global address space is defined that may be accessed by all processes. In addition, each process has a local address space that is local (and therefore available) only to that process. An address space processor is implemented in software to perform system functions that distinguish between local addresses and global addresses. In the preferred embodiments, the local address space has a size that is a multiple of the size of a segment of global address space. When the hardware indicates a page fault, the address space processor determines whether the address being translated is a local address or a global address. If the address is a local address, the address space processor uses a local directory to process the page fault. If the address is a global address, the address space processor uses a global directory to process the page fault. When the hardware indicates an addressing error because a computed address crosses a global segment boundary, the address space processor determines whether the address is a local address or a global address. If the address is a global address, the address space processor indicates an addressing error. If the address is a local address, the address space processor determines whether the address is within the process' local address space, and indicates an addressing error if the address is outside the process' local address space. Instructions are allowed to operate on both local and global addresses because the address space processor handles either type of address whenever software assistance is required, such as for servicing a page fault or checking a segment boundary crossing. In addition, the address space processor dynamically checks the addressing compatibility of called code before passing control to the called code.

6. 发明授权

US06738889B2 Apparatus and method for providing simultaneous local and global addressing with hardware address translation 有权
标题翻译：用于通过硬件地址转换提供同时本地和全局寻址的装置和方法
公开(公告)号：US06738889B2
公开(公告)日：2004-05-18
申请号：US09352001
申请日：1999-07-12
申请人： Paul LuVerne Godtland , George David Timms, Jr.
发明人： Paul LuVerne Godtland , George David Timms, Jr.
IPC分类号： G06F1200
CPC分类号： G06F12/0284 , G06F12/1036 , G06F12/109
摘要： An apparatus and method provide simultaneous local and global addressing capabilities. A global address space is defined that may be accessed by all processes. In addition, each process has a local address space that is local (and therefore available) only to that process. An address translation mechanism is implemented, preferably in hardware, to compare an address to defined addresses for local and global addressing and to detect when a virtual address computation result would go outside a boundary for the appropriate addressing scheme. The address translation mechanism maps a virtual address to a corresponding physical address, and uses different criteria depending on whether the address is local or global. The address translation mechanism allows an instruction to operate on both local and global addresses by determining at run-time which address space is referenced, and by performing the necessary translation and boundary checking for either global or local address space, whichever is accessed by the instruction. By providing both global and local addressing for the same instructions, the apparatus and method of the present invention provide great flexibility in addressing, allowing a computer program to benefit from the advantages of both addressing modes.
摘要翻译：一种装置和方法提供同时的本地和全局寻址能力。定义全局地址空间，可以由所有进程访问。此外，每个进程都有一个本地地址空间，只有该进程才是本地（因此可用）。实现地址转换机制，优选地在硬件中，以将地址与用于本地和全局寻址的定义的地址进行比较，并且检测何时虚拟地址计算结果将超出用于适当寻址方案的边界。地址转换机制将虚拟地址映射到对应的物理地址，并根据地址是本地还是全局使用不同的标准。地址转换机制允许指令通过在运行时确定哪个地址空间被引用，并且通过对全局或本地地址空间执行必要的转换和边界检查，以指令访问的方式来对本地和全局地址进行操作。通过为相同的指令提供全局和局部寻址，本发明的装置和方法在寻址方面提供了极大的灵活性，允许计算机程序从两种寻址模式的优点中受益。

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