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1. 发明专利

JP2013084850A Semiconductor device and manufacturing method of the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2013084850A
公开(公告)日：2013-05-09
申请号：JP2011225006
申请日：2011-10-12
申请人： Elpida Memory Inc , エルピーダメモリ株式会社 , National Institute Of Advanced Industrial & Technology , 独立行政法人産業技術総合研究所
发明人： KAKEGAWA TOMOYASU , AKINAGA HIROYUKI , SHIMA HISASHI
IPC分类号： H01L27/105 , H01L45/00 , H01L49/00
CPC分类号： H01L45/04 , H01L27/2436 , H01L27/2472 , H01L45/1233 , H01L45/124 , H01L45/146 , H01L45/16
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device which inhibits the reduction of an effective area of a storage element.SOLUTION: A manufacturing method of a semiconductor device includes the steps of: forming a first conductive plug on a substrate; forming a variable resistance film covering an upper surface of the first conductive plug on the substrate; forming a first insulation film covering the upper surface of the first conductive plug on the substrate; partially removing the first insulation film at a position located on the first conductive plug to form a hole part at the first insulation film; forming a first conductive film over an area ranging an upper surface of the first insulation film to the hole part so that the first conductive film buries the hole part thereby contacting with the variable resistance film in the hole part and electrically connecting with the first conductive plug through the variable resistance film.
摘要翻译：解决的问题：提供抑制存储元件的有效面积减小的半导体器件的制造方法。解决方案：半导体器件的制造方法包括以下步骤：在衬底上形成第一导电插塞; 形成覆盖所述基板上的所述第一导电插塞的上表面的可变电阻膜; 形成覆盖所述基板上的所述第一导电插塞的上表面的第一绝缘膜; 在位于所述第一导电插塞上的位置处部分地移除所述第一绝缘膜，以在所述第一绝缘膜处形成孔部; 在第一绝缘膜的上表面到孔部分的区域上形成第一导电膜，使得第一导电膜掩埋孔部分，从而与孔部分中的可变电阻膜接触并与第一导电插塞通过可变电阻膜。版权所有（C）2013，JPO＆INPIT

2. 发明专利

JP2012059827A Semiconductor device, and method of manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2012059827A
公开(公告)日：2012-03-22
申请号：JP2010200004
申请日：2010-09-07
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： KAKEGAWA TOMOYASU , ASANO ISAMU , KAWAGOE TAKESHI , SASAOKA HIROMI , HYUGANO NAOYA , WATANABE YUTA
IPC分类号： H01L27/105 , H01L21/768 , H01L23/522 , H01L27/10 , H01L45/00
CPC分类号： H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/1293 , H01L45/144 , H01L45/1675
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of obtaining a higher heat generation efficiency and reducing a rewriting current by covering the circumference of a phase change recording element with a vacuum air gap part with a low conductivity.SOLUTION: A semiconductor device has: a semiconductor substrate; an element layer including a switching element formed on the semiconductor substrate; a phase change recording element 10 configured by laminating a heater electrode 11 connected to the switching element, a phase change recording material layer 12 that changes a phase by heat from the heater electrode 11, and an upper electrode 13 on the element layer sequentially; an interlayer insulating film 21b laminated on the phase change recording element 10; and a vacuum air gap part 15 provided between the element layer and the interlayer insulating film 21b, and formed in the circumference of any one or both of the heater electrode 11 and the phase change recording material layer 12.
摘要翻译：解决的问题：提供一种能够通过用低导电率的真空气隙部分覆盖相变记录元件的圆周来获得更高的发热效率并减少重写电流的半导体器件。解决方案：半导体器件具有：半导体衬底; 元件层，包括形成在所述半导体衬底上的开关元件; 通过层叠连接到开关元件的加热电极11，相继改变来自加热电极11的热相的相变记录材料层12和元件层上的上电极13而构成的相变记录元件10; 叠层在相变记录元件10上的层间绝缘膜21b; 以及设置在元件层和层间绝缘膜21b之间并且形成在加热电极11和相变记录材料层12中的任一个或两个的圆周中的真空气隙部分15.权利要求：（C ）2012，JPO＆INPIT

3. 发明专利

JP2012142375A Semiconductor storage device and semiconductor storage device manufacturing method 审中-公开
标题翻译：半导体存储器件和半导体存储器件制造方法
公开(公告)号：JP2012142375A
公开(公告)日：2012-07-26
申请号：JP2010293079
申请日：2010-12-28
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： KAKEGAWA TOMOYASU , ASANO ISAMU
IPC分类号： H01L27/105 , H01L45/00
摘要： PROBLEM TO BE SOLVED: To inhibit variation in capacitor characteristics (variation in resistance value) in an edge contact type memory cell using a phase change material as a storage layer, occurring based on variation in distance between a lower electrode and an upper electrode due to variation in film thickness of the storage layer caused by deterioration in coverage.SOLUTION: In the case where a storage element is configured by forming a multilayer film 16 including a lower electrode 13, an inter-electrode insulation film 14 and an upper electrode 15, and embedding a phase change material in a recess 19a exposing a side face of each layer of the multilayer film to form a storage layer 19, a distance between the lower electrode 13 and the upper electrode 15 becomes constant due to a thickness t1 of the inter-electrode insulation film 14. Accordingly, variation in characteristics can be inhibited.
摘要翻译：要解决的问题：为了抑制使用相变材料作为存储层的边缘接触型存储单元中的电容器特性（电阻值的变化）的变化，其基于下电极和上电极之间的距离的变化而发生电极由于覆盖层的劣化而导致的存储层的膜厚变化。解决方案：在存储元件通过形成包括下电极13，电极间绝缘膜14和上电极15的多层膜16以及将相变材料包埋在凹部19a中的情况下进行曝光多层膜的每个层的侧面形成存储层19，下电极13与上电极15之间的距离由于电极间绝缘膜14的厚度t1而变得恒定。因此，特性的变化可以禁止。版权所有（C）2012，JPO＆INPIT

4. 发明专利

JP2012119499A Manufacturing method of semiconductor device and semiconductor device 审中-公开
标题翻译：半导体器件和半导体器件的制造方法
公开(公告)号：JP2012119499A
公开(公告)日：2012-06-21
申请号：JP2010268033
申请日：2010-12-01
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： KAKEGAWA TOMOYASU
IPC分类号： H01L27/105 , H01L45/00 , H01L49/00
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device having a variable resistance film and capable of reducing variations in electric characteristics.SOLUTION: A manufacturing method of a semiconductor device comprises: a step of forming a columnar body including a conductive material and extending along a prescribed direction; and a step of oxidizing a part of the formed columnar body in the prescribed direction and integrally forming a structure in which a variable resistance part composed of an oxide of the conductive material is sandwiched between unoxidized conductive materials when viewed from the prescribed direction.
摘要翻译：要解决的问题：提供具有可变电阻膜并能够减小电特性变化的半导体器件的制造方法。解决方案：半导体器件的制造方法包括：形成包括导电材料并沿预定方向延伸的柱状体的步骤; 以及在规定方向上氧化形成的柱状体的一部分的步骤，并且一体地形成将从导电材料的氧化物构成的可变电阻部分从规定方向观察时夹在未氧化的导电材料之间的结构。版权所有（C）2012，JPO＆INPIT

5. 发明专利

JP2013016718A Semiconductor device and method of manufacturing semiconductor device 审中-公开
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：JP2013016718A
公开(公告)日：2013-01-24
申请号：JP2011149727
申请日：2011-07-06
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： KAKEGAWA TOMOYASU
IPC分类号： H01L27/105 , H01L27/10 , H01L45/00
摘要： PROBLEM TO BE SOLVED: To achieve high integration of a PRAM.SOLUTION: A semiconductor device comprises: a sidewall insulating film covering an inner wall surface of a hole of a first interlayer insulating film; a contact plug embedded in the hole via the sidewall insulating film; a lower electrode arranged so as to be connected with the contact plug in a predetermined region on the first interlayer insulating film; a second interlayer insulating film covering the first interlayer insulating film including the lower electrode; an opening penetrating through the second interlayer insulating film, exposing a part of a side end surface of the lower electrode, and formed to a predetermined depth of the first interlayer insulating film; a phase change material layer arranged in a predetermined region on the second interlayer insulating film including the opening, and connected to the part of the side end surface of the lower electrode at the opening; and an upper electrode arranged on the phase change material layer.
摘要翻译：要解决的问题：实现PRAM的高度集成。解决方案：半导体器件包括：覆盖第一层间绝缘膜的孔的内壁表面的侧壁绝缘膜; 通过所述侧壁绝缘膜嵌入所述孔中的接触插塞; 下电极，其布置成在所述第一层间绝缘膜上的预定区域中与所述接触插塞连接; 覆盖包括所述下电极的所述第一层间绝缘膜的第二层间绝缘膜; 穿过所述第二层间绝缘膜的开口，暴露所述下电极的侧端面的一部分，并形成为所述第一层间绝缘膜的预定深度; 相变材料层，其布置在包括所述开口的所述第二层间绝缘膜上的预定区域中，并且在所述开口处连接到所述下电极的侧端表面的所述部分; 以及布置在所述相变材料层上的上电极。版权所有（C）2013，JPO＆INPIT

6. 发明专利

JP2013012620A Semiconductor device manufacturing method 审中-公开
标题翻译：半导体器件制造方法
公开(公告)号：JP2013012620A
公开(公告)日：2013-01-17
申请号：JP2011145126
申请日：2011-06-30
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： KAKEGAWA TOMOYASU
IPC分类号： H01L21/027
CPC分类号： H01L45/06 , H01L27/2436 , H01L27/2472 , H01L45/141
摘要： PROBLEM TO BE SOLVED: To inhibit collapse of a mask having a high aspect ratio even when a fine pattern is formed.SOLUTION: A semiconductor device manufacturing method comprises: a processing object formation process of forming a processing object; a first mask formation process of forming a first mask and a first support medium supporting one lateral face side of the first mask; a first processing process of processing the processing object using the first mask and the first support medium as a mask; a second support medium formation process of forming a second support medium supporting the processing object and another lateral face side of the first mask; a first support medium removal process of removing the first support medium; and a second processing process of processing the processing object using the first mask and the second support medium as a mask.
摘要翻译：要解决的问题：即使形成精细图案，也能抑制具有高纵横比的掩模的塌陷。解决方案：一种半导体器件制造方法，包括：形成处理对象的处理对象形成处理; 形成第一掩模的第一掩模形成工艺和支撑所述第一掩模的一个侧面侧的第一支撑介质; 使用第一掩模和第一支撑介质作为掩模来处理处理对象的第一处理过程; 第二支撑介质形成工艺，其形成支撑处理对象的第二支撑介质和第一掩模的另一侧面; 去除第一支撑介质的第一支撑介质移除过程; 以及使用第一掩模和第二支撑介质作为掩模来处理处理对象的第二处理过程。版权所有（C）2013，JPO＆INPIT

7. 发明专利

JP2012222114A Semiconductor device and manufacturing method of the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2012222114A
公开(公告)日：2012-11-12
申请号：JP2011085635
申请日：2011-04-07
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： KAKEGAWA TOMOYASU
IPC分类号： H01L27/105 , H01L45/00 , H01L49/00
CPC分类号： H01L45/04 , H01L27/2436 , H01L45/124 , H01L45/145 , H01L45/1633
摘要： PROBLEM TO BE SOLVED: To solve the problem of variation in a memory element characteristic in a semiconductor device having a conventional ReRAM.SOLUTION: A semiconductor device manufacturing method comprises: a step of forming a first insulation film 23 covering a substrate 11; a step of forming a conductive plug 24 penetrating the first insulation film 23; a step of partially removing an upper part of the conductive plug 24 to form a hole part including a bottom face formed from a top face of the conductive plug 24 and a lateral face formed from the first insulation film 23 at a part covered with the partially removed conductive plug 24; a step of forming a lateral wall insulation film 25 that covers the lateral wall of the hole part and exposes a part of the bottom face of the hole part; a step of forming a variable resistance film 26 covering the lateral wall insulation film 25 and the bottom face of the hole part; and a step of forming a conductive film 27 covering the variable resistance film 26.
摘要翻译：要解决的问题：为了解决具有常规ReRAM的半导体器件中的存储元件特性的变化的问题。解决方案：半导体器件制造方法包括：形成覆盖衬底11的第一绝缘膜23的步骤; 形成穿过第一绝缘膜23的导电插塞24的步骤; 部分地去除导电插塞24的上部以形成包括由导电插塞24的顶面形成的底面的孔部和由第一绝缘膜23形成的部分覆盖部分的部分的部分去除的导电插塞24; 形成覆盖孔部的侧壁并露出孔部的底面的一部分的侧壁绝缘膜25的工序。形成覆盖侧壁绝缘膜25和孔部的底面的可变电阻膜26的工序; 以及形成覆盖可变电阻膜26的导电膜27的步骤。版权所有（C）2013，JPO＆INPIT

8. 发明专利

JP2011091156A Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2011091156A
公开(公告)日：2011-05-06
申请号：JP2009242529
申请日：2009-10-21
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： KAKEGAWA TOMOYASU
IPC分类号： H01L27/105 , H01L45/00
CPC分类号： H01L45/148 , G11C13/0004 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/141 , H01L45/143 , H01L45/144 , H01L45/1683
摘要： PROBLEM TO BE SOLVED: To obtain a semiconductor device including a phase-change memory reducing an operating current without deteriorating the efficiency of heating a phase-change material, and to provide a method of manufacturing the semiconductor device.
SOLUTION: The semiconductor device includes: a semiconductor substrate 1; first interlayer dielectrics 30; a heater electrode 32 embedded into the first interlayer dielectrics 30; second interlayer dielectrics 40 laminated on the first interlayer dielectrics 30 while forming a hole 42 exposing the top face 32a of the heater electrode 32; a phase-change material film 70 being filled into the hole 42 while coating the second interlayer dielectrics 40; and an upper electrode 80 coating the phase-change material film 70. The semiconductor device further includes: a conductive film 52 brought into contact with the top face 32a of the heater electrode 32 in the hole 42 and formed among the second interlayer dielectrics 40 and the phase-change material film 70; and an insulating film 62 brought into contact with the top face 52a of the conductive film 52 in the hole 42 and formed among the second interlayer dielectrics 40 and the phase-change material film 70. Such semiconductor device and method of manufacturing the semiconductor device are provided.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：为了获得包括减少工作电流的相变存储器而不降低相变材料的加热效率的半导体器件，并且提供制造半导体器件的方法。解决方案：半导体器件包括：半导体衬底1; 第一层间电介质30; 嵌入到第一层间电介质30中的加热电极32; 第二层间电介质40层压在第一层间电介质30上，同时形成露出加热器电极32的顶面32a的孔42; 相位改变材料膜70被填充到孔42中同时涂覆第二层间电介质40; 以及涂覆相变材料膜70的上部电极80.半导体器件还包括：导电膜52，其与孔42中的加热器电极32的顶面32a接触并形成在第二层间电介质40和相变材料膜70; 以及在孔42中与导电膜52的顶面52a接触并形成在第二层间电介质40和相变材料膜70之间的绝缘膜62.这种半导体器件及其制造方法是提供。版权所有（C）2011，JPO＆INPIT

9. 发明专利

JP2013008718A Phase change element and manufacturing method therefor 审中-公开
标题翻译：相变元件及其制造方法
公开(公告)号：JP2013008718A
公开(公告)日：2013-01-10
申请号：JP2011138483
申请日：2011-06-22
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： KAKEGAWA TOMOYASU
IPC分类号： H01L27/105 , H01L45/00
摘要： PROBLEM TO BE SOLVED: To provide a phase change element in which increase and variation of contact resistance on the boundary surface of phase change recording material film/upper electrode layer can be minimized.SOLUTION: In the phase change element including a conductive plug (13), a phase change recording material film (20) and an upper electrode layer (15), the conductive plug (13) and the phase change recording material film (20) are connected in the longitudinal direction, and the phase change recording material film (20) and the upper electrode layer (15) are connected at least partially on the side surface of the phase change recording material film (20).

10. 发明专利

JP2011243727A Semiconductor device and manufacturing method therefor 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2011243727A
公开(公告)日：2011-12-01
申请号：JP2010114263
申请日：2010-05-18
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： KAKEGAWA TOMOYASU
IPC分类号： H01L27/105 , H01L21/338 , H01L29/778 , H01L29/812 , H01L45/00
摘要： PROBLEM TO BE SOLVED: To reduce a voltage drop loss and efficiently apply heat to a phase change material by directly connecting a phase change material area to a second source/drain electrode of a MOS transistor without going through a contact plug, enabling a reduction in power consumption.SOLUTION: A semiconductor device comprises: a MOS transistor having a first source/drain electrode and a second source/drain electrode; a GND wire connected to the first source/drain electrode through a contact plug; a phase change material area; and an upper electrode on the phase change material area. The phase change material area is directly connected to the second source/drain electrode.
摘要翻译：要解决的问题：为了降低电压降损失并且通过将相变材料区域直接连接到MOS晶体管的第二源极/漏极而不通过接触插塞来有效地向相变材料施加热量，使得能够降低功耗。解决方案：半导体器件包括：具有第一源极/漏极电极和第二源极/漏极电极的MOS晶体管; GND线，通过接触插头连接到第一源/漏电极; 相变材料区域; 和相变材料区域上的上电极。相变材料区域直接连接到第二源/漏电极。版权所有（C）2012，JPO＆INPIT

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