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1. 发明授权

US09705315B2 Protection circuit for preventing an over-current from an output stage 有权
公开(公告)号：US09705315B2
公开(公告)日：2017-07-11
申请号：US14685611
申请日：2015-04-14
申请人： Elite Semiconductor Memory Technology Inc.
发明人： Szu-Chun Tsao
IPC分类号： H02H9/00 , H02H9/02 , H03K17/082
CPC分类号： H02H9/025 , H03K17/0822
摘要： A semiconductor device including: an output stage, including a PMOS, an NMOS and an output terminal, wherein a source terminal of the PMOS is connected to a first supply voltage, a drain terminal of the PMOS is connected to a drain terminal of the NMOS and the output terminal, a source terminal of the NMOS is connected to a second supply voltage, and the output terminal outputs an output signal; and a protection circuit, including a first voltage clamping circuit, including a first transistor, a second transistor and a first switch, wherein the first transistor and the second transistor are for clamping a gate voltage of the PMOS of the output stage and are connected in series, the first switch is coupled to the first supply voltage and a node between the first transistor and the second transistor for selectively coupling the first supply voltage to the node.

2. 发明授权

US10404227B1 Quaternary/ternary modulation selecting circuit and associated method 有权
公开(公告)号：US10404227B1
公开(公告)日：2019-09-03
申请号：US15922908
申请日：2018-03-15
申请人： Elite Semiconductor Memory Technology Inc.
发明人： Szu-Chun Tsao , Deng-Yao Shih
IPC分类号： H03F3/217 , H03F1/02 , H03F1/32 , H03F3/187 , H03K21/02 , H03K19/20 , H03K5/24
摘要： A quaternary/ternary modulation selecting circuit of an amplifier includes: a signal generating circuit, a detecting circuit, and a selecting circuit. The signal generating circuit is arranged to generate a ternary signal and a quaternary signal. The detecting circuit coupled to the signal generating circuit is arranged to generate a mode selecting signal according to at least the ternary signal. The selecting circuit coupled to the signal generating circuit and the detecting circuit is arranged to select and output one of the ternary signal and the quaternary signal to an output stage of the amplifier according to the mode selecting signal.

3. 发明授权

US10958259B2 Pulse width modulation output stage with dead time control 有权
公开(公告)号：US10958259B2
公开(公告)日：2021-03-23
申请号：US16837634
申请日：2020-04-01
申请人： ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
发明人： Szu-Chun Tsao , Yang-Jing Huang , Ya-Mien Hsu
IPC分类号： H03K7/08
摘要： A pulse width modulation output stage incorporates a half bridge output stage, a gate control circuit, a detection circuit, and a control logic. The half bridge output stage has a first transistor and a second transistor connected in series between a power supply node and a ground node. The gate control circuit outputs a pulse width modulation signal to drive the first transistor and the second transistor. The detection circuit detects whether or not a glitch occurs in one of the gate voltages of the first and second transistor so as to generate a control code. The logic circuit varies the delay time of the pulse width modulation signal based on the control code.

4. 发明申请

US20190288652A1 QUATERNARY/TERNARY MODULATION SELECTING CIRCUIT AND ASSOCIATED METHOD 有权
公开(公告)号：US20190288652A1
公开(公告)日：2019-09-19
申请号：US15922908
申请日：2018-03-15
申请人： Elite Semiconductor Memory Technology Inc.
发明人： Szu-Chun Tsao , Deng-Yao Shih
IPC分类号： H03F3/217 , H03F3/187 , H03F1/32 , H03F1/02
摘要： A quaternary/ternary modulation selecting circuit of an amplifier includes: a signal generating circuit, a detecting circuit, and a selecting circuit. The signal generating circuit is arranged to generate a ternary signal and a quaternary signal. The detecting circuit coupled to the signal generating circuit is arranged to generate a mode selecting signal according to at least the ternary signal. The selecting circuit coupled to the signal generating circuit and the detecting circuit is arranged to select and output one of the ternary signal and the quaternary signal to an output stage of the amplifier according to the mode selecting signal.

5. 发明授权

US09977459B1 Clock generating circuit and associated method 有权
公开(公告)号：US09977459B1
公开(公告)日：2018-05-22
申请号：US15484149
申请日：2017-04-11
申请人： Elite Semiconductor Memory Technology Inc.
发明人： Chin-Tung Chan , Szu-Chun Tsao , Deng-Yao Shih
IPC分类号： G06F1/08 , G04F5/00
CPC分类号： G06F1/08 , G04F5/00
摘要： A clock generating circuit includes: a generating circuit, a reference circuit and an adjusting circuit. The generating circuit generates a clock signal. The reference circuit is coupled to the generating circuit, and generates a reference signal to the generating circuit according to the clock signal, wherein a frequency of the clock signal is varied according to the reference signal when the reference signal is received by the generating circuit. The adjusting circuit generates an adjusting signal and a trigger signal to the generating circuit, wherein the generating circuit refers to the trigger signal to decide whether to adjust the clock signal frequency according to the adjusting signal.

6. 发明申请

US20160308352A1 PROTECTION CIRCUIT FOR PREVENTING AN OVER-CURRENT FROM AN OUTPUT STAGE 有权
标题翻译：用于防止从输出阶段过流的保护电路
公开(公告)号：US20160308352A1
公开(公告)日：2016-10-20
申请号：US14685611
申请日：2015-04-14
申请人： Elite Semiconductor Memory Technology Inc.
发明人： Szu-Chun Tsao
IPC分类号： H02H9/02
CPC分类号： H02H9/025 , H03K17/0822
摘要： A semiconductor device including: an output stage, including a PMOS, an NMOS and an output terminal, wherein a source terminal of the PMOS is connected to a first supply voltage, a drain terminal of the PMOS is connected to a drain terminal of the NMOS and the output terminal, a source terminal of the NMOS is connected to a second supply voltage, and the output terminal outputs an output signal; and a protection circuit, including a first voltage clamping circuit, including a first transistor, a second transistor and a first switch, wherein the first transistor and the second transistor are for clamping a gate voltage of the PMOS of the output stage and are connected in series, the first switch is coupled to the first supply voltage and a node between the first transistor and the second transistor for selectively coupling the first supply voltage to the node.
摘要翻译：一种半导体器件，包括：输出级，包括PMOS，NMOS和输出端，其中PMOS的源极端子连接到第一电源电压，PMOS的漏极端子连接到NMOS的漏极端子和所述输出端子，所述NMOS的源极端子连接到第二电源电压，并且所述输出端子输出输出信号; 以及包括第一电压钳位电路的保护电路，包括第一晶体管，第二晶体管和第一开关，其中第一晶体管和第二晶体管用于钳位输出级的PMOS的栅极电压，第一开关耦合到第一电源电压和第一晶体管和第二晶体管之间的节点，用于选择性地将第一电源电压耦合到节点。

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