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1. 发明专利

JP2008048305A Class-d acoustic amplifier with half-swing pulse-width-modulation 审中-公开
标题翻译：具有半波形脉冲宽度调制的CLASS-D声学放大器
公开(公告)号：JP2008048305A
公开(公告)日：2008-02-28
申请号：JP2006223831
申请日：2006-08-21
申请人： Elite Semiconductor Memory Technology Inc , 晶豪科技股▲ふん▼有限公司
发明人： YANG CHENG-CHUNG
IPC分类号： H03F3/217
摘要： PROBLEM TO BE SOLVED: To allow a class-D amplifier to be used in portable equipment by decreasing system and solution costs by obviating an output filter required by a conventional class-D amplifier.
SOLUTION: The amplifier includes a first comparator 116a, a second comparator 116b, and an output switch 120a, 120b. The first and second comparators respectively compare a pair of differential signals with a half-swing modulation signal to generate first and second pulse-width modulation (PWM) control signals, wherein a voltage swing of the half-swing modulation signal is smaller than the voltage swing of the differential signals. The output switch includes a pair of inputs coupled to receive the PWM control signals to provide a ternary encoded output signal in response to the PWM control signals.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了通过消除常规D类放大器所需的输出滤波器来降低系统和解决方案成本，允许D类放大器用于便携式设备。解决方案：放大器包括第一比较器116a，第二比较器116b和输出开关120a，120b。第一和第二比较器分别将一对差分信号与半摆幅调制信号进行比较，以产生第一和第二脉冲宽度调制（PWM）控制信号，其中半摆幅调制信号的电压摆幅小于电压摆动差动信号。输出开关包括耦合以接收PWM控制信号的一对输入，以响应于PWM控制信号提供三进制编码的输出信号。版权所有（C）2008，JPO＆INPIT

2. 发明授权

US11209850B2 Termination voltage regulation apparatus with transient response enhancement 有权
公开(公告)号：US11209850B2
公开(公告)日：2021-12-28
申请号：US16790920
申请日：2020-02-14
申请人： ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
发明人： Yao-Wei Yang
IPC分类号： G05F1/575 , G05F1/59 , H02M3/156
摘要： A termination voltage regulation apparatus with transient response enhancement includes a termination voltage regulator and a transient response enhancer. The termination voltage regulator provides a termination voltage at a termination voltage terminal, including first and second switching units. The transient response enhancer, coupled to the termination voltage regulator, is utilized for enhancing transient response of the termination voltage regulator, including a first enhancement circuit for sensing a first signal associated with the first switching unit and enabling a first control terminal of the first switching unit to be at a first voltage in response to the first signal in a sinking mode; and a second enhancement circuit for sensing a second signal associated with the second switching unit and enabling a second control terminal of the second switching unit to be at a second voltage in response to the second signal in a sourcing mode.

3. 发明授权

US10958259B2 Pulse width modulation output stage with dead time control 有权
公开(公告)号：US10958259B2
公开(公告)日：2021-03-23
申请号：US16837634
申请日：2020-04-01
申请人： ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
发明人： Szu-Chun Tsao , Yang-Jing Huang , Ya-Mien Hsu
IPC分类号： H03K7/08
摘要： A pulse width modulation output stage incorporates a half bridge output stage, a gate control circuit, a detection circuit, and a control logic. The half bridge output stage has a first transistor and a second transistor connected in series between a power supply node and a ground node. The gate control circuit outputs a pulse width modulation signal to drive the first transistor and the second transistor. The detection circuit detects whether or not a glitch occurs in one of the gate voltages of the first and second transistor so as to generate a control code. The logic circuit varies the delay time of the pulse width modulation signal based on the control code.

4. 发明申请

US20210049095A1 MEMORY CHIP, MEMORY MODULE AND METHOD FOR PSEUDO-ACCESSING MEMORY BANK THEREOF 有权
公开(公告)号：US20210049095A1
公开(公告)日：2021-02-18
申请号：US16539041
申请日：2019-08-13
申请人： ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
发明人： PEI-JEY HUANG , TSE-HUA YAO
IPC分类号： G06F12/06 , G06F12/10
摘要： The present application proposes a memory chip includes a plurality of memory banks, a plurality of address pins, and a pseudo-address determining circuit. The plurality of address pins is arranged for receiving a plurality of address signals corresponding to the plurality of memory banks, respectively. The pseudo-address determining circuit has a plurality of input terminals coupled to the plurality of address pins, respectively, and a plurality of output terminals coupled to the plurality of memory banks. The pseudo-address determining circuit generates a pseudo-address table for the plurality of memory banks when the memory chip is powered-up. The pseudo-address table has a plurality of pseudo-addresses corresponding to the plurality of memory banks, respectively. The present application also provides a memory module that incorporates the memory chip and a method for pseudo-accessing memory banks of the memory chip.

5. 发明授权

US10916293B1 Target row refresh mechanism capable of effectively determining target row address to effectively mitigate row hammer errors without using counter circuit 有权
公开(公告)号：US10916293B1
公开(公告)日：2021-02-09
申请号：US16747553
申请日：2020-01-21
申请人： Elite Semiconductor Memory Technology Inc.
发明人： Ya-Chun Lai , Po-Hsun Wu , Jen-Shou Hsu
IPC分类号： G11C11/40 , G11C11/406 , G11C7/06 , G06F12/02 , G11C11/409
摘要： A target row refresh method includes: providing first table having M entries each capable of storing information of target row address; providing second table having K entries respectively capable of storing information of different/identical candidate row addresses; determining whether an input address in an input address register matches address information recorded in the first table; when not match, determining whether to update information of a target row latch by using the input address in the input address register according to a sample policy so as to determine whether to compare the input address with address information recorded in the second table to determine a target row address; and performing a target row refresh operation to refresh a memory device's row(s) adjacent to a target row corresponding to the target row address.

6. 发明申请

US20200294570A1 SEMICONDUCTOR MEMORY DEVICE AND WORD-LINE ACTIVATION METHOD 审中-公开
公开(公告)号：US20200294570A1
公开(公告)日：2020-09-17
申请号：US16354138
申请日：2019-03-14
申请人： ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
发明人： Yi Heng LIU , Jian-Sing LIOU
IPC分类号： G11C11/408 , G11C11/4091
摘要： A semiconductor memory device includes a memory bank of an open bit-line architecture and a word-line decoder. The memory bank is divided into a plurality of memory blocks in a bit-line direction, and each of the memory blocks includes a plurality of word lines, a plurality of bit lines and a plurality of memory cells which are grouped into a plurality of memory sections including two edge memory sections and at least one non-edge memory section. The word-line decoder generates a plurality of word-line enabling signals based on a plurality of address signals and activates one of the word lines for each of the two edge memory sections of one of the memory blocks and one of the word lines for one of the at least one non-edge memory section of each of the other memory blocks concurrently in an active mode according to the word-line enabling signals.

7. 发明授权

US10771017B2 Amplifier circuit with low malfunction rate 有权
公开(公告)号：US10771017B2
公开(公告)日：2020-09-08
申请号：US16242011
申请日：2019-01-08
申请人： Elite Semiconductor Memory Technology Inc.
发明人： Shao-Ming Sun
IPC分类号： H03F1/26 , H03F3/217 , H03F3/45
摘要： An amplifier circuit with novel design is provided. The amplifier circuit includes an input stage, a resistor, an output stage, an intermediate stage and a gm circuit. The input stage is coupled to a first supply voltage, and is arranged to receive an input voltage and a feedback current. The resistor is coupled between the input voltage and the input stage. The output stage is coupled to a second supply voltage, and is arranged to provide an output voltage for driving a load. The intermediate stage is coupled between the input stage and the output stage, and includes a level shifter. The gm circuit is coupled to the input stage, and is arranged to compare the input voltage with a common mode voltage, and thereby generates a compensate current for the input stage.

8. 发明授权

US10587196B1 Constant on-time controller and buck regulator device using the same 有权
公开(公告)号：US10587196B1
公开(公告)日：2020-03-10
申请号：US16282352
申请日：2019-02-22
申请人： ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
发明人： I-Hsiu Ho
IPC分类号： H02M3/158 , H02M1/08 , H02M3/157 , H02M1/00
摘要： A constant on-time controller has a voltage divider, a current ripple extractor, a one-shot on-timer, a comparator and a flip flop. The voltage divider generates a feedback voltage according to a regulator output voltage. The current ripple extractor senses a current in an energy storage inductor of a buck regulator flowing through flowing through an output capacitor's ESR, and generates an extracted ripple current having no DC component accordingly. The one-shot on-timer outputs a constant-on time control signal according to a buck regulator input voltage and the regulator output voltage. The modulation circuit outputs a modulation signal according to a reference voltage signal, the feedback voltage and the extracted ripple current. The flip flop generates a control signal to the buck regulator according to the modulation signal and the constant-on time control signal. An off-time of the buck regulator is determined according to the modulation signal.

9. 发明申请

US20190259461A1 ERASING METHOD USED IN FLASH MEMORY 审中-公开
公开(公告)号：US20190259461A1
公开(公告)日：2019-08-22
申请号：US15902325
申请日：2018-02-22
申请人： ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
发明人： Chih-Hao CHEN
IPC分类号： G11C16/34 , G11C16/14 , G11C11/56
摘要： An erasing method used in a flash memory comprising at least one memory block divided into a plurality of memory sectors is illustrated. Whether the memory block or the memory sector corresponding to an address has at least one under-erased transistor memory cell according to a sector enable signal is verified, wherein the sector enable signal is determined according to whether the memory block has at least one over-erased transistor memory cell. The transistor memory cells of the memory block or the memory sector will be erased according to the sector enable signal if the memory block or the memory sector corresponding to the address that has the under-erased transistor memory cell.

10. 发明申请

US20190258537A1 TESTING APPARATUS AND FOLDED PROBE CARD TESTING SYSTEM 审中-公开
公开(公告)号：US20190258537A1
公开(公告)日：2019-08-22
申请号：US15902688
申请日：2018-02-22
申请人： ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
发明人： Min-Chung Chou
IPC分类号： G06F11/07 , G01R1/073 , G01R1/067 , G01R31/28
摘要： A testing apparatus has first and second IOs, first and second comparators, a data combining module, and first and second data output circuits. The first and second comparators respectively receive first and second test data. The data combining module electrically connected to the first and second comparators receive compared first and second test data of the first and second comparators, and further receive a command code. The first and second data output circuits are respectively connected to the first and second IOs, and are further electrically connected to the data combining module. According to the command code, the data combining module outputs the compared first and second test data respectively to the first and second IOs through the first and second data output circuits, or respectively to the second and first IOs through the second and first data output circuits.

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