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1. 发明授权

US4894696A Dynamic random access memory having a trench capacitor 失效
标题翻译：具有沟槽电容器的动态随机存取存储器
公开(公告)号：US4894696A
公开(公告)日：1990-01-16
申请号：US938967
申请日：1986-12-08
申请人： Eiji Takeda , Kiyoo Itoh , Ryoichi Hori , Katsuhiro Shimohigashi , Katsutaka Kimura
发明人： Eiji Takeda , Kiyoo Itoh , Ryoichi Hori , Katsuhiro Shimohigashi , Katsutaka Kimura
IPC分类号： H01L27/10 , G11C11/34 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10861 , Y10S257/90
摘要： A very highly integrated semiconductor memory which enables the dynamic random access memory to develop less soft error and to eliminate margin for aligning the masks, that hinders the device from being highly integrated. The memory cell capacitor is constituted by a trench which is provided at a position defined by an insulator formed on the side of gate electrode of a MOS transistor that constitutes the memory cell. Therefore, the MOS transistor and the trench capacitor are self-aligned, and no margin is required for alignment.
摘要翻译：一种非常高度集成的半导体存储器，其使得动态随机存取存储器能够开发更少的软错误并消除对准掩模的余量，这妨碍了器件的高度集成。存储单元电容器由设置在由形成在构成存储单元的MOS晶体管的栅极侧的绝缘体限定的位置处的沟槽构成。因此，MOS晶体管和沟槽电容器是自对准的，并且不需要用于对准的余量。

2. 发明授权

US4930112A Semiconductor device having a voltage limiter 失效
标题翻译：具有限压器的半导体器件
公开(公告)号：US4930112A
公开(公告)日：1990-05-29
申请号：US934546
申请日：1986-11-24
申请人： Hitoshi Tanaka , Ryoichi Hori , Kiyoo Itoh , Katsutaka Kimura , Katsuhiro Shimohigashi
发明人： Hitoshi Tanaka , Ryoichi Hori , Kiyoo Itoh , Katsutaka Kimura , Katsuhiro Shimohigashi
IPC分类号： G11C11/407 , G05F1/46 , G11C11/401 , G11C11/4074 , G11C11/409
CPC分类号： G05F1/465 , G11C11/4074
摘要： A semiconductor device comprising a plurality of circuits driven by at least one external power source, and at least one voltage converter transforming the voltage of the external power source into another voltage. At least a part of the plurality of circuits are driven by the output voltage of the at least one voltage converter, which is provided with a controller for controlling its load driving power, corresponding to the operation of the part of the plurality of circuits. The voltage converter includes a voltage limiter which is used exclusively for each of the different natures of the loads, and its operation and load driving power are controlled, depending on the operations of each of the loads.
摘要翻译：一种半导体器件，包括由至少一个外部电源驱动的多个电路和至少一个将外部电源的电压转换成另一电压的电压转换器。所述多个电路的至少一部分由所述至少一个电压转换器的输出电压驱动，所述至少一个电压转换器的输出电压与所述多个电路的所述部分的操作相对应地设置有用于控制其负载驱动功率的控制器。电压转换器包括专用于负载的不同性质的电压限制器，并且根据每个负载的操作来控制其操作和负载驱动功率。

3. 发明授权

US4796234A Semiconductor memory having selectively activated blocks including CMOS sense amplifiers 失效
标题翻译：半导体存储器具有选择性地激活的块，包括CMOS读出放大器
公开(公告)号：US4796234A
公开(公告)日：1989-01-03
申请号：US927144
申请日：1986-11-05
申请人： Kiyoo Itoh , Yoshiki Kawajiri , Katsutaka Kimura , Ryoichi Hori , Jun Etoh
发明人： Kiyoo Itoh , Yoshiki Kawajiri , Katsutaka Kimura , Ryoichi Hori , Jun Etoh
IPC分类号： G11C11/409 , G11C7/06 , G11C8/12 , G11C8/14 , G11C11/401 , G11C11/4091 , G11C7/00
CPC分类号： G11C8/14 , G11C11/4091 , G11C7/06 , G11C8/12
摘要： It is contemplated to realize a semiconductor memory with a large memory capacity, high in integration and low in power dissipation. A semiconductor memory is disclosed, comprising a plurality of blocks each having a memory cell array and sense amplifier(s) to differentially amplify signals read out from the array, wherein a common driving line of amplifiers composed of N-channel MOS transistors among said sense amplifiers and a common driving line of amplifiers composed of P-channel MOS transistors among the sense amplifers are connected between different blocks.
摘要翻译：可以想到实现具有大存储容量，高集成度和低功耗的半导体存储器。公开了一种半导体存储器，包括多个块，每个块具有存储单元阵列和读出放大器，用于差分放大从阵列读出的信号，其中由所述感测中的N沟道MOS晶体管组成的公共驱动线放大器和由感测放大器中的P沟道MOS晶体管组成的放大器的公共驱动线连接在不同的块之间。

4. 发明授权

US5550781A Semiconductor apparatus with two activating modes of different number of selected word lines at refreshing 失效
标题翻译：具有不同数量的所选字线的两种激活模式的半导体装置在刷新时
公开(公告)号：US5550781A
公开(公告)日：1996-08-27
申请号：US381648
申请日：1995-01-31
申请人： Ken Sugawara , Shigeru Sakairi , Mikio Matoba , Toshio Sasaki , Katsuhiro Shimohigashi , Katsutaka Kimura
发明人： Ken Sugawara , Shigeru Sakairi , Mikio Matoba , Toshio Sasaki , Katsuhiro Shimohigashi , Katsutaka Kimura
IPC分类号： G11C5/14 , G11C8/18 , G11C11/406 , G11C11/4074 , G11C11/40
CPC分类号： G11C8/18 , G11C11/406 , G11C11/4074 , G11C5/141 , G11C5/143 , G11C5/147
摘要： A memory cartridge having a plurality of dynamic memory units includes an access conversion circuit which converts a static access signal into its inverted signal and an access control circuit which controllably switches between a signal for refreshing each dynamic unit and a signal for external access. The memory cartridge also includes a power switching circuit which switches power from an internal power supply to an external power supply when the memory cartridge is mounted to an external device.
摘要翻译：具有多个动态存储单元的存储器盒包括将静态访问信号转换为其反相信号的访问转换电路和可控地在用于刷新每个动态单元的信号和用于外部访问的信号之间切换的访问控制电路。存储盒还包括一个电源切换电路，当存储盒被安装到外部设备时，电源切换电路将电源从内部电源切换到外部电源。

5. 发明授权

US4992985A Method for selectively initiating/terminating a test mode in an address multiplexed DRAM and address multiplexed DRAM having such a capability 失效
标题翻译：用于在地址多路复用DRAM中选择性地启动/终止测试模式的方法，以及具有这种能力的地址多路复用DRAM
公开(公告)号：US4992985A
公开(公告)日：1991-02-12
申请号：US319693
申请日：1989-03-07
申请人： Kazuyuki Miyazawa , Katsuhiro Shimohigashi , Jun Etoh , Katsutaka Kimura
发明人： Kazuyuki Miyazawa , Katsuhiro Shimohigashi , Jun Etoh , Katsutaka Kimura
IPC分类号： G11C11/401 , G01R31/317 , G11C29/00 , G11C29/14 , G11C29/46
CPC分类号： G11C29/46 , G01R31/31701
摘要： An address multiplexed dynamic RAM device is provided which is capable of initiating (setting) and terminating (resetting) the test mode in response to the signal level combinations of the row address and column address strobe signals with the write enable signal, which signal level combinations correspond to those which are otherwise left unused in the normal operating mode thereby obviating the requirement of an additional external control signal terminal. Such initiating of the test mode can be effected by setting the RAS signal of the DRAM at a logic "low" level when the CAS signal and the WE signal are at a logic "low" level. Clearing or resetting thereof is effected by the same combination sequence, except that the WE signal is at a logic "high" level. The setting or initiating of a test mode is also implemented by the additional combination of one of the row address signal bits, e.g. the most significant bit.

6. 发明授权

US5467314A Method of testing an address multiplexed dynamic RAM 失效
标题翻译：测试地址多路复用动态RAM的方法
公开(公告)号：US5467314A
公开(公告)日：1995-11-14
申请号：US277430
申请日：1994-07-18
申请人： Kazuyuki Miyazawa , Katsuhiro Shimohigashi , Jun Etoh , Katsutaka Kimura
发明人： Kazuyuki Miyazawa , Katsuhiro Shimohigashi , Jun Etoh , Katsutaka Kimura
IPC分类号： G11C11/401 , G01R31/317 , G11C29/00 , G11C29/14 , G11C29/46 , G11C7/00
CPC分类号： G11C29/46 , G01R31/31701
摘要： In an address multiplexed dynamic random access memory (RAM) which has both a normal operation mode and a test mode capability, the test mode is initiated in response to particular signal level combinations of both the row address strobe (RAS) and column address strobe (CAS) signals and the write enable (WE) signal. Since the signal level combinations employed in connection with implementing the test mode are unused in the normal operating mode of the dynamic RAM, additional external terminals are unneeded. This dynamic RAM employs multiplexing circuitry on both the input side as well as on the output side of the dynamic RAM, which multiplexing circuitry is controlled during normal operation by select signals from a decoder and during the test mode by a test signal which allows accessing of data at all of the common complementary data lines by the testing circuitry so as to determine whether there is consistency or inconsistency of the data being read out for testing.
摘要翻译：在具有正常操作模式和测试模式能力的地址多路复用动态随机存取存储器（RAM）中，测试模式是响应于行地址选通（＆amp; Upbar＆R）和列地址选通（＆upbar＆C）信号和写使能（＆upbar＆W）信号。由于在动态RAM的正常操作模式中不使用与实现测试模式相关的信号电平组合，因此不需要额外的外部终端。该动态RAM在动态RAM的输入侧和输出侧都采用多路复用电路，该复用电路在正常操作期间通过来自解码器的选择信号以及在测试模式期间通过允许访问的测试信号通过测试电路在所有公共补充数据线上的数据，以便确定正在读出的用于测试的数据是否一致或不一致。

7. 发明授权

US5117393A Method of testing memory cells in an address multiplexed dynamic RAM including test mode selection 失效
标题翻译：包含测试模式选择的地址多重动态RAM中的存储单元测试方法
公开(公告)号：US5117393A
公开(公告)日：1992-05-26
申请号：US648885
申请日：1991-01-31
申请人： Kazuyuki Miyazawa , Katsuhiro Shimohigashi , Jun Etoh , Katsutaka Kimura
发明人： Kazuyuki Miyazawa , Katsuhiro Shimohigashi , Jun Etoh , Katsutaka Kimura
IPC分类号： G11C11/401 , G01R31/317 , G11C29/00 , G11C29/14 , G11C29/46
CPC分类号： G11C29/46 , G01R31/31701
摘要： An address multiplexed dynamic RAM device is provided which is capable of initiating (setting) and terminating (resetting) the test mode in response to the signal level combinations of the row address and column address strobe signals and the write enable signal. The signal level combinations employed correspond to those which are unused in the normal operating mode thereby obviating the need for providing additional external control signal terminals. In addition to writing predetermined data in selected memory cells during the test mode, verficiation of the predetermined data is also implemented during the read phase of the test mode.

8. 发明授权

US4873672A Dynamic random access memory capable of fast erasing of storage data 失效
标题翻译：能够快速擦除存储数据的动态随机存取存储器
公开(公告)号：US4873672A
公开(公告)日：1989-10-10
申请号：US51715
申请日：1987-05-20
申请人： Jun Etoh , Katsuhiro Shimohigashi , Kazuyuki Miyazawa , Katsutaka Kimura , Takesada Akiba
发明人： Jun Etoh , Katsuhiro Shimohigashi , Kazuyuki Miyazawa , Katsutaka Kimura , Takesada Akiba
IPC分类号： G11C11/401 , G11C11/4072 , G11C11/4078 , G11C11/409
CPC分类号： G11C11/4078 , G11C11/4072
摘要： This invention relates to a semiconductor memory having a high speed operation and a high integration density. When a high integration semiconductor memory is applied to a large scale computer system, storage data must be erased at a high speed for data security. The present invention erases the storage data by a method which is different from the write method of conventional prior art. In the invention, the erasing operation is made by continuously selecting word lines while sense amplifiers are kept in this on-state. The present invention includes a control circuit for attaining such an operation, and can be used for a semiconductor memory implemented in a computer system accessed by a plurality of users.
摘要翻译：本发明涉及具有高速运算和高集成密度的半导体存储器。当将高集成半导体存储器应用于大规模计算机系统时，为了数据安全，必须高速擦除存储数据。本发明通过与传统现有技术的写入方法不同的方法擦除存储数据。在本发明中，通过在感测放大器保持在该接通状态的同时连续选择字线来进行擦除操作。本发明包括用于实现这种操作的控制电路，并且可以用于由多个用户访问的计算机系统中实现的半导体存储器。

9. 发明授权

US5430681A Memory cartridge and its memory control method 失效
标题翻译：内存盒及其内存控制方式
公开(公告)号：US5430681A
公开(公告)日：1995-07-04
申请号：US266870
申请日：1994-07-05
申请人： Ken Sugawara , Shigeru Sakairi , Mikio Matoba , Toshio Sasaki , Katsuhiro Shimohigashi , Katsutaka Kimura
发明人： Ken Sugawara , Shigeru Sakairi , Mikio Matoba , Toshio Sasaki , Katsuhiro Shimohigashi , Katsutaka Kimura
IPC分类号： G11C5/14 , G11C8/18 , G11C11/406 , G11C11/4074 , G11C11/40
CPC分类号： G11C8/18 , G11C11/406 , G11C11/4074 , G11C5/141 , G11C5/143 , G11C5/147
摘要： A memory cartridge having a plurality of dynamic memory units includes an access conversion circuit which converts a static access signal into its inverted signal and an access control circuit which controllably switches between a signal for refreshing each dynamic unit and a signal for external access. The memory cartridge also includes a power switching circuit which switches power from an internal power supply to an external power supply when the memory cartridge is mounted to an external device.
摘要翻译：具有多个动态存储单元的存储器盒包括将静态访问信号转换为其反相信号的访问转换电路和可控地在用于刷新每个动态单元的信号和用于外部访问的信号之间切换的访问控制电路。存储盒还包括一个电源切换电路，当存储盒被安装到外部设备时，电源切换电路将电源从内部电源切换到外部电源。

10. 发明授权

US5331596A Address multiplexed dynamic RAM having a test mode capability 失效
标题翻译：地址复用动态RAM具有测试模式能力
公开(公告)号：US5331596A
公开(公告)日：1994-07-19
申请号：US887802
申请日：1992-05-26
申请人： Kazuyuki Miyazawa , Katsuhiro Shimohigashi , Jun Etoh , Katsutaka Kimura
发明人： Kazuyuki Miyazawa , Katsuhiro Shimohigashi , Jun Etoh , Katsutaka Kimura
IPC分类号： G11C11/401 , G01R31/317 , G11C29/00 , G11C29/14 , G11C29/46 , G11C11/407
CPC分类号： G11C29/46 , G01R31/31701
摘要： An address multiplexed dynamic random access memory (RAM) which has both a normal operation mode and a test mode capability is provided. The test mode is initiated in response to particular signal level combinations of both the row address strobe (RAS) and column address strobe (CAS) signals and the write enable (WE) signal. Since the signal level combinations employed in connection with implementing the test mode are unused in the normal operating mode of the dynamic RAM, additional external terminals are unneeded. This dynamic RAM employs multiplexing circuitry on both the input side as well as on the output side of the dynamic RAM, which multiplexing circuitry is controlled during normal operation by select signals from a decoder and during the test mode by a test signal which allows accessing of data at all of the common complementary data lines by the testing circuitry so as to determine whether there is consistency or inconsistency of the data being read out for testing.
摘要翻译：提供具有正常操作模式和测试模式能力的地址多路复用动态随机存取存储器（RAM）。响应于行地址选通（＆upbar＆R）和列地址选通（＆upbar＆C）信号和写使能（＆upbar＆W）信号的特定信号电平组合，启动测试模式。由于在动态RAM的正常操作模式中不使用与实现测试模式相关的信号电平组合，因此不需要额外的外部终端。该动态RAM在动态RAM的输入侧和输出侧都采用多路复用电路，该复用电路在正常操作期间通过来自解码器的选择信号以及在测试模式期间通过允许访问的测试信号通过测试电路在所有公共补充数据线上的数据，以便确定正在读出的用于测试的数据是否一致或不一致。

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