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1. 发明授权

US4796234A Semiconductor memory having selectively activated blocks including CMOS sense amplifiers 失效
标题翻译：半导体存储器具有选择性地激活的块，包括CMOS读出放大器
公开(公告)号：US4796234A
公开(公告)日：1989-01-03
申请号：US927144
申请日：1986-11-05
申请人： Kiyoo Itoh , Yoshiki Kawajiri , Katsutaka Kimura , Ryoichi Hori , Jun Etoh
发明人： Kiyoo Itoh , Yoshiki Kawajiri , Katsutaka Kimura , Ryoichi Hori , Jun Etoh
IPC分类号： G11C11/409 , G11C7/06 , G11C8/12 , G11C8/14 , G11C11/401 , G11C11/4091 , G11C7/00
CPC分类号： G11C8/14 , G11C11/4091 , G11C7/06 , G11C8/12
摘要： It is contemplated to realize a semiconductor memory with a large memory capacity, high in integration and low in power dissipation. A semiconductor memory is disclosed, comprising a plurality of blocks each having a memory cell array and sense amplifier(s) to differentially amplify signals read out from the array, wherein a common driving line of amplifiers composed of N-channel MOS transistors among said sense amplifiers and a common driving line of amplifiers composed of P-channel MOS transistors among the sense amplifers are connected between different blocks.
摘要翻译：可以想到实现具有大存储容量，高集成度和低功耗的半导体存储器。公开了一种半导体存储器，包括多个块，每个块具有存储单元阵列和读出放大器，用于差分放大从阵列读出的信号，其中由所述感测中的N沟道MOS晶体管组成的公共驱动线放大器和由感测放大器中的P沟道MOS晶体管组成的放大器的公共驱动线连接在不同的块之间。

2. 发明授权

US4503522A Dynamic type semiconductor monolithic memory 失效
标题翻译：动态型半导体单片存储器
公开(公告)号：US4503522A
公开(公告)日：1985-03-05
申请号：US358678
申请日：1982-03-16
申请人： Jun Etoh , Yoshiki Kawajiri , Ryoichi Hori , Kiyoo Itoh
发明人： Jun Etoh , Yoshiki Kawajiri , Ryoichi Hori , Kiyoo Itoh
IPC分类号： G11C11/408 , G11C11/4096 , G11C7/00 , G11C11/40
CPC分类号： G11C11/4085 , G11C11/4096
摘要： A dynamic type semiconductor memory using MOS transistors, in which first and second booster circuits utilizing capacitances, respectively, are provided at each of stages preceding and succeeding to a word driver, respectively. Data lines of the memory are each provided with a voltage compensating circuit for increasing a voltage for charging a memory cell to a level higher than a source voltage for being rewritten in the memory cell. A first boosting circuit is operated after a word line driving pulse signal is produced. Subsequently, word driver selecting transistors are turned off, which is followed by operation of the second booster circuit. Thus, the word line voltage is boosted twice.
摘要翻译：使用MOS晶体管的动态型半导体存储器，其中分别在字驱动器之前和之后的每个级提供利用电容的第一和第二升压电路。存储器的数据线各自设置有电压补偿电路，用于将用于将存储器单元充电的电压提高到高于用于在存储器单元中重写的源电压的电平。在产生字线驱动脉冲信号之后，第一升压电路被操作。随后，字驱动器选择晶体管截止，其后是第二升压电路的操作。因此，字线电压被提升两次。

3. 发明授权

US4475181A Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US4475181A
公开(公告)日：1984-10-02
申请号：US337099
申请日：1982-01-05
申请人： Jun Etoh , Ryoichi Hori , Yoshiki Kawajiri , Kiyoo Itoh
发明人： Jun Etoh , Ryoichi Hori , Yoshiki Kawajiri , Kiyoo Itoh
IPC分类号： G11C8/00 , G11C8/06 , G11C8/18 , G11C11/407 , G11C11/408 , G11C11/418 , H03K5/135 , G11C7/00
CPC分类号： H03K5/135 , G11C11/407 , G11C11/408 , G11C11/418 , G11C8/06 , G11C8/18
摘要： A semiconductor memory of multiplexed address inputs is made operative to receive column addresses and row addresses through common external address lines and to decode them consecutively in response to first and second strobe signals thereby to select one of memory cells. The semiconductor memory is equipped with address buffers exclusively for column and row addressing operations, respectively, the outputs of which are consecutively transmitted to column decoders and row decoders through common internal address lines.
摘要翻译：多路复用地址输入的半导体存储器用于通过公共外部地址线接收列地址和行地址，并且响应于第一和第二选通信号连续解码它们，从而选择一个存储单元。半导体存储器分别配备有用于列和行寻址操作的地址缓冲器，它们的输出通过公共内部地址线连续发送到列解码器和行解码器。

4. 发明授权

US5262999A Large scale integrated circuit for low voltage operation 失效
标题翻译：用于低压运行的大规模集成电路
公开(公告)号：US5262999A
公开(公告)日：1993-11-16
申请号：US838505
申请日：1992-03-24
申请人： Jun Etoh , Kiyoo Itoh , Yoshiki Kawajiri , Yoshinobu Nakagome , Eiji Kume , Hitoshi Tanaka
发明人： Jun Etoh , Kiyoo Itoh , Yoshiki Kawajiri , Yoshinobu Nakagome , Eiji Kume , Hitoshi Tanaka
IPC分类号： G11C5/14 , G11C11/406 , G11C11/4074 , G11C11/4096 , G11C7/00
CPC分类号： G11C5/147 , G11C11/406 , G11C11/4074 , G11C11/4096
摘要： Disclosed is a one-chip ULSI which can carry out the fixed operation in a wide range of power supply voltage (1 V to 5.5 V). This one-chip ULSI is composed of a voltage converter circuit(s) which serves to a fixed internal voltage for a wide range of power supply voltage, an input/output buffer which can be adapted to several input/output levels, a dynamid RAM(s) which can operate at a power supply voltage of 2 V or less, etc. This one-chip ULSI can be applied to compact and portable electronic devices such as a lap-top type personal computer, an electronic pocket note book, a solid-state camera, etc.
摘要翻译：公开了一种单芯片ULSI，其可以在宽范围的电源电压（1V至5.5V）中进行固定操作。该单芯片ULSI由一个电压转换器电路组成，该电路用于宽范围电源电压的固定内部电压，可适用于多个输入/输出电平的输入/输出缓冲器，一个动态RAM 可以在2V以下的电源电压下工作的这种单芯片ULSI可以应用于紧凑型便携式电子设备，例如笔记本型个人计算机，电子口袋笔记本，固态摄像机等

5. 发明授权

US5297097A Large scale integrated circuit for low voltage operation 失效
标题翻译：用于低压运行的大规模集成电路
公开(公告)号：US5297097A
公开(公告)日：1994-03-22
申请号：US366869
申请日：1989-06-14
申请人： Jun Etoh , Kiyoo Itoh , Yoshiki Kawajiri , Yoshinobu Nakagome , Eiji Kume , Hitoshi Tanaka
发明人： Jun Etoh , Kiyoo Itoh , Yoshiki Kawajiri , Yoshinobu Nakagome , Eiji Kume , Hitoshi Tanaka
IPC分类号： G11C5/14 , G11C11/406 , G11C11/4074 , G11C11/4096 , G11C11/407
CPC分类号： G11C11/4096 , G11C11/406 , G11C11/4074 , G11C5/147
摘要： Disclosed is a one-chip ULSI which can carry out fixed operations for a wide range of power supply voltages (1 V to 5.5 V). This one-chip ULSI is composed of a voltage converter circuit(s) which provides a fixed internal voltage for a wide range of power supply voltages, an input/output buffer which can be adapted to several input/out interface levels, a dynamic or volatile RAM(s) which can operate at a power supply voltage of 2 V or less, etc. This one-chip ULSI can be applied to compact and portable electronic devices such as a lap-top type personal computer, an electronic pocket note book, a solid-state camera, etc.
摘要翻译：公开了一种单芯片ULSI，其可以对宽范围的电源电压（1V至5.5V）进行固定操作。该单芯片ULSI由一个电压转换器电路组成，该电路为广泛的电源电压提供固定的内部电压，可适应多个输入/输出接口电平的输入/输出缓冲器，动态或可以在2V以下的电源电压下工作的易失性RAM。该单芯片ULSI可以应用于紧凑型便携式电子设备，例如笔记本型个人计算机，电子口袋笔记本，固态摄像机等

6. 发明授权

US5526313A Large scale integrated circuit with sense amplifier circuits for low voltage operation 失效
公开(公告)号：US5526313A
公开(公告)日：1996-06-11
申请号：US104508
申请日：1993-08-10
申请人： Jun Etoh , Kiyoo Itoh , Yoshiki Kawajiri , Yoshinobu Nakagome , Eiji Kume , Hitoshi Tanaka
发明人： Jun Etoh , Kiyoo Itoh , Yoshiki Kawajiri , Yoshinobu Nakagome , Eiji Kume , Hitoshi Tanaka
IPC分类号： G11C5/14 , G11C11/406 , G11C11/4074 , G11C11/4096 , G11C7/00
CPC分类号： G11C11/4096 , G11C11/406 , G11C11/4074 , G11C5/147
摘要： Disclosed is a one-chip ULSI which can carry out the fixed operation in a wide range of power supply voltage (1 V to 5.5 V). This one-chip ULSI is composed of a voltage converter circuit(s) which serves to a fixed internal voltage for a wide range of power supply voltage, an input/output buffer which can be adapted to several input/output levels, a dynamid RAM(s) which can operate at a power supply voltage of 2 V or less, etc. This one-chip ULSI can be applied to compact and portable electronic devices such as a lap-top type personal computer, an electronic pocket note book, a solid-state camera, etc.

7. 再颁专利

USRE37593E1 Large scale integrated circuit with sense amplifier circuits for low voltage operation 失效
标题翻译：具有读出放大器电路的大规模集成电路用于低电压操作
公开(公告)号：USRE37593E1
公开(公告)日：2002-03-19
申请号：US09095101
申请日：1998-06-10
申请人： Jun Etoh , Kiyoo Itoh , Yoshiki Kawajiri , Yoshinobu Nakagome , Eiji Kume , Hitoshi Tanaka
发明人： Jun Etoh , Kiyoo Itoh , Yoshiki Kawajiri , Yoshinobu Nakagome , Eiji Kume , Hitoshi Tanaka
IPC分类号： G11C700
CPC分类号： G11C11/4096 , G11C5/147 , G11C11/406 , G11C11/4074
摘要： Disclosed is a one-chip ULSI which can carry out the fixed operation in a wide range of power supply voltage (1 V to 5.5 V). This one-chip ULSI is composed of a voltage converter circuit(s) which serves to a fixed internal voltage for a wide range of power supply voltage, an input/output buffer which can be adapted to several input/output levels, a dynamid RAM(s) which can operate at a power supply voltage of 2 V or less, etc. This one-chip ULSI can be applied to compact and portable electronic devices such as a lap-top type personal computer, an electronic pocket note book, a solid-state camera, etc.
摘要翻译：公开了一种单芯片ULSI，其可以在宽范围的电源电压（1V至5.5V）中进行固定操作。该单芯片ULSI由一个电压转换器电路组成，该电路用于宽范围电源电压的固定内部电压，可适用于多个输入/输出电平的输入/输出缓冲器，一个动态RAM 可以在2V以下的电源电压下工作的这种单芯片ULSI可以应用于紧凑型便携式电子设备，例如笔记本型个人计算机，电子口袋笔记本，固态摄像机等

8. 发明授权

US4965769A Semiconductor memory capable of high-speed data erasing 失效
标题翻译：具有高速数据擦除功能的半导体存储器
公开(公告)号：US4965769A
公开(公告)日：1990-10-23
申请号：US278025
申请日：1988-11-30
申请人： Jun Etoh , Kiyoo Itoh , Masakazu Aoki , Ryoichi Hori
发明人： Jun Etoh , Kiyoo Itoh , Masakazu Aoki , Ryoichi Hori
IPC分类号： G11C11/401 , G11C7/20 , G11C8/12 , G11C11/404 , G11C11/4072 , G11C11/408 , H01L27/10
CPC分类号： G11C7/20 , G11C11/4072 , G11C11/4087 , G11C8/12
摘要： A semiconductor memory having a plurality of word lines, and a plurality of data lines arranged to intersect the word lines. Memory cells are arranged at nodes of the word lines and the data lines. Each of the memory cells has a field effect transistor and a capacitor. A word line multiple selection circuit is provided for selecting a plurality of the word lines. The multiple selection circuit simultaneously accesses all of the memory cells by selecting all the word lines of a memory array when a semiconductor memory is in a clear mode. In the clear mode a detector selects data lines of the memory array. A plate voltage control circuit controls a voltage at one plate of each of the capacitors in the memory cells. The plate control circuit changes a voltage at the plate to a preselected clear mode voltage when a semiconductor memory is in a clear mode. It is a feature of the invention that preselected data is written in the memory cells by data communication through the data lines during the clear mode. The preselected data includes at least one "1" data of the preselected data written in the memory cells. Subsequently to end the clear mode operation, the plate voltage control circuit changes the plate voltage for normal operations.
摘要翻译：一种具有多个字线的半导体存储器和与该字线相交的多条数据线。存储单元被布置在字线和数据线的节点处。每个存储单元都具有场效应晶体管和电容器。提供用于选择多个字线的字线多重选择电路。当半导体存储器处于清除模式时，多选择电路通过选择存储器阵列的所有字线来同时访问所有存储单元。在清除模式下，检测器选择存储器阵列的数据线。板电压控制电路控制存储单元中的每个电容器的一个板上的电压。当半导体存储器处于清除模式时，板控制电路将板处的电压改变为预选的清除模式电压。本发明的特征在于，在清除模式期间，通过数据线进行数据通信，将预选数据写入存储单元。预选数据包括写入存储单元的预选数据的至少一个“1”数据。随后结束清除模式操作，板电压控制电路改变正常操作的板电压。

9. 发明授权

US4716313A Pulse drive circuit 失效
标题翻译：脉冲驱动电路
公开(公告)号：US4716313A
公开(公告)日：1987-12-29
申请号：US058617
申请日：1987-06-03
申请人： Ryoichi Hori , Kiyoo Itoh , Jun Etoh
发明人： Ryoichi Hori , Kiyoo Itoh , Jun Etoh
IPC分类号： G11C11/419 , G11C11/401 , G11C11/409 , H03K19/017 , H03K19/0185 , H03K5/02 , H03K17/08 , H03K17/28 , H03K17/284
CPC分类号： H03K19/01707 , H03K19/018507
摘要： In order to drive a capacitance load at a high speed without an undesirably large increase in the circuit size, a driving arrangement is provided to charge the capacitance load in accordance with a limited voltage. A voltage limiter is coupled to a supply voltage providing a predetermined limited voltage. A pulse generator is coupled to receive the limited voltage and to provide output pulses which are, in turn, limited in accordance with the output voltage of the voltage limiter. A driver is coupled between the supply voltage and the capacitance load, and is controlled by the output pulses of the pulse generator. In this way, the capacitance load is charged through the driver in accordance with the limited voltage. Since the voltage limiter is not arranged along a series connection between the driver and the capacitance load, the internal equivalent resistance of the voltage limiter does not detrimentally influence the resistance along the series connection.
摘要翻译：为了以高速度驱动电容负载而不会不期望地大大增加电路尺寸，提供驱动装置以根据有限的电压对电容负载充电。电压限制器耦合到提供预定有限电压的电源电压。耦合脉冲发生器以接收有限的电压并提供输出脉冲，其依次受限于电压限制器的输出电压的限制。驱动器耦合在电源电压和电容负载之间，并由脉冲发生器的输出脉冲控制。以这种方式，电容负载根据限制的电压通过驱动器充电。由于电压限制器不沿着驱动器和电容负载之间的串联连接布置，因此限压器的内部等效电阻不会有害地影响串联电阻。

10. 发明授权

US4873672A Dynamic random access memory capable of fast erasing of storage data 失效
标题翻译：能够快速擦除存储数据的动态随机存取存储器
公开(公告)号：US4873672A
公开(公告)日：1989-10-10
申请号：US51715
申请日：1987-05-20
申请人： Jun Etoh , Katsuhiro Shimohigashi , Kazuyuki Miyazawa , Katsutaka Kimura , Takesada Akiba
发明人： Jun Etoh , Katsuhiro Shimohigashi , Kazuyuki Miyazawa , Katsutaka Kimura , Takesada Akiba
IPC分类号： G11C11/401 , G11C11/4072 , G11C11/4078 , G11C11/409
CPC分类号： G11C11/4078 , G11C11/4072
摘要： This invention relates to a semiconductor memory having a high speed operation and a high integration density. When a high integration semiconductor memory is applied to a large scale computer system, storage data must be erased at a high speed for data security. The present invention erases the storage data by a method which is different from the write method of conventional prior art. In the invention, the erasing operation is made by continuously selecting word lines while sense amplifiers are kept in this on-state. The present invention includes a control circuit for attaining such an operation, and can be used for a semiconductor memory implemented in a computer system accessed by a plurality of users.
摘要翻译：本发明涉及具有高速运算和高集成密度的半导体存储器。当将高集成半导体存储器应用于大规模计算机系统时，为了数据安全，必须高速擦除存储数据。本发明通过与传统现有技术的写入方法不同的方法擦除存储数据。在本发明中，通过在感测放大器保持在该接通状态的同时连续选择字线来进行擦除操作。本发明包括用于实现这种操作的控制电路，并且可以用于由多个用户访问的计算机系统中实现的半导体存储器。

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