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    • 7. 发明授权
    • Image processing method and apparatus suitable for both high-resolution
and low-resolution image data
    • 适用于高分辨率和低分辨率图像数据的图像处理方法和装置
    • US5781666A
    • 1998-07-14
    • US380940
    • 1995-01-31
    • Yasuhisa IshizawaYoshitsugu YamanashiHiroshi NonoshitaKenjiro Chyo
    • Yasuhisa IshizawaYoshitsugu YamanashiHiroshi NonoshitaKenjiro Chyo
    • G06T1/20H04N1/387H04N1/40G06K9/00
    • H04N1/3871G06T1/20H04N1/40068
    • An image processing apparatus makes it possible to efficiently use memories, and to output an image having a high picture quality and a high resolution. The apparatus also makes it possible to reproduce particularly edge portions of an image having a relatively low resolution wherein a plurality of bits are allocated per picture element, with a high resolution. The apparatus further makes it possible to reproduce an image having a high resolution represented by one bit per picture element as an image represented by a plurality of bits per picture element. The apparatus processes a color image obtained by synthesizing a photograph and another photograph, or a photograph and characters with a small memory capacity, and outputs an image having a high quality. That is, the apparatus comprises a memory for storing character/figure images having a high resolution and a small amount of information for one picture element, a memory for storing photographic images having a low resolution and a large amount of information per picture element, and a memory for storing control data for controlling the above-described two kinds of images. An image output having a high picture quality can be obtained with a small amount of information by effectively utilizing features of the above-described two kinds of images. It is thereby possible to reduce the number of devices required for storing information, and therefore to reduce cost. It is also possible to minimize deterioration in picture quality caused by reducing the amount of information.
    • 图像处理装置使得可以有效地使用存储器,并且输出具有高图像质量和高分辨率的图像。 该装置还使得可以以高分辨率再现具有相对低分辨率的图像的特定边缘部分,其中每个图像元素分配多个比特。 该装置还使得可以将具有由每个图像元素的一位表示的高分辨率的图像再现为由每个图像元素的多个比特表示的图像。 该装置处理通过合成照片和另一照片或具有小存储容量的照片和字符而获得的彩色图像,并输出具有高质量的图像。 也就是说,该装置包括一个存储器,用于存储具有高分辨率和一个图像元素的少量信息的字符/图形图像;存储器,用于存储每个图像元素具有低分辨率和大量信息的照相图像;以及 用于存储用于控制上述两种图像的控制数据的存储器。 通过有效地利用上述两种图像的特征,可以通过少量的信息来获得具有高图像质量的图像输出。 从而可以减少存储信息所需的设备数量,从而降低成本。 也可以通过减少信息量来最小化图像质量的恶化。
    • 9. 发明授权
    • Method for logic checking to check operation of circuit to be connected to bus
    • 用于检查要连接到总线的电路运行的逻辑检查方法
    • US08112263B2
    • 2012-02-07
    • US12432394
    • 2009-04-29
    • Yoshihiro TerashimaHiroshi NonoshitaNobuyuki Yuasa
    • Yoshihiro TerashimaHiroshi NonoshitaNobuyuki Yuasa
    • G06F17/50G01R31/00
    • G01R31/318357G01R31/318314G06F17/5022
    • To check operation of a circuit to be checked connected to a bus to which at least one master circuit and at least one slave circuit are connected, a model is connected to a bus in place of a master circuit or a slave circuit and cause given signals to be outputted at given timing for checking the operation of the circuit to be checked. Especially, by causing various data transfer to occur at random timing by a plurality of models, it is easy to cause severer than actual conditions to take place easily, enabling to enhance efficiency of checking. For example, when checking operation of a bus arbiter, a plurality of master models are connected in place of a plurality of master circuits to cause a request of bus accessibility to be outputted from each master model at random timing to check arbitration operation of a bus arbiter.
    • 为了检查要连接到至少一个主电路和至少一个从电路的总线的检查电路的操作,将模型连接到总线来代替主电路或从电路,并且产生给定信号 在给定的定时输出以检查要检查的电路的操作。 特别是通过多个模型的随机定时进行各种数据传送,容易使实际情况变得更加严重,能够提高检查效率。 例如,当检查总线仲裁器的操作时,代替多个主电​​路连接多个主机模型,以便在随机定时从每个主模型输出总线可访问性的请求,以检查总线的仲裁操作 仲裁者。
    • 10. 发明授权
    • Method for logic checking to check operation of circuit to be connected to bus
    • 用于检查要连接到总线的电路运行的逻辑检查方法
    • US07548841B2
    • 2009-06-16
    • US10291508
    • 2002-11-12
    • Yoshihiro TerashimaHiroshi NonoshitaNobuyuki Yuasa
    • Yoshihiro TerashimaHiroshi NonoshitaNobuyuki Yuasa
    • G06F17/50G01R31/00
    • G01R31/318357G01R31/318314G06F17/5022
    • To check operation of a circuit to be checked connected to a bus to which at least one master circuit and at least one slave circuit are connected, a model is connected to a bus in place of a master circuit or a slave circuit and cause given signals to be outputted at given timing for checking the operation of the circuit to be checked. Especially, by causing various data transfer to occur at random timing by a plurality of models, it is early to cause severer than actual conditions to take place easily, enabling to enhance efficiency of checking. For example, when checking operation of a bus arbiter, a plurality of master models are connected in place of a plurality of master circuits to cause a request of bus accessibility to be outputted from each master model at random timing to check arbitration operation of a bus arbiter.
    • 为了检查要连接到至少一个主电路和至少一个从电路的总线的检查电路的操作,将模型连接到总线来代替主电路或从电路,并且产生给定信号 在给定的定时输出以检查要检查的电路的操作。 特别是通过多种模式的随机定时进行各种数据传送,容易引起比实际情况更严重的问题,能够提高检查效率。 例如,当检查总线仲裁器的操作时,代替多个主电​​路连接多个主机模型,以便在随机定时从每个主模型输出总线可访问性的请求,以检查总线的仲裁操作 仲裁者。