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1. 发明授权

US4545010A Memory identification apparatus and method 失效
标题翻译：存储器识别装置和方法
公开(公告)号：US4545010A
公开(公告)日：1985-10-01
申请号：US480964
申请日：1983-03-31
申请人： Edward R. Salas , Edwin P. Fisher , Robert B. Johnson , Chester M. Nibby, Jr. , Daniel A. Boudreau
发明人： Edward R. Salas , Edwin P. Fisher , Robert B. Johnson , Chester M. Nibby, Jr. , Daniel A. Boudreau
IPC分类号： G06F12/06 , G06F13/00
CPC分类号： G06F12/0653
摘要： A memory system includes at least one or more memory module boards identical in construction and a single computer board containing the control circuits for controlling memory operations. Each board plugs into the main board and includes a memory section having a number of rows of memory chips and an identification section containing circuits for generating signals indicating the board density and the type of memory parts used in constructing the board's memory section. The main board control circuits include a number of decoder circuits which couple to the identification and to the memory section of each memory module board. The decoder circuits receive different address bit combinations of a predetermined multibit address portion of each memory request address. In response to signals generated by the identification sections of the installed memory boards, the decoder circuits are selectively enabled to decode those bit combinations of the address portion specified by the sections for enabling successive addressing of all of the blocks of location within the system.
摘要翻译：存储器系统包括至少一个或多个存储器模块板，其结构相同，以及包含用于控制存储器操作的控制电路的单个计算机板。每个板插入主板，并且包括具有多行存储器芯片的存储器部分和用于产生指示板密度的信号的电路的识别部分和用于构建电路板存储部分的存储器部件的类型的识别部分。主板控制电路包括耦合到每个存储器模块板的识别和存储器部分的多个解码器电路。解码器电路接收每个存储器请求地址的预定多位地址部分的不同地址位组合。响应于由所安装的存储器板的识别部分产生的信号，解码器电路被选择性地能够解码由这些部分指定的地址部分的那些比特组合，以便能够对系统内的所有位置块进行连续寻址。

2. 发明授权

US4468731A Identification apparatus for use in a controller to facilitate the diagnosis of faults 失效
标题翻译：用于控制器的识别装置，以便于诊断故障
公开(公告)号：US4468731A
公开(公告)日：1984-08-28
申请号：US330971
申请日：1981-12-15
申请人： Robert B. Johnson , Chester M. Nibby, Jr. , Edward R. Salas
发明人： Robert B. Johnson , Chester M. Nibby, Jr. , Edward R. Salas
IPC分类号： G06F11/22 , G06F11/10
CPC分类号： G06F11/22
摘要： A data processing system includes a main memory system which couples in common with a central processing unit to a bus for transfer of data between the central processing unit and memory system. The memory system includes a plurality of memory controllers, each of which controls the operation of a number of memory modules. Each controller also includes reconfiguration apparatus for enabling reconfiguration of the memory system upon detection of a fault. The reconfiguration apparatus includes apparatus for identifying the type and design revision of the controller associated therewith enabling more expeditious fault diagnosis based upon status signals provided by the controller during diagnostic testing by the central processing unit.
摘要翻译：一种数据处理系统包括一个与中央处理单元共同耦合到总线的主存储系统，用于在中央处理单元和存储器系统之间传送数据。存储器系统包括多个存储器控制器，每个存储器控制器控制多个存储器模块的操作。每个控制器还包括重新配置装置，用于在检测到故障时能够重新配置存储器系统。重新配置装置包括用于识别与其相关联的控制器的类型和设计版本的装置，其基于由中央处理单元在诊断测试期间由控制器提供的状态信号进行更快速的故障诊断。

3. 发明授权

US4507730A Memory system with automatic memory configuration 失效
标题翻译：具有自动内存配置的内存系统
公开(公告)号：US4507730A
公开(公告)日：1985-03-26
申请号：US413631
申请日：1982-09-03
申请人： Robert B. Johnson , Chester M. Nibby, Jr. , Edward R. Salas
发明人： Robert B. Johnson , Chester M. Nibby, Jr. , Edward R. Salas
IPC分类号： G06F11/00 , G06F12/06 , G11C29/00 , G06F13/00
CPC分类号： G11C29/76 , G06F11/006 , G06F12/0661
摘要： A memory system includes a plurality of memory controllers which connect to a common bus. Each memory controller includes reconfiguration apparatus which enables the controller when faulty to be switched off line and another controller to be substituted in its place so as to maintain system memory contiguous.
摘要翻译：存储器系统包括连接到公共总线的多个存储器控制器。每个存储器控制器包括重新配置装置，其使控制器在故障切断时能够使控制器在其位置被替换，从而使系统存储器连续。

4. 发明授权

US4432055A Sequential word aligned addressing apparatus 失效
标题翻译：顺序字对齐寻址装置
公开(公告)号：US4432055A
公开(公告)日：1984-02-14
申请号：US306839
申请日：1981-09-29
申请人： Edward R. Salas , Chester M. Nibby, Jr. , Robert B. Johnson
发明人： Edward R. Salas , Chester M. Nibby, Jr. , Robert B. Johnson
IPC分类号： G06F12/06 , G06F12/04 , G06F13/00 , G11C8/04 , G11C11/4063
CPC分类号： G06F12/04 , G11C11/4063 , G11C8/04
摘要： A memory subsystem which couples to a multiword bus for processing memory requests received therefrom includes at least a pair of independently addressable dynamic memory module units. Each memory unit includes a number of rows of random access memory (RAM) chips. The subsystem further includes an adder circuit, a pair of tristate operated address register circuits and timing circuits. The address circuits include a pair of tristate operated address registers which couple to the bus and to the set of address lines to each memory unit. In response to a memory request, the registers store row and column address portions of a chip address of the memory request. A multibit adder circuit which couples to the bus is connected to increment by one the low order column address portion when the least significant address bit of the memory request indicates a subboundary address condition thereby enabling access to a pair of sequential word locations. Whenever a memory request specifies an address which cannot access a double word, boundary circuits upon detecting the condition cause the timing circuits to generate only timing signals necessary for accessing the first word location.
摘要翻译：耦合到多字总线以用于处理从其接收的存储器请求的存储器子系统包括至少一对独立可寻址的动态存储器模块单元。每个存储器单元包括多行随机存取存储器（RAM）芯片。子系统还包括加法器电路，一对三态操作地址寄存器电路和定时电路。地址电路包括一对三态操作的地址寄存器，其耦合到总线和到每个存储器单元的一组地址线。响应于存储器请求，寄存器存储存储器请求的芯片地址的行和列地址部分。当存储器请求的最低有效地址位指示子边界地址条件从而使得能够访问一对顺序字位置时，耦合到总线的多位加法器电路被连接以递增低位列地址部分的一个。每当存储器请求指定不能访问双字的地址时，边界电路打开检测状态使得定时电路只产生访问第一字位置所必需的定时信号。

5. 发明授权

US4563736A Memory architecture for facilitating optimum replaceable unit (ORU) detection and diagnosis 失效
标题翻译：用于促进最佳可替换单元（ORU）检测和诊断的存储器架构
公开(公告)号：US4563736A
公开(公告)日：1986-01-07
申请号：US509265
申请日：1983-06-29
申请人： Daniel A. Boudreau , Edward R. Salas , Richard C. Zelley
发明人： Daniel A. Boudreau , Edward R. Salas , Richard C. Zelley
IPC分类号： G06F11/20 , G06F11/267 , G06F13/00
CPC分类号： G06F11/267 , G06F11/20
摘要： A single computer board data processing system includes a multiport memory system which is accessible by I/O controllers through a system bus I/O memory port or directly by the system's central processing unit (CPU) via a CPU memory port. The logic and control circuits of the memory ports and CPU are included within the computer main board while memory modules/pacs are contained on one or more memory daughter boards which plug into memory input/output connectors contained on the main board. The port address and data paths connect in common to the memory connectors for transmitting and receiving memory addresses and data between the memory modules and the CPU and I/O ports. At least one register connects between the CPU and to common address path. When the CPU is placed in a diagnostic mode of operation, this register together with existing data registers are conditioned to store signals representative of the address and data being transmitted to the memory modules enabling the CPU to diagnose whether the main board or portions thereof has failed without requiring any testing of the memory modules.
摘要翻译：单个计算机板数据处理系统包括可通过I / O控制器通过系统总线I / O存储器端口或通过CPU存储器端口直接由系统的中央处理器（CPU）访问的多端口存储器系统。存储器端口和CPU的逻辑和控制电路被包括在计算机主板内，而存储器模块/ pac被包含在插入到主板上的存储器输入/输出连接器的一个或多个存储器子板上。端口地址和数据路径共同连接到存储器连接器，用于在存储器模块与CPU和I / O端口之间发送和接收存储器地址和数据。至少有一个寄存器连接在CPU和公共地址路径之间。当CPU处于诊断操作模式时，该寄存器与现有数据寄存器一起被调节为将表示正在发送的地址和数据的信号存储到存储器模块，使得CPU能够诊断主板或其部分是否已经失败而不需要对内存模块进行任何测试。

6. 发明授权

US4787060A Technique for determining maximum physical memory present in a system and for detecting attempts to access nonexistent memory 失效
标题翻译：用于确定系统中存在的最大物理存储器并用于检测尝试访问不存在的存储器的技术
公开(公告)号：US4787060A
公开(公告)日：1988-11-22
申请号：US931956
申请日：1986-11-24
申请人： Daniel A. Boudreau , Edward R. Salas
发明人： Daniel A. Boudreau , Edward R. Salas
IPC分类号： G06F11/00 , G06F11/22 , G06F12/06 , G06F12/14
CPC分类号： G06F11/2289 , G06F11/006 , G06F12/0684
摘要： A method for determining the maximum amount of physical memory present in a data processing system that can be configured to have one or more memory modules where the memory modules may be one of several types having different amounts of memory locations. By having signals indicating the presence of a memory module and the module type directly available with minimal intervening logic, a diagnostic process can accurately determine the amount of memory present in the system and reduce the possibility of a failed memory module going undetected. A method is also descibed using these memory module present and module type signals for detecting an attempt by either the central processor or an input/output controller to access a memory location that is not physically present within the data processing system.
摘要翻译：一种用于确定数据处理系统中存在的物理存储器的最大量的方法，其可被配置为具有一个或多个存储器模块，其中存储器模块可以是具有不同数量的存储器位置的几种类型之一。通过具有指示存在存储器模块的信号和具有最小间隔逻辑直接可用的模块类型，诊断过程可以准确地确定存在于系统中的存储器的量并且减少未检测到故障存储器模块的可能性。还使用存在这些存储器模块和模块类型信号来描述一种方法，该模块类型信号用于检测由中央处理器或输入/输出控制器访问数据处理系统中没有物理存在的存储器位置的尝试。

7. 发明授权

US4493036A Priority resolver having dynamically adjustable priority levels 失效
标题翻译：优先级解析器具有动态可调优先级
公开(公告)号：US4493036A
公开(公告)日：1985-01-08
申请号：US449702
申请日：1982-12-14
申请人： Daniel A. Boudreau , Edward R. Salas
发明人： Daniel A. Boudreau , Edward R. Salas
IPC分类号： G06F13/18 , G06F9/46
CPC分类号： G06F13/18
摘要： A data processing system including a dual ported main memory that can be accessed by I/O controllers via a common bus or directly by the central processing unit. The main memory is comprised of a volatile RAM array that requires periodic refreshing to prevent loss of information. Access to the main memory is controlled by a priority resolver that awards access to the main memory on the basis of predetermined priority levels assigned to CPU, I/O and refresh requests. The priority resolver produces an early signal that is usable to initiate a memory cycle before the final winner of the main memory is determined. The logic path of the lowest priority requester is the shortest path thus allowing the lowest priority requester to initiate a memory cycle in the shortest amount of time even though another requester may ultimately win use of the memory. The priority resolver also provides for the early resetting of access requests so that subsequent requests can be made with minimum delay. Logic is provided that allows the predetermined priority levels to be adjusted dynamically as a function of system conditions.
摘要翻译：一种数据处理系统，包括可通过公共总线或直接由中央处理单元由I / O控制器访问的双端口主存储器。主存储器由易失性RAM阵列组成，需要定期刷新以防止丢失信息。访问主存储器由优先级解析器控制，该优先级解算器根据分配给CPU，I / O和刷新请求的预定优先级来授予对主存储器的访问。优先级解算器产生一个早期信号，该信号可以在确定主存储器的最终获胜者之前启动存储器循环。最低优先级请求者的逻辑路径是最短路径，从而允许最低优先级请求者以最短的时间量启动存储器周期，即使另一个请求者最终可以胜利使用该存储器。优先级解析器还提供访问请求的早期重置，以便可以以最小的延迟进行后续请求。提供了允许根据系统条件动态地调整预定优先级的逻辑。

8. 发明授权

US4964129A Memory controller with error logging 失效
标题翻译：具有错误记录的内存控制器
公开(公告)号：US4964129A
公开(公告)日：1990-10-16
申请号：US287927
申请日：1988-12-21
申请人： Raymond D. Bowden, III , Edward R. Salas , Marc E. Sanfacon , Jeffrey S. Somers
发明人： Raymond D. Bowden, III , Edward R. Salas , Marc E. Sanfacon , Jeffrey S. Somers
IPC分类号： G06F11/07 , G06F11/10
CPC分类号： G06F11/106 , G06F11/073 , G06F11/0772 , G06F11/079
摘要： In accordance with the present invention, there is provided a system for logging an error that occurred in a multi-chip memory storage device in a data processing system. The system has a mechanism for detecting an error and for receiving data and check bits associated therewith. The mechanism for detecting an error generates syndrome bits as a function of the data and of the check bits. Connected to the error detecting mechanism is an error logging mechanism which is adapted to receive the syndrome bits and to determine the chip in which the error occurred.
摘要翻译：根据本发明，提供了一种用于记录在数据处理系统中的多芯片存储器存储装置中发生的错误的系统。该系统具有用于检测错误并用于接收与其相关联的数据和校验位的机制。用于检测错误的机制产生作为数据和校验位的函数的校正子位。连接到错误检测机制的是错误记录机制，其适于接收校正子位并确定发生错误的芯片。

9. 发明授权

US4964130A System for determining status of errors in a memory subsystem 失效
标题翻译：用于确定存储器子系统中的错误状态的系统
公开(公告)号：US4964130A
公开(公告)日：1990-10-16
申请号：US287928
申请日：1988-12-21
申请人： Raymond D. Bowden, III , Edward R. Salas , Marc E. Sanfacon , Jeffrey S. Somers
发明人： Raymond D. Bowden, III , Edward R. Salas , Marc E. Sanfacon , Jeffrey S. Somers
IPC分类号： G06F11/07 , G06F11/10
CPC分类号： G06F11/0766 , G06F11/073 , G06F11/106 , G06F11/1024
摘要： A system and method for detecting an error that occurred in a multi-chip memory storage device in a data processing system. The system detects an error and receives data and check bits associated therewith. A process that uses the principle of scrubbing and incorporates high speed error flags distinguishes between hard and soft errors.
摘要翻译：一种用于检测在数据处理系统中的多芯片存储器存储装置中发生的错误的系统和方法。系统检测到错误并接收与之相关的数据和校验位。使用擦洗原理并结合高速误差标志的过程区分硬错误和软错误。

10. 发明授权

US4600992A Priority resolver with lowest priority level having shortest logic path 失效
标题翻译：具有最低优先级的优先级解算器具有最短的逻辑路径
公开(公告)号：US4600992A
公开(公告)日：1986-07-15
申请号：US449703
申请日：1982-12-14
申请人： Daniel A. Boudreau , Edward R. Salas
发明人： Daniel A. Boudreau , Edward R. Salas
IPC分类号： G06F13/18 , G06F9/46 , G06F15/16
CPC分类号： G06F13/18
摘要： A data processing system including a dual ported main memory that can be accessed by I/O controllers via a common bus or directly by the central processing unit. The main memory is comprised of a volatile RAM array that requires periodic refreshing to prevent loss of information. Access to the main memory is controlled by a priority resolver that awards access to the main memory on the basis of predetermined priority levels assigned to CPU, I/O and refresh requests. The priority resolver produces an early signal that is usable to initiate a memory cycle before the final winner of the main memory is determined. The logic path of the lowest priority requester is the shortest path thus allowing the lowest priority requester to initiate a memory cycle in the shortest amount of time even though another requester may ultimately win use of the memory. The priority resolver also provides for the early resetting of access requests so that subsequent requests can be made with minimum delay.
摘要翻译：一种数据处理系统，包括可通过公共总线或直接由中央处理单元由I / O控制器访问的双端口主存储器。主存储器由易失性RAM阵列组成，需要定期刷新以防止丢失信息。访问主存储器由优先级解析器控制，该优先级解算器根据分配给CPU，I / O和刷新请求的预定优先级来授予对主存储器的访问。优先级解算器产生一个早期信号，该信号可以在确定主存储器的最终获胜者之前启动存储器循环。最低优先级请求者的逻辑路径是最短路径，从而允许最低优先级请求者以最短的时间量启动存储器周期，即使另一个请求者最终可以胜利使用该存储器。优先级解析器还提供访问请求的早期重置，以便可以以最小的延迟进行后续请求。

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