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1. 发明授权

US4964130A System for determining status of errors in a memory subsystem 失效
标题翻译：用于确定存储器子系统中的错误状态的系统
公开(公告)号：US4964130A
公开(公告)日：1990-10-16
申请号：US287928
申请日：1988-12-21
申请人： Raymond D. Bowden, III , Edward R. Salas , Marc E. Sanfacon , Jeffrey S. Somers
发明人： Raymond D. Bowden, III , Edward R. Salas , Marc E. Sanfacon , Jeffrey S. Somers
IPC分类号： G06F11/07 , G06F11/10
CPC分类号： G06F11/0766 , G06F11/073 , G06F11/106 , G06F11/1024
摘要： A system and method for detecting an error that occurred in a multi-chip memory storage device in a data processing system. The system detects an error and receives data and check bits associated therewith. A process that uses the principle of scrubbing and incorporates high speed error flags distinguishes between hard and soft errors.
摘要翻译：一种用于检测在数据处理系统中的多芯片存储器存储装置中发生的错误的系统和方法。系统检测到错误并接收与之相关的数据和校验位。使用擦洗原理并结合高速误差标志的过程区分硬错误和软错误。

2. 发明授权

US4964129A Memory controller with error logging 失效
标题翻译：具有错误记录的内存控制器
公开(公告)号：US4964129A
公开(公告)日：1990-10-16
申请号：US287927
申请日：1988-12-21
申请人： Raymond D. Bowden, III , Edward R. Salas , Marc E. Sanfacon , Jeffrey S. Somers
发明人： Raymond D. Bowden, III , Edward R. Salas , Marc E. Sanfacon , Jeffrey S. Somers
IPC分类号： G06F11/07 , G06F11/10
CPC分类号： G06F11/106 , G06F11/073 , G06F11/0772 , G06F11/079
摘要： In accordance with the present invention, there is provided a system for logging an error that occurred in a multi-chip memory storage device in a data processing system. The system has a mechanism for detecting an error and for receiving data and check bits associated therewith. The mechanism for detecting an error generates syndrome bits as a function of the data and of the check bits. Connected to the error detecting mechanism is an error logging mechanism which is adapted to receive the syndrome bits and to determine the chip in which the error occurred.
摘要翻译：根据本发明，提供了一种用于记录在数据处理系统中的多芯片存储器存储装置中发生的错误的系统。该系统具有用于检测错误并用于接收与其相关联的数据和校验位的机制。用于检测错误的机制产生作为数据和校验位的函数的校正子位。连接到错误检测机制的是错误记录机制，其适于接收校正子位并确定发生错误的芯片。

3. 发明授权

US5204964A Method and apparatus for resetting a memory upon power recovery 失效
标题翻译：电源恢复时重置存储器的方法和装置
公开(公告)号：US5204964A
公开(公告)日：1993-04-20
申请号：US593917
申请日：1990-10-05
申请人： Raymond D. Bowden, III , Michelle A. Pence , George J. Barlow , Marc E. Sanfacon , Jeffrey S. Somers
发明人： Raymond D. Bowden, III , Michelle A. Pence , George J. Barlow , Marc E. Sanfacon , Jeffrey S. Somers
IPC分类号： G06F11/14 , G06F11/20 , G11C7/20 , G11C11/406
CPC分类号： G06F11/1441 , G11C11/406 , G11C7/20 , G06F11/2015
摘要： A method and apparatus for resetting memory state when power is applied to the system. The memory has memory elements, a refresh clock and a refresh counter for counting refresh cycles and providing refresh signals to the memory elements, the memory elements and refresh means being connected from the power system and from a battery back-up means. A state detection means is connected from the refresh counter for detecting a change in state of the refresh counter to a state equivalent to the reset state of the refresh counter and asserting a state change signal. A means responsive to the state change signal and to the occurrence of the reset signal provides a memory controller reset signal, so that the memory controller reset signal occurs in synchronization with the change of state of the refresh counter to a state equivalent to the refresh counter reset state. The memory reset further includes a time-out counter means responsive to the assertion of the reset signal and to the refresh clock for counting refresh cycles in synchronization with the refresh counter. A time-out detection means is responsive to the time out counter means for providing a time out signal when the time-out counter has counted a refresh period plus one clock cycle and to the state change signal for providing the memory controller reset signal when the time-out counter has counted a refresh cycle plus one clock period and the state change signal has not been asserted.
摘要翻译：一种当向系统施加电力时复位存储器状态的方法和装置。存储器具有存储器元件，刷新时钟和刷新计数器，用于对刷新周期进行计数，并向存储器元件提供刷新信号，存储器元件和刷新装置从电力系统和电池备用装置连接。状态检测装置从刷新计数器连接，用于检测刷新计数器的状态改变到与刷新计数器的复位状态相当的状态，并且断言状态改变信号。响应于状态改变信号和复位信号的发生的装置提供存储器控制器复位信号，使得存储器控制器复位信号与刷新计数器的状态改变同步到与刷新计数器相当的状态复位状态。存储器复位还包括响应于重置信号的断言和与刷新计数器同步来刷新周期的刷新时钟的超时计数器装置。超时检测装置响应于超时计数器装置，用于当超时计数器已经计数了刷新周期加一个时钟周期时提供超时信号，以及当状态改变信号提供存储器控制器复位信号时超时计数器已经计数了刷新周期加上一个时钟周期，状态改变信号还没有被断言。

4. 发明授权

US5291580A High performance burst read data transfer operation 失效
标题翻译：高性能突发读取数据传输操作
公开(公告)号：US5291580A
公开(公告)日：1994-03-01
申请号：US771703
申请日：1991-10-04
申请人： Raymond D. Bowden, III , Richard A. Lemay , Chester M. Nibby, Jr. , Jeffrey S. Somers
发明人： Raymond D. Bowden, III , Richard A. Lemay , Chester M. Nibby, Jr. , Jeffrey S. Somers
IPC分类号： G06F13/42 , G06F13/28
CPC分类号： G06F13/4243
摘要： A memory system tightly couples to a high performance microprocessor through a synchronous bus. The logic circuits included in the memory system generate a blipper pulse signal using successive transitions of clock pulse signals other than the edges used to synchronize microprocessor and memory operations. The blipper pulse signal is logically combined with the memory's column address strobe timing signal which is derived from the synchronizing edges of clock pulse signals which defines the duration of the column address interval required for accessing of a pair of DRAM memories during successive memory cycles for providing sequences of four memory read responses with no wait state.
摘要翻译：存储器系统通过同步总线紧密耦合到高性能微处理器。包括在存储器系统中的逻辑电路使用不同于用于同步微处理器和存储器操作的边缘的时钟脉冲信号的连续转换来产生blipper脉冲信号。 blipper脉冲信号与存储器的列地址选通定时信号进行逻辑结合，该定时信号是从时钟脉冲信号的同步边沿导出的，该时钟脉冲信号定义在连续存储器周期期间访问一对DRAM存储器所需的列地址间隔的持续时间，以提供四个内存读取响应的序列，无等待状态。

5. 发明授权

US5345573A High speed burst read address generation with high speed transfer 失效
标题翻译：高速突发读地址生成与高速传输
公开(公告)号：US5345573A
公开(公告)日：1994-09-06
申请号：US771702
申请日：1991-10-04
申请人： Raymond D. Bowden, III , Chester M. Nibby, Jr.
发明人： Raymond D. Bowden, III , Chester M. Nibby, Jr.
IPC分类号： G06F12/08 , G06F13/28 , G11C11/408 , G06F12/00 , G11C11/409
CPC分类号： G06F13/28 , G06F12/0879
摘要： A memory system coupled to a local bus of a microprocessor includes at least a pair of dynamic random access memories (DRAMs) and includes circuits for storing the first address of an address sequence at the beginning of each burst operation and uses predetermined bits to generate any one of a set of address sequences as a function of the states of these bits. A first predetermined address bit is used to select different sequences of addressed readout data words to be transferred by the pair of DRAMs to the user. A second predetermined address bit is complemented to reverse two high order addressed word responses with two low order addressed word responses of specific address sequences. These operations are utilized in all of the required address sequences within different subgroups.
摘要翻译：耦合到微处理器的本地总线的存储器系统包括至少一对动态随机存取存储器（DRAM），并且包括用于在每个突发操作开始时存储地址序列的第一地址的电路，并且使用预定位来产生任何作为这些位的状态的函数的一组地址序列中的一个。第一预定地址位被用于选择由该对DRAM传送给用户的寻址读出数据字的不同序列。对第二预定地址位进行补码，以反转具有特定地址序列的两个低阶寻址字响应的两个高阶寻址字应答。这些操作在不同子组中的所有必需地址序列中使用。

6. 发明授权

US5210867A Method and apparatus for memory retry 失效
标题翻译：用于记忆重试的方法和装置
公开(公告)号：US5210867A
公开(公告)日：1993-05-11
申请号：US593182
申请日：1990-10-05
申请人： George J. Barlow , Raymond D. Bowden, III , Michelle A. Pence
发明人： George J. Barlow , Raymond D. Bowden, III , Michelle A. Pence
IPC分类号： G06F11/14
CPC分类号： G06F11/1402
摘要： Memory retry logic to improve the resilience of system memory operations with respect to system errors or faults which prevent a memory read operation from being completed on a first attempt by allowing the memory to retry the operation once. The memory retry logic detects the occurrence of an improper response from the system element requesting a memory read operation when attempting to initiate the system bus operation for reading the data from memory to the requesting element and, if an improper response indicating that the requesting element is not accepting the bus operation request is detected, stores the memory operation request and the requested data and retries the data transmission on the next available bus cycle. If the memory receives an improper response of a specified type during a bus operation of a memory burst, the memory will terminate the operation and proceed to the next requested operation.
摘要翻译：存储器重试逻辑以提高系统存储器操作相对于系统错误或故障的弹性，从而通过允许存储器重试操作一次来防止存储器读取操作在第一次尝试中完成。当尝试启动用于从存储器读取数据到请求单元的系统总线操作时，存储器重试逻辑检测到来自系统元件的不正确响应的发生，请求存储器读取操作，并且如果指示请求元素是不正确的响应不接受检测到总线操作请求，存储存储器操作请求和请求的数据，并在下一个可用的总线周期重试数据传输。如果在存储器突发的总线操作期间存储器接收到指定类型的不正确响应，则存储器将终止操作并进行下一个所请求的操作。

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