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1. 发明申请

US20060151851A1 ON-PAD BROADBAND MATCHING NETWORK 失效
标题翻译： ON-PAD宽带配对网络
公开(公告)号：US20060151851A1
公开(公告)日：2006-07-13
申请号：US10905624
申请日：2005-01-13
申请人： Edward Pillai , Louis Hsu , Wolfgang Sauter , Daniel Storaska
发明人： Edward Pillai , Louis Hsu , Wolfgang Sauter , Daniel Storaska
IPC分类号： H01L23/48
CPC分类号： H01L23/5227 , H01L23/66 , H01L24/05 , H01L24/48 , H01L27/0255 , H01L2224/0401 , H01L2224/04042 , H01L2224/05093 , H01L2224/05095 , H01L2224/05556 , H01L2224/05599 , H01L2224/131 , H01L2224/48463 , H01L2224/85399 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/0103 , H01L2924/01033 , H01L2924/01041 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/1423 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/00011 , H01L2224/45099 , H01L2924/00
摘要： A chip is provided in which an on-chip matching network has a first terminal conductively connected to a bond pad of the chip and a second terminal conductively connected to a common node on the chip. A wiring trace connects the on-chip matching network to a circuit of the chip. The on-chip matching network includes an electrostatic discharge protection (ESD) circuit having at least one diode having a first terminal conductively connected to the bond pad and a second terminal connected in an overvoltage discharge path to a source of fixed potential. The matching network further includes a first inductor coupled to provide a first inductive path between the bond pad and the wiring trace, a termination resistor having a first terminal connected to the common node, and a second inductor coupled to provide a second inductive path between the wiring trace and a second terminal of the termination resistor.
摘要翻译：提供了芯片，其中片上匹配网络具有导电连接到芯片的焊盘的第一端子和导电连接到芯片上的公共节点的第二端子。接线迹线将片上匹配网络连接到芯片的电路。片上匹配网络包括具有至少一个二极管的静电放电保护（ESD）电路，其具有导电连接到接合焊盘的第一端子和连接到固定电位源的过电压放电路径的第二端子。匹配网络还包括耦合以在接合焊盘和布线迹线之间提供第一感应路径的第一电感器，具有连接到公共节点的第一端子的终端电阻器，以及耦合以在第二电感器之间提供第二电感路径的第二电感器接线迹线和终端电阻的第二个端子。

2. 发明申请

US20060274681A1 APPARATUS AND METHOD FOR REDUCED LOADING OF SIGNAL TRANSMISSION ELEMENTS 有权
标题翻译：用于减少信号传输元件负载的装置和方法
公开(公告)号：US20060274681A1
公开(公告)日：2006-12-07
申请号：US10908959
申请日：2005-06-02
申请人： Louis Hsu , Karl Selander , Michael Sorna , Daniel Storaska
发明人： Louis Hsu , Karl Selander , Michael Sorna , Daniel Storaska
IPC分类号： H04B1/58
CPC分类号： G06F13/4072
摘要： An apparatus is provided which includes a common signal node operable to conduct a first signal, a first circuit coupled to the common signal node to utilize the first signal and a signal-handling element coupled to the common signal node. The signal-handling element includes an isolating circuit coupled to the first conductor, a second conductor operable to conduct an output of the isolating circuit, and a signal-handling circuit coupled to the second conductor. The signal-handling circuit is operable to perform a signal-handling function in response to the output of the isolating circuit. By virtue of the isolating circuit, the signal-handling circuit and the first circuit are isolated from the second conductor and the signal-handling circuit. Preferably, the achieved isolation permits a communication signal included in the first signal to be conducted within a communication apparatus with less capacitance, and producing less return loss of that signal.
摘要翻译：提供一种装置，其包括可操作以传导第一信号的公共信号节点，耦合到公共信号节点以利用第一信号的第一电路和耦合到公共信号节点的信号处理元件。信号处理元件包括耦合到第一导体的隔离电路，可操作以导通隔离电路的输出的第二导体和耦合到第二导体的信号处理电路。信号处理电路可操作以响应于隔离电路的输出执行信号处理功能。通过隔离电路，信号处理电路和第一电路与第二导体和信号处理电路隔离。优选地，所实现的隔离允许包含在第一信号中的通信信号在具有较小电容的通信设备内传导，并且产生较小的该信号的回波损耗。

3. 发明授权

US06778447B2 Embedded DRAM system having wide data bandwidth and data transfer data protocol 有权
标题翻译：具有宽数据带宽和数据传输数据协议的嵌入式DRAM系统
公开(公告)号：US06778447B2
公开(公告)日：2004-08-17
申请号：US10062972
申请日：2002-01-31
申请人： Louis L. Hsu , Rajiv V. Joshi , Jeremy Stephens , Daniel Storaska
发明人： Louis L. Hsu , Rajiv V. Joshi , Jeremy Stephens , Daniel Storaska
IPC分类号： G11C700
CPC分类号： G11C7/1006 , G11C7/1048 , G11C7/22 , G11C2207/104
摘要： A self-timed data communication system for a wide data width semiconductor memory system having a plurality of data paths is provided. The data communication system includes a central data path including at least one junction circuit configured for exchanging data signals between the central data path and the plurality of data paths of the at least one data path. A respective one junction circuit of the at least one junction circuit includes circuitry for controlling resetting the respective one junction circuit for preparation of a subsequent data transfer through the respective one junction circuit in accordance with receipt of an input junction monitor signal indicating that data has been transferred to the respective one junction circuit. The data communication system further includes a plurality of data banks configured for storing data, wherein a corresponding data bank of the plurality of data banks is connected to a respective one data path of the plurality of data paths. The data communication system further includes circuitry for controlling the respective one data path in accordance with receipt of a monitor signal indicating that a data transfer operation has been initiated for transfer of data from the respective one data path. The circuitry for controlling includes circuitry for generating a control signal for controlling resetting of the respective one data path after data is transferred for preparation of a subsequent data transfer operation.
摘要翻译：提供了具有多个数据路径的宽数据宽度半导体存储器系统的自定时数据通信系统。该数据通信系统包括中央数据路径，该中央数据路径包括至少一个结电路，该至少一个结电路被配置用于在中央数据路径与至少一条数据路径的多条数据路径之间交换数据信号。所述至少一个结电路的相应的一个结电路包括用于根据接收到指示数据已经被输入的输入结监视器信号来控制复位相应的一个结电路以准备通过相应的一个结电路的后续数据传输的电路转移到相应的一个结电路。数据通信系统还包括被配置用于存储数据的多个数据组，其中多个数据组中相应的数据组连接到多个数据路径中相应的一个数据路径。数据通信系统还包括用于根据接收到指示已经发起数据传送操作的监视信号来控制相应的一个数据路径的电路，用于从相应的一个数据路径传送数据。用于控制的电路包括用于产生控制信号的电路，该控制信号用于在传送数据以准备随后的数据传送操作之后控制相应的一个数据路径的复位。

4. 发明授权

US06266272B1 Partially non-volatile dynamic random access memory formed by a plurality of single transistor cells used as DRAM cells and EPROM cells 有权
标题翻译：由用作DRAM单元和EPROM单元的多个单晶体管单元形成的部分非易失性动态随机存取存储器
公开(公告)号：US06266272B1
公开(公告)日：2001-07-24
申请号：US09364841
申请日：1999-07-30
申请人： Toshiaki Kirihata , Daniel Storaska , Chandrasekhar Narayan , William Tonti , Claude Bertin , Nick van Heel
发明人： Toshiaki Kirihata , Daniel Storaska , Chandrasekhar Narayan , William Tonti , Claude Bertin , Nick van Heel
IPC分类号： G11C1450
CPC分类号： G11C16/02 , G11C11/005
摘要： A Partially Non-Volatile Dynamic Random Access Memory (PNDRAM) uses a DRAM array formed by a plurality of single transistor (1T) cells or two transistor (2T) cells. The cells are electrically programmable as a non-volatile memory. This results in a single chip design featuring both, a dynamic random access memory (DRAM) and an electrically programmable-read-only-memory (EPROM). The DRAM and the EPROM integrated in the PNDRAM can be easily reconfigured at any time, whether during manufacturing or in the field. The PNDRAM has multiple applications such as combining a main memory with ID, BIOS, or operating system information in a single chip.
摘要翻译：部分非易失性动态随机存取存储器（PNDRAM）使用由多个单晶体管（1T）单元或两个晶体管（2T）单元形成的DRAM阵列。电池可电可编程为非易失性存储器。这导致具有动态随机存取存储器（DRAM）和电可编程只读存储器（EPROM）的单芯片设计。集成在PNDRAM中的DRAM和EPROM可以随时重新配置，无论是在制造还是在现场。 PNDRAM具有多个应用，例如将主内存与ID，BIOS或操作系统信息组合在一个芯片中。

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