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1. 发明授权

US07203818B2 Microcontroller instruction set 有权
标题翻译：微控制器指令集
公开(公告)号：US07203818B2
公开(公告)日：2007-04-10
申请号：US10796771
申请日：2004-03-09
申请人： Edward Brian Boles , Rodney Jay Drake , Darrel Ray Johansen , Sumit K. Mitra , Randy Yach , James Grosbach , Joshua M. Conner , Joseph W. Triece
发明人： Edward Brian Boles , Rodney Jay Drake , Darrel Ray Johansen , Sumit K. Mitra , Randy Yach , James Grosbach , Joshua M. Conner , Joseph W. Triece
IPC分类号： G06F12/00 , G06F15/00
CPC分类号： G06F9/30192 , G06F9/30032 , G06F9/3004 , G06F9/30101 , G06F9/3012 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/30167 , G06F9/321 , G06F9/325
摘要： A microcontroller apparatus is provided with an instruction set for manipulating the behavior of the microcontroller. The apparatus and system is provided that enables a linearized address space that makes modular emulation possible. Direct or indirect addressing is possible through register files or data memory. Special function registers, including the Program Counter (PC) and Working Register (W), are mapped in the data memory. An orthogonal (symmetrical) instruction set makes possible any operation on any register using any addressing mode. Consequently, two file registers to be used to some two operand instructions. This allows data to be moved directly between two registers without going through the W register. Thus, increasing performance and decreasing program memory usage.
摘要翻译：微控制器装置设置有用于操纵微控制器的行为的指令集。提供了使得能够实现模块化仿真的线性化地址空间的装置和系统。可以通过寄存器文件或数据存储器进行直接或间接寻址。特殊功能寄存器，包括程序计数器（PC）和工作寄存器（W），映射到数据存储器中。正交（对称）指令集可以使用任何寻址模式对任何寄存器进行任何操作。因此，两个文件寄存器用于一些两个操作数指令。这允许在两个寄存器之间直接移动数据，而不经过W寄存器。因此，提高性能并减少程序内存使用。

2. 发明授权

US5987583A Processor architecture scheme and instruction set for maximizing available opcodes and address selection modes 失效
标题翻译：处理器架构方案和指令集，用于最大化可用的操作码和地址选择模式
公开(公告)号：US5987583A
公开(公告)日：1999-11-16
申请号：US959942
申请日：1997-10-29
申请人： Joseph W. Triece , Sumit K. Mitra
发明人： Joseph W. Triece , Sumit K. Mitra
IPC分类号： G06F9/30 , G06F9/318 , G06F9/34 , G06F9/35 , G06F9/355
CPC分类号： G06F9/30181 , G06F9/30101 , G06F9/35
摘要： A system for allowing multiple addressing modes while maximizing a number of available opcodes and addressable registers. The system has a processor architecture scheme which allows for encoding of multiple addressing modes through use of virtual register addresses. The system has an instruction set having a plurality of instructions. Each instruction has a plurality of bits wherein none of the plurality of bits in each of the plurality of instructions are dedicated bits for implementing different addressing modes. Each of the plurality of instructions are able to implement different addressing modes by addressing the virtual register addresses in the processor architecture scheme. Since no bits are required for implementing different addressing modes, the length of the opcode field and the register address field are determined by the number of opcodes and the number of addressable registers the user wishes to implement.
摘要翻译：一种允许多个寻址模式同时最大化可用操作码和可寻址寄存器数量的系统。该系统具有处理器架构方案，其允许通过使用虚拟寄存器地址对多个寻址模式进行编码。该系统具有指令集，该指令集具有多个指令。每个指令具有多个位，其中多个指令中的每一个中的多个位中的每一个都不是用于实现不同寻址模式的专用位。多个指令中的每一个能够通过在处理器架构方案中寻址虚拟寄存器地址来实现不同的寻址模式。由于不需要位来实现不同的寻址模式，所以操作码字段和寄存器地址字段的长度由操作码的数量和用户希望实现的可寻址寄存器的数量来确定。

3. 发明授权

US06192463B1 Processor architecture scheme which uses virtual address registers to implement different addressing modes and method therefor 失效
标题翻译：处理器架构方案使用虚拟地址寄存器来实现不同的寻址模式及其方法
公开(公告)号：US06192463B1
公开(公告)日：2001-02-20
申请号：US08946426
申请日：1997-10-07
申请人： Sumit K. Mitra , Joseph W. Triece
发明人： Sumit K. Mitra , Joseph W. Triece
IPC分类号： G06F926
CPC分类号： G06F9/30138 , G06F9/35
摘要： A processor architecture scheme which allows for encoding of multiple addressing modes through use of virtual register addresses in order to maximize number of directly addressable registers in the processor architecture scheme. A set of virtual address register locations associated with an indirect addressing pointer is reserved in memory. The number of virtual register address locations reserved is equal to a number of indirect addressing modes associated with the indirect addressing pointer. Each of the virtual register address locations initiates an indirect addressing mode to be used with the associated indirect addressing pointer when accessed.
摘要翻译：一种处理器架构方案，其允许通过使用虚拟寄存器地址对多个寻址模式进行编码，以便最大化处理器架构方案中直接可寻址寄存器的数量。与间接寻址指针相关联的一组虚拟地址寄存器位置被保留在存储器中。保留的虚拟寄存器地址位置的数量等于与间接寻址指针相关联的间接寻址模式的数量。每个虚拟寄存器地址位置启动间接寻址模式，以在访问时与相关联的间接寻址指针一起使用。

4. 发明授权

US06578139B1 Processor architecture scheme which uses virtual address registers to implement different addressing modes and method therefor 有权
标题翻译：处理器架构方案使用虚拟地址寄存器来实现不同的寻址模式及其方法
公开(公告)号：US06578139B1
公开(公告)日：2003-06-10
申请号：US09691375
申请日：2000-10-18
申请人： Sumit K. Mitra , Joseph W. Triece
发明人： Sumit K. Mitra , Joseph W. Triece
IPC分类号： G06F922
CPC分类号： G06F9/30138 , G06F9/35
摘要： A processor architecture scheme which allows for encoding of multiple addressing modes through use of virtual register addresses in order to maximize number of directly addressable registers in the processor architecture scheme. A set of virtual address register locations associated with an indirect addressing pointer is reserved in memory. The number of virtual register address locations reserved is equal to a number of indirect addressing modes associated with the indirect addressing pointer. Each of the virtual register address locations initiates an indirect addressing mode to be used with the associated indirect addressing pointer when accessed.
摘要翻译：一种处理器架构方案，其允许通过使用虚拟寄存器地址对多个寻址模式进行编码，以便最大化处理器架构方案中直接可寻址寄存器的数量。与间接寻址指针相关联的一组虚拟地址寄存器位置被保留在存储器中。保留的虚拟寄存器地址位置的数量等于与间接寻址指针相关联的间接寻址模式的数量。每个虚拟寄存器地址位置启动间接寻址模式，以在访问时与相关联的间接寻址指针一起使用。

5. 发明授权

US07265708B2 Analog-to-digital converter with interchangeable resolution and sample and hold amplifier channels 有权
标题翻译：具有可互换分辨率和采样和保持放大器通道的模数转换器
公开(公告)号：US07265708B2
公开(公告)日：2007-09-04
申请号：US11358289
申请日：2006-02-21
申请人： Sumit K. Mitra , Harry Hu , Pieter Schieke
发明人： Sumit K. Mitra , Harry Hu , Pieter Schieke
IPC分类号： H03M1/12
CPC分类号： H03M1/004 , H03M1/007 , H03M1/1225 , H03M1/468 , H03M1/68 , H03M1/804
摘要： A successive approximation register analog-to-digital converter (SAR ADC) having a sample, hold and convert amplifier circuit may be configured for either a single channel SAR ADC or a multiple channel SAR ADC. Switches or metal connection options, e.g., bit configurable or metal mask configurable, respectively, may be used to configure a common capacitor area, a portion of which may be used as a reconfigurable charge-redistribution digital-to-analog converter (CDAC) of the SAR ADC as either a single channel sample, hold and convert 12-bit capacitor configuration or a four channel sample, hold and convert 10-bit capacitor configuration. All other parts of the SAR ADC circuitry may be substantially the same for either configuration, e.g., the resistive digital-to-analog converter (RDAC), successive approximation register (SAR), ADC controller, sample, hold and convert switches, comparator, etc, may be substantially the same for either the single or multiple channel SAR ADC configurations.
摘要翻译：具有采样，保持和转换放大器电路的逐次逼近寄存器模数转换器（SAR ADC）可以配置为单通道SAR ADC或多通道SAR ADC。可以分别使用开关或金属连接选项，例如位配置或金属掩模可配置，以配置公共电容器区域，其一部分可用作可重新配置的电荷再分配数模转换器（CDAC） SAR ADC作为单通道采样，保持和转换12位电容配置或四通道采样，保持和转换10位电容配置。 SAR ADC电路的所有其他部分对于任一配置可能基本相同，例如电阻数模转换器（RDAC），逐次逼近寄存器（SAR），ADC控制器，采样，保持和转换开关，比较器，对于单通道或多通道SAR ADC配置可能基本相同。

6. 发明授权

US5577235A Microcontroller with multiple timing functions available in a single peripheral module 失效
标题翻译：具有多个定时功能的单片机可在单个外设模块中使用
公开(公告)号：US5577235A
公开(公告)日：1996-11-19
申请号：US298775
申请日：1994-08-31
申请人： Sumit K. Mitra
发明人： Sumit K. Mitra
IPC分类号： G06F9/22 , G06F1/14 , G06F15/78 , G06F19/00
CPC分类号： G06F15/7814
摘要： A microcontroller chip with a central processing unit (CPU) is adapted to control an external system with which the device is to be installed in circuit. The microcontroller chip includes an on-chip peripheral universal timing function module with a register for storing a value selected to signify a distinctive event in a waveform. A timer generates a series of values as a function of time as a measure of the value selected to signify the distinctive event. The register and the timer are coupled to a pin of the microcontroller chip on which said waveform is to be applied. Equality between the values in the timer and the register signify the distinctive event as one of a capture and a compare of an event in the waveform, to generate an interrupt to the CPU. The register is selectively split into separate master and slave registers for automatic synchronization of the transfer of a value entered into the master register to the slave register with a repetitive boundary of the waveform, to provide selective pulse width modulation of the waveform.
摘要翻译：具有中央处理单元（CPU）的微控制器芯片适于控制在该电路中安装该设备的外部系统。微控制器芯片包括具有寄存器的片上外设通用定时功能模块，用于存储所选择的值以表示波形中的特殊事件。定时器产生作为时间的函数的一系列值作为选择用于表示特征事件的值的量度。寄存器和定时器耦合到要施加所述波形的微控制器芯片的引脚。定时器和寄存器之间的值之间的相等性将特征事件表示为波形中的事件的捕获和比较之一，以产生CPU的中断。该寄存器选择性地分成独立的主寄存器和从寄存器，用于自动同步输入到主寄存器的值到具有波形重复边界的从寄存器，以提供波形的选择性脉宽调制。

7. 发明授权

US5014191A Security for digital signal processor program memory 失效
标题翻译：数字信号处理器程序存储器的安全性
公开(公告)号：US5014191A
公开(公告)日：1991-05-07
申请号：US189189
申请日：1988-05-02
申请人： Ajay J. Padgaonkar , Sumit K. Mitra
发明人： Ajay J. Padgaonkar , Sumit K. Mitra
IPC分类号： G06F21/00
CPC分类号： G06F21/79 , G06F21/74 , G06F2221/2105
摘要： The processor executes programs from an internal EEPROM or from an external source. The EEPROM can be read either by a special operating (test) mode of the processor or by an instruction executing under normal operating mode from the EEPROM or from an external source. Similarly, the EEPROM can be programmed (written) either by a special operating mode or by under a normal operating mode instruction. The read and write circuits for the EEPROM are controlled to provide two levels of security against piracy of programmed information. In the first level, access is prevented for the read and write test modes and also for the read and write normal operating instructions if the instructions originate from an external source. In the second level, program execution from external source is also disabled.
摘要翻译：处理器从内部EEPROM或外部源执行程序。 EEPROM可以通过处理器的特殊操作（测试）模式或通过从EEPROM或外部源在正常工作模式下执行的指令来读取。类似地，EEPROM可以通过特殊操作模式或正常工作模式指令进行编程（写入）。控制EEPROM的读和写电路，以提供两级安全性，防止编程信息的盗版。在第一级中，如果指令源于外部源，则可以访问读取和写入测试模式以及读取和写入正常操作指令。在第二级，外部源程序执行也被禁用。

8. 发明授权

US5594894A Microcontroller with programmable postscaler for pulse width modulation interrupt 失效
标题翻译：具有可编程后分频器的微控制器，用于脉宽调制中断
公开(公告)号：US5594894A
公开(公告)日：1997-01-14
申请号：US319985
申请日：1994-10-07
申请人： Sumit K. Mitra
发明人： Sumit K. Mitra
IPC分类号： G06F1/025 , G06F1/14 , G06F9/06
CPC分类号： G06F1/025
摘要： A microcontroller device is fabricated in a semiconductor integrated circuit chip for controlling an external system with which the microcontroller device is to be installed in circuit. The device includes a CPU, a program memory, a data memory, and peripherals for use in controlling the external system. An on-chip peripheral timing module establishes the timing of and degree of control exercised over the external system by a generating a repetitive event configured as a pulse waveform. The timing module is adapted for selectively setting the period of the pulse waveform to designate the frequency of occurrence of the repetitive event for the timing of control and to provoke a corresponding periodic interrupt of the CPU. The width of the pulse in each period of the pulse waveform is selectively modulated to set the degree of control. The timing module selectively varies the frequency of periodic interrupts of the CPU without affecting the period of the pulse waveform. In one embodiment, the selective variation of frequency of the periodic interrupts is performed by a divider circuit.
摘要翻译：微控制器装置制造在半导体集成电路芯片中，用于控制将微控制器装置安装在电路中的外部系统。该设备包括CPU，程序存储器，数据存储器以及用于控制外部系统的外围设备。片上外设定时模块通过产生被配置为脉冲波形的重复事件来建立对外部系统执行的时序和控制程度。定时模块适于选择性地设置脉冲波形的周期以指定控制定时的重复事件的发生频率，并引起CPU的相应周期性中断。脉冲波形的每个周期中的脉冲宽度被有选择地调制以设定控制度。定时模块选择性地改变CPU的周期性中断的频率，而不影响脉冲波形的周期。在一个实施例中，周期性中断的频率的选择性变化由分频器电路执行。

9. 发明授权

US5212780A System for single cycle transfer of unmodified data to a next sequentially higher address in a semiconductor memory 失效
标题翻译：用于将未修改数据单周期传送到半导体存储器中的下一个顺序更高地址的系统
公开(公告)号：US5212780A
公开(公告)日：1993-05-18
申请号：US191983
申请日：1988-05-09
申请人： Ajay J. Padgaonkar , Sumit K. Mitra
发明人： Ajay J. Padgaonkar , Sumit K. Mitra
IPC分类号： G06F5/01 , G11C7/10
CPC分类号： G06F5/01 , G11C7/1006
摘要： The RAM includes sub-arrays having odd and even memory locations, respectively. A data move instruction results in externally generated row and column address signals which are decoded to cause a first memory location, in one of the sub-arrays, to be selected and data to be read. The next memory location in sequence, in the other of the sub-arrays, is then selected, without necessity for an additional set of row address signals, for writing of the read information. The row decoder includes row indexing circuitry actuatable upon receipt of a shift signal signifying that the first memory location is in the last column of a given row. When the shift signal is received, the write location is automatically selected to be in the succeeding row.
摘要翻译： RAM包括分别具有奇数和偶数存储器位置的子阵列。数据移动指令导致外部产生的行和列地址信号，其被解码以引起在其中一个子阵列中的第一存储器位置和要读取的数据。然后，在另一个子阵列中顺序地选择下一个存储器位置，而不需要额外的行地址信号组来写入读取的信息。行解码器包括在接收到表示第一存储器位置在给定行的最后一列中的移位信号时可操作的行索引电路。当接收到移位信号时，自动选择写入位置在后面的行中。

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