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1. 发明授权

US08949635B2 Integrated circuit performance improvement across a range of operating conditions and physical constraints 有权
标题翻译：在一系列操作条件和物理限制下的集成电路性能改进
公开(公告)号：US08949635B2
公开(公告)日：2015-02-03
申请号：US11864886
申请日：2007-09-28
申请人： Stephen H. Gunther , Stephan Jourdan , Robert Greiner , Edward A. Burton , Anant S. Deval , Michael Cornaby , Jeremy Shrall , Ray Ramadorai
发明人： Stephen H. Gunther , Stephan Jourdan , Robert Greiner , Edward A. Burton , Anant S. Deval , Michael Cornaby , Jeremy Shrall , Ray Ramadorai
IPC分类号： G06F1/32 , G06F9/38 , G06F9/30
CPC分类号： G06F9/3885 , G06F1/32 , G06F9/30181 , G06F9/3891
摘要： Methods and apparatus to improve integrated circuit (IC) performance across a range of operating conditions and/or physical constraints are described. In one embodiment, an operating parameter of one or more of processor cores may be adjusted in response to a change in the activity level of processor cores (e.g., the number of active processor cores) and/or a comparison of one or more operating conditions and one or more corresponding threshold values. Other embodiments are also described.
摘要翻译：描述了在一系列操作条件和/或物理约束下改善集成电路（IC）性能的方法和装置。在一个实施例中，可以响应于处理器核心的活动水平（例如，活动处理器核心的数量）的变化和/或一个或多个操作条件的比较来调整处理器核心中的一个或多个处理器核心的操作参数和一个或多个相应的阈值。还描述了其它实施例。

2. 发明申请

US20120226926A1 INDEPENDENT POWER CONTROL OF PROCESSING CORES 审中-公开
标题翻译：加工过程中的独立功率控制
公开(公告)号：US20120226926A1
公开(公告)日：2012-09-06
申请号：US13471222
申请日：2012-05-14
申请人： Stephen H. Gunther , Edward A. Burton , Anant Deval , Stephan Jourdan , Robert Greiner , Michael Cornaby
发明人： Stephen H. Gunther , Edward A. Burton , Anant Deval , Stephan Jourdan , Robert Greiner , Michael Cornaby
IPC分类号： G06F1/32
CPC分类号： G06F1/3234 , G06F1/3203 , G06F1/324 , G06F1/3287 , G06F1/3296
摘要： Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores.
摘要翻译：两个或多个处理核心的独立功率控制。更具体地，本发明的至少一个实施例涉及将至少一个处理核放置在功率状态而不与一个或多个其它处理核的功率状态协调的技术。

3. 发明授权

US07449966B2 Method and an apparatus to sense supply voltage 有权
标题翻译：检测电源电压的方法和装置
公开(公告)号：US07449966B2
公开(公告)日：2008-11-11
申请号：US11431256
申请日：2006-05-09
申请人： Edward A. Burton , Robert J. Greiner , Anant S. Deval , Douglas R. Huard
发明人： Edward A. Burton , Robert J. Greiner , Anant S. Deval , Douglas R. Huard
IPC分类号： H03B27/00
CPC分类号： H03K3/0315 , G01R19/0084 , H03K5/19
摘要： A method and an apparatus to sense supply voltage have been disclosed. In one embodiment, the apparatus includes a resistor having a first end and a second end, the first end coupled to a voltage supply and a ring oscillator sensor coupled between the second end of the resistor and ground, the ring oscillator sensor having an output coupled to a computational element. Other embodiments have been claimed and described.
摘要翻译：已经公开了一种感测电源电压的方法和装置。在一个实施例中，该装置包括具有第一端和第二端的电阻器，第一端耦合到电压源和耦合在电阻器的第二端和地之间的环形振荡器传感器，环形振荡器传感器具有输出耦合到计算元素。已经要求和描述了其它实施例。

4. 发明授权

US07282975B2 Apparatus and method to control self-timed and synchronous systems 有权
标题翻译：控制自定时和同步系统的装置和方法
公开(公告)号：US07282975B2
公开(公告)日：2007-10-16
申请号：US10750320
申请日：2003-12-31
申请人： Edward A. Burton , Paul Madland
发明人： Edward A. Burton , Paul Madland
IPC分类号： H03L7/00
CPC分类号： G06F1/04
摘要： An apparatus includes a substrate, a target timing circuit, a leakage timing circuit, and a control unit. The target timing circuit and the leakage timing circuits are formed on the substrate. The target timing circuit has a target timing circuit frequency related to a target frequency. The leakage timing circuit has a leakage timing circuit frequency related to a leakage current. The control unit maintains a substantially constant ratio between the target timing circuit frequency and the leakage timing circuit frequency. A method includes generating a first signal related to a target circuit frequency, generating a second signal related to a leakage current, and adjusting a control signal applied to a substrate to maintain a substantially constant frequency ratio between a first signal and the second signal.
摘要翻译：一种装置包括基板，目标定时电路，泄漏定时电路和控制单元。目标定时电路和泄漏定时电路形成在基板上。目标定时电路具有与目标频率相关的目标定时电路频率。泄漏定时电路具有与漏电流相关的泄漏定时电路频率。控制单元在目标定时电路频率和泄漏定时电路频率之间保持基本恒定的比率。一种方法包括产生与目标电路频率相关的第一信号，产生与漏电流相关的第二信号，以及调整施加到衬底的控制信号，以保持第一信号和第二信号之间基本恒定的频率比。

5. 发明授权

US07138716B2 Addition of metal layers with signal reallocation to a microprocessor for increased frequency and lower power 有权
标题翻译：添加具有信号重新分配到微处理器的金属层，以提高频率和更低的功率
公开(公告)号：US07138716B2
公开(公告)日：2006-11-21
申请号：US10607550
申请日：2003-06-27
申请人： Edward A. Burton , Kumar Anshumali
发明人： Edward A. Burton , Kumar Anshumali
IPC分类号： H01L23/48 , H01L29/739
CPC分类号： H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device and method of adding metal layers in a semiconductor device with signal reallocation are disclosed. The device has a first layer with a plurality of signal wires. A second layer adjacent to the first layer is also included that has a plurality of signal wires. The signal wires in the first and second layers are substantially parallel with each other. The signal wires are distributed between the first and second layer in a manner that reduces the wire capacitance and/or resistance thereby permitting higher frequency operation and lower power consumption in the device.
摘要翻译：公开了一种在具有信号再分配的半导体器件中添加金属层的半导体器件和方法。该装置具有带有多条信号线的第一层。还包括与第一层相邻的第二层，其具有多条信号线。第一层和第二层中的信号线基本上彼此平行。信号线以降低线电容和/或电阻的方式分布在第一和第二层之间，从而允许器件中的较高频率操作和较低功耗。

6. 发明授权

US06924710B2 Voltage ID based frequency control for clock generating circuit 有权
标题翻译：用于时钟发生电路的基于电压ID的频率控制
公开(公告)号：US06924710B2
公开(公告)日：2005-08-02
申请号：US10659637
申请日：2003-09-09
申请人： Keng L. Wong , Hong-Piao Ma , Greg F. Taylor , Chee How Lim , Robert Greiner , Edward A. Burton , Douglas R. Huard
发明人： Keng L. Wong , Hong-Piao Ma , Greg F. Taylor , Chee How Lim , Robert Greiner , Edward A. Burton , Douglas R. Huard
IPC分类号： G06F1/08 , G06F1/10 , H03L7/099 , H03L7/18 , H03L1/00
CPC分类号： G06F1/3203 , G06F1/08 , G06F1/10 , H03L7/0995 , H03L7/18 , Y02D10/126
摘要： An apparatus and method are provided for operating a processor core. This may include a first circuit to operate at a frequency that is dependent on a power supply voltage. A frequency control circuit may be provided to control a frequency of the first circuit by directing a voltage regulator to increase or decrease the power supply voltage.
摘要翻译：提供了一种用于操作处理器核心的装置和方法。这可以包括在取决于电源电压的频率下操作的第一电路。可以提供频率控制电路以通过引导电压调节器来增加或减少电源电压来控制第一电路的频率。

7. 发明授权

US06429051B1 Stitched plane structure for package power delivery and dual referenced stripline I/O performance 失效
标题翻译：用于封装电源传输和双参考带状线I / O性能的缝合平面结构
公开(公告)号：US06429051B1
公开(公告)日：2002-08-06
申请号：US09972532
申请日：2001-10-05
申请人： Dustin Wood , Seng Hooi Ong , Edward A. Burton
发明人： Dustin Wood , Seng Hooi Ong , Edward A. Burton
IPC分类号： H01L2144
CPC分类号： H01L23/50 , H01L23/49822 , H01L2224/16 , H01L2924/00014 , H01L2924/01087 , H01L2924/09701 , H01L2924/10253 , H01L2924/3011 , H01L2924/00 , H01L2224/0401
摘要： Conductive planes in a power delivery region of a microelectronic package substrate are stitched to correlated conductive planes in a signal region of the substrate. The conductive planes occupy varying horizontal levels of the substrate and are stitched together at a junction between the power delivery region and the signal region of the substrate using alternating tabs connected with vias.
摘要翻译：在微电子封装基板的功率传送区域中的导电平面被缝合以在衬底的信号区域中相关的导电平面。导电平面占据基板的不同水平位置，并且使用与通孔连接的交替凸片，在功率输送区域和基板的信号区域之间的接合处缝合在一起。

8. 发明授权

US5757206A Electronic circuit with programmable gradual power consumption control 失效
标题翻译：具有可编程逐步功耗控制的电子电路
公开(公告)号：US5757206A
公开(公告)日：1998-05-26
申请号：US426442
申请日：1995-04-21
申请人： Edward A. Burton , Farrell L. Ostler
发明人： Edward A. Burton , Farrell L. Ostler
IPC分类号： G05F1/66 , G05F1/46 , H02J1/00 , H03K19/00 , H03K19/086 , H03K19/173 , H03K19/177 , H03K19/01
CPC分类号： G05F1/468 , H03K19/0016
摘要： An electronic device comprises a circuit that is provided with incrementally modifiable power consumption control means. By applying a program signal to this control means the balance between speed and power consumption is optimized. A PLA circuit considerably benefits from this architecture.
摘要翻译：一种电子设备包括一个电路，该电路具有递增可修改的功耗控制装置。通过将程序信号应用于该控制装置，可以优化速度和功耗之间的平衡。 PLA电路相当受益于此架构。

9. 发明授权

US5329178A Integrated circuit device with user-programmable conditional power-down means 失效
标题翻译：具有用户可编程条件断电功能的集成电路器件
公开(公告)号：US5329178A
公开(公告)日：1994-07-12
申请号：US799499
申请日：1991-11-27
申请人： Edward A. Burton
发明人： Edward A. Burton
IPC分类号： H02J1/00 , H03K19/00 , H03K19/173 , H03K19/177
CPC分类号： H03K19/0016
摘要： An integrated circuit device is provided with user-programmable power-down means for disabling a particular circuit in the device under control of a user-specified state of an input signal supplied to the device. In particular, for PLDs a power-down feature of this kind is simple to implement, requiring no additional I/O pins on the device, considerably reduces power consumption and renders the device more versatile than prior art devices.
摘要翻译：集成电路装置具有用户可编程的掉电装置，用于在被提供给装置的输入信号的用户指定状态的控制下禁用装置中的特定电路。特别地，对于PLD，这种掉电功能易于实现，不需要设备上的额外I / O引脚，大大降低了功耗，并使器件比现有技术的器件更加通用。

10. 发明授权

US5155387A Circuit suitable for differential multiplexers and logic gates utilizing bipolar and field-effect transistors 失效
标题翻译：电路适用于采用双极型和场效应晶体管的差分复用器和逻辑门
公开(公告)号：US5155387A
公开(公告)日：1992-10-13
申请号：US727811
申请日：1991-07-08
申请人： Thomas D. Fletcher , Edward A. Burton
发明人： Thomas D. Fletcher , Edward A. Burton
IPC分类号： G06F7/50 , G06F7/503 , H03K17/693 , H03K19/0944 , H03K19/21
CPC分类号： G06F7/503 , H03K17/693 , H03K19/09448 , H03K19/21
摘要： A circuit employable as a differential multiplexer (10, 310, or 610) or as a differential logic gate (110, 210, 250, 410, or 510) of either the OR/NOR or EXCLUSIVE OR/EXCLUSIVE NOR type contains four pass gates that operate on four circuit input signals and are controlled by two additional circuit input signals. Two of the pass gates drive a bipolar transistor serially coupled to a first FET driven from the other two pass gates. Likewise, the second pair of pass gates drive another bipolar transistor serially coupled to another FET driven from the first pair of pass gates. The bipolar transistors supply respective circuit output signals. The two FETs are of a first polarity. The circuit preferably includes a pair of FETs of a second polarity opposite to the first polarity. The second pair of FETs are arranged so as to provide output pull-up/pull-down assistance for the bipolar transistors.
摘要翻译： OR / NOR或EXCLUSIVE OR / EXCLUSIVE NOR类型的可用作差分多路复用器（10,310或610）或差分逻辑门（110,210,250,410或510）的电路包含四通道其操作在四个电路输入信号上，并由两个额外的电路输入信号控制。两个通路驱动双极晶体管串联耦合到从另外两个通过栅极驱动的第一FET。类似地，第二对通孔驱动另一双极晶体管串联耦合到从第一对通孔驱动的另一个FET。双极晶体管提供相应的电路输出信号。两个FET是第一极性。电路优选地包括与第一极性相反的第二极性的一对FET。第二对FET被布置成为双极晶体管提供输出上拉/下拉辅助。

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