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1. 发明授权

US6009505A System and method for routing one operand to arithmetic logic units from fixed register slots and another operand from any register slot 失效
标题翻译：将一个操作数从固定寄存器时隙和另一个操作数从任何寄存器时隙路由到算术逻辑单元的系统和方法
公开(公告)号：US6009505A
公开(公告)日：1999-12-28
申请号：US759046
申请日：1996-12-02
申请人： John S. Thayer , Gary W. Thome , Brian E. Longhenry , John G. Favor , Frederick D. Weber
发明人： John S. Thayer , Gary W. Thome , Brian E. Longhenry , John G. Favor , Frederick D. Weber
IPC分类号： G06F9/30 , G06F9/302 , G06F9/312 , G06F9/315 , G06F17/16
CPC分类号： G06F9/30014 , G06F9/30032 , G06F9/30036 , G06F9/30043 , G06F9/30109 , G06F9/3877
摘要： A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local CPU bus to a conventional processor. The MEU employs vector registers, a vector ALU, and an operand routing unit (ORU) to perform a maximum number of the multimedia operations within as few instruction cycles as possible. Complex algorithms are readily performed by arranging operands upon the vector ALU in accordance with the desired algorithm flowgraph. The ORU aligns the operands within partitioned slots or sub-slots of the vector registers using vector instructions unique to the MEU. At the output of the ORU, operand pairs from vector source or destination registers can be easily routed and combined at the vector ALU. The vector instructions employ special load/store instructions in combination with numerous operational instructions to carry out concurrent multimedia operations on the aligned operands. In one embodiment, multiple ALUs may each receive one operand from a fixed source register slot location, where the fixed slot location may be different for each ALU. The operand routing may provide another operand from any source register slot location for another input to each respective ALU.
摘要翻译：提供多媒体扩展单元（MEU）用于执行各种多媒体类型操作。 MEU可以通过协处理器总线或本地CPU总线耦合到常规处理器。 MEU使用向量寄存器，向量ALU和操作数路由单元（ORU）来尽可能少地执行多媒体操作。通过根据期望的算法流程图将操作数布置在向量ALU上来容易地执行复杂算法。 ORU使用MAU特有的向量指令对齐向量寄存器的分区插槽或子时隙内的操作数。在ORU的输出端，矢量源或目标寄存器的操作数对可以很容易地在矢量ALU中路由和组合。向量指令采用特殊的加载/存储指令与许多操作指令相结合，对对齐的操作数执行并发的多媒体操作。在一个实施例中，多个ALU可以从固定的源寄存器时隙位置接收一个操作数，其中固定时隙位置对于每个ALU可以是不同的。操作数路由可以从任何源寄存器时隙位置提供另一个操作数，用于另一个输入到每个相应的ALU。

2. 发明授权

US6154831A Decoding operands for multimedia applications instruction coded with less number of bits than combination of register slots and selectable specific values 有权
标题翻译：解码多媒体应用程序的操作数，编码的位数少于寄存器时隙组合和可选择的特定值
公开(公告)号：US6154831A
公开(公告)日：2000-11-28
申请号：US296356
申请日：1999-04-22
申请人： John S. Thayer , Gary W. Thome , John G. Favor , Frederick D. Weber
发明人： John S. Thayer , Gary W. Thome , John G. Favor , Frederick D. Weber
IPC分类号： G06F9/30 , G06F9/302 , G06F9/312 , G06F9/318 , G06F9/38 , G06F9/34
CPC分类号： G06F9/3885 , G06F9/30014 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30043 , G06F9/30109 , G06F9/30112 , G06F9/3012 , G06F9/3013 , G06F9/3824
摘要： A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local CPU bus to a conventional processor. The MEU employs vector registers, a vector ALU, and an operand routing unit (ORU) to perform a maximum number of the multimedia operations within as few instruction cycles as possible. Complex algorithms are readily performed by arranging operands upon the vector ALU in accordance with the desired algorithm flowgraph. The ORU aligns the operands within partitioned slots or sub-slots of the vector registers using vector instructions unique to the MEU. At the output of the ORU, operand pairs from vector source or destination registers can be easily routed and combined at the vector ALU. The MEU may include a plurality of ALUs, registers partitioned into slots, and a decode unit for decoding an instruction specifying operands from any slot from one register and from a fixed slot of another register as well as different operations to be performed by the ALUs on the operands.
摘要翻译：提供多媒体扩展单元（MEU）用于执行各种多媒体类型操作。 MEU可以通过协处理器总线或本地CPU总线耦合到常规处理器。 MEU使用向量寄存器，向量ALU和操作数路由单元（ORU）来尽可能少地执行多媒体操作。通过根据期望的算法流程图将操作数布置在向量ALU上来容易地执行复杂算法。 ORU使用MAU特有的向量指令对齐向量寄存器的分区插槽或子时隙内的操作数。在ORU的输出端，矢量源或目标寄存器的操作数对可以很容易地在矢量ALU中路由和组合。 MEU可以包括多个ALU，被划分成时隙的寄存器，以及解码单元，用于对来自一个寄存器和另一个寄存器的固定时隙的任何时隙指定操作数的指令进行解码，以及由ALU执行的不同操作操作数。

3. 发明授权

US6061521A Computer having multimedia operations executable as two distinct sets of operations within a single instruction cycle 失效
标题翻译：具有多媒体操作的计算机在单个指令周期内可执行为两组不同的操作
公开(公告)号：US6061521A
公开(公告)日：2000-05-09
申请号：US759042
申请日：1996-12-02
申请人： John S. Thayer , Gary W. Thome , John G. Favor , Frederick D. Weber
发明人： John S. Thayer , Gary W. Thome , John G. Favor , Frederick D. Weber
IPC分类号： G06F9/30 , G06F9/302 , G06F9/312 , G06F9/318 , G06F9/38
CPC分类号： G06F9/3885 , G06F9/30014 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30043 , G06F9/30109 , G06F9/30112 , G06F9/3012 , G06F9/3013 , G06F9/3824
摘要： A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU may be coupled either through a coprocessor bus or a local CPU bus to a conventional processor. The MEU employs vector registers, a vector ALU, and an operand routing unit (ORU) to perform a maximum number of the multimedia operations within as few instruction cycles as possible. Complex algorithms are readily performed by arranging operands upon the vector ALU in accordance with the desired algorithm flowgraph. The ORU aligns the operands within partitioned slots or sub-slots of the vector registers using vector instructions unique to the MEU. At the output of the ORU, operand pairs from vector source or destination registers may be easily routed and combined at the vector ALU. The vector instructions employ special load/store instructions in combination with numerous operational instructions to carry out concurrent multimedia operations on the aligned operands. In one embodiment, an arithmetic logic unit may be partitioned into at least two logic portions. A first logic portion may be coupled to receive a first operand from a fixed slot of a first register and a second operand from any slot of a second register. A second logic portion may be coupled to receive a third operand from a fixed slot of the first register and a fourth operand from any slot of the second register. The first logic portion may perform an arithmetic operation dissimilar from the second logic portion.
摘要翻译：提供多媒体扩展单元（MEU）用于执行各种多媒体类型操作。 MEU可以通过协处理器总线或本地CPU总线耦合到常规处理器。 MEU使用向量寄存器，向量ALU和操作数路由单元（ORU）来尽可能少地执行多媒体操作。通过根据期望的算法流程图将操作数布置在向量ALU上来容易地执行复杂算法。 ORU使用MAU特有的向量指令对齐向量寄存器的分区插槽或子时隙内的操作数。在ORU的输出端，矢量源或目标寄存器的操作数对可以很容易地路由和组合在矢量ALU。向量指令采用特殊的加载/存储指令与许多操作指令相结合，对对齐的操作数执行并发的多媒体操作。在一个实施例中，算术逻辑单元可以被划分为至少两个逻辑部分。第一逻辑部分可以被耦合以从第二寄存器的任何时隙的第一寄存器的固定时隙和第二操作数接收第一操作数。第二逻辑部分可以被耦合以从第一寄存器的固定时隙接收第三操作数，并从第二寄存器的任何时隙接收第四操作数。第一逻辑部分可以执行与第二逻辑部分不同的算术运算。

4. 发明授权

US5909572A System and method for conditionally moving an operand from a source register to a destination register 失效
标题翻译：用于有条件地将操作数从源寄存器移动到目标寄存器的系统和方法
公开(公告)号：US5909572A
公开(公告)日：1999-06-01
申请号：US759025
申请日：1996-12-02
申请人： John S. Thayer , John G. Favor , Frederick D. Weber
发明人： John S. Thayer , John G. Favor , Frederick D. Weber
IPC分类号： G06F9/30 , G06F9/302 , G06F9/312 , G06F9/315 , G06F9/38 , G06F9/00
CPC分类号： G06F9/30072 , G06F9/30014 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30043 , G06F9/30109 , G06F9/30163 , G06F9/30167 , G06F9/3885 , G06F9/3887
摘要： A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local CPU bus to a conventional processor. The MEU employs vector registers, a vector ALU, and an operand routing unit (ORU) to perform a maximum number of the multimedia operations within as few instruction cycles as possible. Complex algorithms are readily performed by arranging operands upon the vector ALU in accordance with the desired algorithm flowgraph. The ORU aligns the operands within partitioned slots or sub-slots of the vector registers using vector instructions unique to the MEU. At the output of the ORU, operand pairs from vector source or destination registers can be easily routed and combined at the vector ALU. The vector instructions employ special load/store instructions in combination with numerous operational instructions to carry out concurrent multimedia operations on the aligned operands.
摘要翻译：提供多媒体扩展单元（MEU）用于执行各种多媒体类型操作。 MEU可以通过协处理器总线或本地CPU总线耦合到常规处理器。 MEU使用向量寄存器，向量ALU和操作数路由单元（ORU）来尽可能少地执行多媒体操作。通过根据期望的算法流程图将操作数布置在向量ALU上来容易地执行复杂算法。 ORU使用MAU特有的向量指令对齐向量寄存器的分区插槽或子时隙内的操作数。在ORU的输出端，矢量源或目标寄存器的操作数对可以很容易地路由和组合在矢量ALU。向量指令采用特殊的加载/存储指令与许多操作指令相结合，对对齐的操作数执行并发的多媒体操作。

5. 发明授权

US06173366B2 Load and store instructions which perform unpacking and packing of data bits in separate vector and integer cache storage 失效
标题翻译：加载和存储在单独的向量和整数高速缓存存储中执行数据位的解包和打包的指令
公开(公告)号：US06173366B2
公开(公告)日：2001-01-09
申请号：US08759044
申请日：1996-12-02
申请人： John S. Thayer , John G. Favor , Frederick D. Weber
发明人： John S. Thayer , John G. Favor , Frederick D. Weber
IPC分类号： G06F1204
CPC分类号： G06F9/30014 , G06F9/30025 , G06F9/30036 , G06F9/30043 , G06F9/30109 , G06F9/30112 , G06F9/3013 , G06F12/0875 , H04N19/42 , H04N19/61
摘要： A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local CPU bus to a conventional processor. The MEU employs vector registers, a vector ALU, and an operand routing unit (ORU) to perform a maximum number of the multimedia operations within as few instruction cycles as possible. Complex algorithms are readily performed by arranging operands upon the vector ALU in accordance with the desired algorithm flowgraph. The ORU aligns the operands within partitioned slots or sub-slots of the vector registers using vector instructions unique to the MEU. At the output of the ORU, operand pairs from vector source or destination registers can be easily routed and combined at the vector ALU. The vector instructions employ special load/store instructions in combination with numerous operational instructions to carry out concurrent multimedia operations on the aligned operands.
摘要翻译：提供多媒体扩展单元（MEU）用于执行各种多媒体类型操作。 MEU可以通过协处理器总线或本地CPU总线耦合到常规处理器。 MEU使用向量寄存器，向量ALU和操作数路由单元（ORU）来尽可能少地执行多媒体操作。通过根据期望的算法流程图将操作数布置在向量ALU上来容易地执行复杂算法。 ORU使用MAU特有的向量指令对齐向量寄存器的分区插槽或子时隙内的操作数。在ORU的输出端，矢量源或目标寄存器的操作数对可以很容易地在矢量ALU中路由和组合。向量指令采用特殊的加载/存储指令与许多操作指令相结合，对对齐的操作数执行并发的多媒体操作。

6. 发明授权

US06047372A Apparatus for routing one operand to an arithmetic logic unit from a fixed register slot and another operand from any register slot 有权
标题翻译：用于从固定寄存器时隙将一个操作数路由到算术逻辑单元的装置，以及来自任何寄存器时隙的另一个操作数的装置
公开(公告)号：US06047372A
公开(公告)日：2000-04-04
申请号：US290837
申请日：1999-04-13
申请人： John S. Thayer , Brian E. Longhenry , John G. Favor , Frederick D. Weber
发明人： John S. Thayer , Brian E. Longhenry , John G. Favor , Frederick D. Weber
IPC分类号： G06F9/30 , G06F9/302 , G06F9/312 , G06F9/315 , G06F7/00
CPC分类号： G06F9/30014 , G06F9/30032 , G06F9/30036 , G06F9/30043 , G06F9/30109 , G06F9/3877
摘要： A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local CPU bus to a conventional processor. The MEU employs vector registers, a vector ALU, and an operand routing unit (ORU) to perform a maximum number of the multimedia operations within as few instruction cycles as possible. Complex algorithms are readily performed by arranging operands upon the vector ALU in accordance with the desired algorithm flowgraph. The ORU aligns the operands within partitioned slots or sub-slots of the vector registers using vector instructions unique to the MEU. At the output of the ORU, operand pairs from vector source or destination registers can be easily routed and combined at the vector ALU. The vector instructions employ special load/store instructions in combination with numerous operational instructions to carry out concurrent multimedia operations on the aligned operands. In one embodiment multiple ALUs may each receive one operand from a fixed source register slot location, where the fixed slot location may be different for each ALU. The operand routing may provide another operand from any source register slot location for another input to each respective ALU.
摘要翻译：提供多媒体扩展单元（MEU）用于执行各种多媒体类型操作。 MEU可以通过协处理器总线或本地CPU总线耦合到常规处理器。 MEU使用向量寄存器，向量ALU和操作数路由单元（ORU）来尽可能少地执行多媒体操作。通过根据期望的算法流程图将操作数布置在向量ALU上来容易地执行复杂算法。 ORU使用MAU特有的向量指令对齐向量寄存器的分区插槽或子时隙内的操作数。在ORU的输出端，矢量源或目标寄存器的操作数对可以很容易地在矢量ALU中路由和组合。向量指令采用特殊的加载/存储指令与许多操作指令相结合，对对齐的操作数执行并发的多媒体操作。在一个实施例中，多个ALU可以从固定的源寄存器时隙位置接收一个操作数，其中固定的时隙位置对于每个ALU可以是不同的。操作数路由可以从任何源寄存器时隙位置提供另一个操作数，用于另一个输入到每个相应的ALU。

7. 发明授权

US5801975A Computer modified to perform inverse discrete cosine transform operations on a one-dimensional matrix of numbers within a minimal number of instruction cycles 失效
标题翻译：计算机被修改为对最小数量的指令周期内的数字的一维矩阵执行逆离散余弦变换操作
公开(公告)号：US5801975A
公开(公告)日：1998-09-01
申请号：US759045
申请日：1996-12-02
申请人： John S. Thayer , John G. Favor , Frederick D. Weber
发明人： John S. Thayer , John G. Favor , Frederick D. Weber
IPC分类号： G06F17/14
CPC分类号： G06F9/30021 , G06F17/147 , G06F9/30014 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/3013 , G06F9/3885 , G06F9/3887
摘要： A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local central processing unit (CPU) bus to a conventional processor. The MEU employs vector registers, a vector arithmetic logic unit (ALU), and an operand routing unit (ORU) to perform a maximum number of the multimedia operations within as few instruction cycles as possible. Complex algorithms are readily performed by arranging operands upon the vector ALU in accordance with the desired algorithm flowgraph. The ORU aligns the operands within partitioned slots or sub-slots of the vector registers using vector instructions unique to the MEU. At the output of the ORU, operand pairs from vector source or destination registers can be easily routed and combined at the vector ALU. The vector instructions employ special load/store instructions in combination with numerous operational instructions to carry out concurrent multimedia operations on the aligned operands.
摘要翻译：提供多媒体扩展单元（MEU）用于执行各种多媒体类型操作。 MEU可以通过协处理器总线或本地中央处理单元（CPU）总线耦合到常规处理器。 MEU采用向量寄存器，向量算术逻辑单元（ALU）和操作数路由单元（ORU），以尽可能少的指令周期执行最大数量的多媒体操作。通过根据期望的算法流程图将操作数布置在向量ALU上来容易地执行复杂算法。 ORU使用MAU特有的向量指令对齐向量寄存器的分区插槽或子时隙内的操作数。在ORU的输出端，矢量源或目标寄存器的操作数对可以很容易地在矢量ALU中路由和组合。向量指令采用特殊的加载/存储指令与许多操作指令相结合，对对齐的操作数执行并发的多媒体操作。

8. 发明授权

US06298438B1 System and method for conditional moving an operand from a source register to destination register 有权
标题翻译：有条件地将操作数从源寄存器移动到目标寄存器的系统和方法
公开(公告)号：US06298438B1
公开(公告)日：2001-10-02
申请号：US09303513
申请日：1999-05-03
申请人： John S. Thayer , John G. Favor , Frederick D. Weber
发明人： John S. Thayer , John G. Favor , Frederick D. Weber
IPC分类号： G06F738
CPC分类号： G06F9/30072 , G06F9/30014 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30043 , G06F9/30109 , G06F9/30163 , G06F9/30167 , G06F9/3885 , G06F9/3887
摘要： A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local CPU bus to a conventional processor. The MEU employs vector registers, a vector ALU, and an operand routing unit (ORU) to perform a maximum number of the multimedia operations within as few instruction cycles as possible. Complex algorithms are readily performed by arranging operands upon the vector ALU in accordance with the desired algorithm flowgraph. The ORU aligns the operands within partitioned slots or sub-slots of the vector registers using vector instructions unique to the MEU. At the output of the ORU, operand pairs from vector source or destination registers can be easily routed and combined at the vector ALU. The vector instructions employ special load/store instructions in combination with numerous operational instructions to carry out concurrent multimedia operations on the aligned operands.
摘要翻译：提供多媒体扩展单元（MEU）用于执行各种多媒体类型操作。 MEU可以通过协处理器总线或本地CPU总线耦合到常规处理器。 MEU使用向量寄存器，向量ALU和操作数路由单元（ORU）来尽可能少地执行多媒体操作。通过根据期望的算法流程图将操作数布置在向量ALU上来容易地执行复杂算法。 ORU使用MAU特有的向量指令对齐向量寄存器的分区插槽或子时隙内的操作数。在ORU的输出端，矢量源或目标寄存器的操作数对可以很容易地在矢量ALU中路由和组合。向量指令采用特殊的加载/存储指令与许多操作指令相结合，对对齐的操作数执行并发的多媒体操作。

9. 发明授权

US06215504B1 Line drawing using operand routing and operation selective multimedia extension unit 失效
标题翻译：线图使用操作数路由和操作选择性多媒体扩展单元
公开(公告)号：US06215504B1
公开(公告)日：2001-04-10
申请号：US08905685
申请日：1997-08-01
申请人： Brian E. Longhenry , Gary W. Thome , John S. Thayer
发明人： Brian E. Longhenry , Gary W. Thome , John S. Thayer
IPC分类号： G06T1120
CPC分类号： G06T3/40
摘要： A routable operand and selectable operation processor multimedia extension unit is employed to draw lines in a video system using an efficient, parallel technique. A first series of integral y pixel values and error values are calculated according to Bresenham's line drawing algorithm. Then, subsequent pixels and error values are calculated in parallel based on the previously calculated values.
摘要翻译：使用可路由操作数和可选择的操作处理器多媒体扩展单元来使用有效的并行技术在视频系统中绘制线。根据Bresenham的线图算法计算第一系列积分y像素值和误差值。然后，基于先前计算的值并行计算后续像素和误差值。

10. 发明授权

US5862063A Enhanced wavetable processing technique on a vector processor having operand routing and slot selectable operations 失效
公开(公告)号：US5862063A
公开(公告)日：1999-01-19
申请号：US770346
申请日：1996-12-20
申请人： Gary W. Thome , John S. Thayer
发明人： Gary W. Thome , John S. Thayer
IPC分类号： G10H7/00 , G06F7/38 , G06F17/10
CPC分类号： G10H7/002 , G10H2210/305
摘要： An apparatus and a method for massaging audio signal perform interpolation, dynamic filtering, and panning on the audio signal represented as a matrix of input values. In the interpolation process, the input values are loaded into first and second vector registers, while fractional coefficients are loaded into a third vector register. Next, the first vector register is subtracted from the second vector register. Additionally, in a single operation, the routine performs a vector multiply operation between the second and third registers and accumulates the result of the vector multiply operation in the second register. The results are saved and the process is repeated until all input values in the matrix have been processed. In the dynamic filtering process, after the data loading step, for each slot in said vector register, the routine performs a multiply operation between the filter coefficient and the slot of the vector register and accumulates the result of the multiply operation in the slot of the second register in a single clock cycle while it retains data of the remaining slots in the vector register in the same clock cycle. The results are saved and the process is repeated until all input values in the matrix have been processed. In the stretching process, after loading data in the appropriate vector register, the routine copies the content of each slot of the vector register into consecutive pair of slots on a second vector register and when the second vector register is full, copies the content of each of the remaining slots in the first vector register into consecutive pairs of slots on a third register. In the panning process, the routine performs a vector multiply operation between the first vector register and a coefficient vector register for each slot in the first vector register. This vector multiply operation is preferably a 32-bit vector multiply operation which is broken down into a low order extended precision multiply accumulate operation and a high order extended precision multiply accumulate operation.

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