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1. 发明授权

US07374987B2 Stress inducing spacers 有权
标题翻译：应力诱导垫片
公开(公告)号：US07374987B2
公开(公告)日：2008-05-20
申请号：US10935136
申请日：2004-09-07
申请人： Dureseti Chidambarrao , Omer H. Dokumaci , Bruce B. Doris , Jack A. Mandelman , Xavier Baie
发明人： Dureseti Chidambarrao , Omer H. Dokumaci , Bruce B. Doris , Jack A. Mandelman , Xavier Baie
IPC分类号： H01L21/336
CPC分类号： H01L29/6656 , H01L21/823807 , H01L21/823864 , H01L21/84 , H01L27/1203 , H01L29/42316 , H01L29/7842 , H01L29/7843 , H01L29/808
摘要： A substrate under tension and/or compression improves performance of devices fabricated therein. Tension and/or compression can be imposed on a substrate through selection of appropriate gate sidewall spacer material disposed above a device channel region wherein the spacers are formed adjacent both the gate and the substrate and impose forces on adjacent substrate areas. Another embodiment comprises compressive stresses imposed in the plane of the channel using SOI sidewall spacers made of polysilicon that is expanded by oxidation. The substrate areas under compression or tension exhibit charge mobility characteristics different from those of a non-stressed substrate. By controllably varying these stresses within NFET and PFET devices formed on a substrate, improvements in IC performance have been demonstrated.
摘要翻译：在张力和/或压缩下的基底改善了在其中制造的器件的性能。可以通过选择设置在器件沟道区域上方的适当的栅极侧壁间隔物施加张力和/或压缩，其中间隔物邻近栅极和衬底形成，并且在邻近衬底区域上施加力。另一个实施例包括使用通过氧化扩展的多晶硅制成的SOI侧壁间隔施加在沟道的平面中的压应力。在压缩或张力下的衬底区域表现出不同于非应力衬底的电荷迁移率特性。通过可控地改变在衬底上形成的NFET和PFET器件内的这些应力，已经证明了IC性能的提高。

2. 发明授权

US06974981B2 Isolation structures for imposing stress patterns 有权
标题翻译：施加应力模式的隔离结构
公开(公告)号：US06974981B2
公开(公告)日：2005-12-13
申请号：US10318600
申请日：2002-12-12
申请人： Dureseti Chidambarrao , Omer H. Dokumaci , Bruce B. Doris , Jack A. Mandelman
发明人： Dureseti Chidambarrao , Omer H. Dokumaci , Bruce B. Doris , Jack A. Mandelman
IPC分类号： H01L21/76 , H01L21/762 , H01L21/8238 , H01L29/80 , H01L31/109 , H01L31/112 , H01L29/774
CPC分类号： H01L29/7846 , H01L21/76232 , H01L21/823807 , H01L21/823878 , H01L29/785
摘要： A substrate under tension and/or compression improves performance of devices fabricated therein. Tension and/or compression can be imposed on a substrate through selection of appropriate STI fill material. The STI regions are formed in the substrate layer and impose forces on adjacent substrate areas. The substrate areas under compression or tension exhibit charge mobility characteristics different from those of a non-stressed substrate. By controllably varying these stresses within NFET and PFET devices formed on a substrate, improvements in IC performance are achieved.
摘要翻译：在张力和/或压缩下的基底改善了在其中制造的器件的性能。可以通过选择适当的STI填充材料将张力和/或压缩施加在基底上。 STI区域形成在衬底层中并且在相邻衬底区域上施加力。在压缩或张力下的衬底区域表现出不同于非应力衬底的电荷迁移率特性。通过可控地改变在衬底上形成的NFET和PFET器件内的这些应力，实现了IC性能的提高。

3. 发明授权

US06825529B2 Stress inducing spacers 有权
标题翻译：应力诱导垫片
公开(公告)号：US06825529B2
公开(公告)日：2004-11-30
申请号：US10318602
申请日：2002-12-12
申请人： Dureseti Chidambarrao , Omer H. Dokumaci , Bruce B. Doris , Jack A. Mandelman , Xavier Baie
发明人： Dureseti Chidambarrao , Omer H. Dokumaci , Bruce B. Doris , Jack A. Mandelman , Xavier Baie
IPC分类号： H01L2976
CPC分类号： H01L29/6656 , H01L21/823807 , H01L21/823864 , H01L21/84 , H01L27/1203 , H01L29/42316 , H01L29/7842 , H01L29/7843 , H01L29/808
摘要： A substrate under tension and/or compression improves performance of devices fabricated therein. Tension and/or compression can be imposed on a substrate through selection of appropriate gate sidewall spacer material disposed above a device channel region wherein the spacers are formed adjacent both the gate and the substrate and impose forces on adjacent substrate areas. Another embodiment comprises compressive stresses imposed in the plane of the channel using SOI sidewall spacers made of polysilicon that is expanded by oxidation. The substrate areas under compression or tension exhibit charge mobility characteristics different from those of a non-stressed substrate. By controllably varying these stresses within NFET and PFET devices formed on a substrate, improvements in IC performance have been demonstrated.
摘要翻译：在张力和/或压缩下的基底改善了在其中制造的器件的性能。可以通过选择设置在器件沟道区域上方的适当的栅极侧壁间隔物施加张力和/或压缩，其中间隔物邻近栅极和衬底形成，并且在邻近衬底区域上施加力。另一个实施例包括使用通过氧化扩展的多晶硅制成的SOI侧壁间隔施加在沟道的平面中的压应力。在压缩或张力下的衬底区域表现出不同于非应力衬底的电荷迁移率特性。通过可控地改变在衬底上形成的NFET和PFET器件内的这些应力，已经证明了IC性能的提高。

4. 发明授权

US06878582B2 Low-GIDL MOSFET structure and method for fabrication 失效
公开(公告)号：US06878582B2
公开(公告)日：2005-04-12
申请号：US10876873
申请日：2004-06-25
申请人： Omer H. Dokumaci , Bruce B. Doris , Oleg Gluschenkov , Jack A. Mandelman , Carl J. Radens
发明人： Omer H. Dokumaci , Bruce B. Doris , Oleg Gluschenkov , Jack A. Mandelman , Carl J. Radens
IPC分类号： H01L21/265 , H01L21/28 , H01L21/336 , H01L29/49 , H01L29/78 , H01L21/8238
CPC分类号： H01L29/4983 , H01L21/26586 , H01L21/28105 , H01L29/66484 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7831 , H01L29/7836 , Y10S257/90
摘要： A low-GIDL current MOSFET device structure and a method of fabrication thereof which provides a low-GIDL current. The MOSFET device structure contains a central gate conductor whose edges may slightly overlap the source/drain diffusions, and left and right side wing gate conductors which are separated from the central gate conductor by a thin insulating and diffusion barrier layer.

5. 发明授权

US06780694B2 MOS transistor 有权
标题翻译： MOS晶体管
公开(公告)号：US06780694B2
公开(公告)日：2004-08-24
申请号：US10338930
申请日：2003-01-08
申请人： Bruce B. Doris , Omer H. Dokumaci , Jack A. Mandelman , Carl J. Radens
发明人： Bruce B. Doris , Omer H. Dokumaci , Jack A. Mandelman , Carl J. Radens
IPC分类号： H01L21338
CPC分类号： H01L21/28114 , H01L21/26586 , H01L21/82385 , H01L21/823864 , H01L29/42376 , H01L29/665
摘要： A method of fabricating a semiconductor transistor device comprises the steps as follows. Provide a semiconductor substrate with a gate dielectric layer thereover and a lower gate electrode structure formed over the gate dielectric layer with the lower gate electrode structure having a lower gate top. Form a planarizing layer over the gate dielectric layer leaving the gate top of the lower gate electrode structure exposed. Form an upper gate structure over the lower gate electrode structure to form a T-shaped gate electrode with an exposed lower surface of the upper gate surface and exposed vertical sidewalls of the gate electrode. Remove the planarizing layer. Form source/drain extensions in the substrate protected from the short channel effect. Form sidewall spacers adjacent to the exposed lower surface of the upper gate and the exposed vertical sidewalls of the T-shaped gate electrode. Form source/drain regions in the substrate. Form silicide layers on top of the T-shaped gate electrode and above the source/drain regions.
摘要翻译：制造半导体晶体管器件的方法包括以下步骤。提供其上具有栅极介电层的半导体衬底和形成在栅极电介质层上的下部栅极电极结构，而下部栅电极结构具有较低的栅极顶部。在栅极电介质层上形成平坦化层，离开下部栅电极结构的栅极顶部。在下栅极电极结构上形成上栅极结构，形成具有上栅极表面的暴露下表面和暴露的栅电极垂直侧壁的T形栅电极。取出平坦化层。衬底中形成源/漏极扩展，防止短沟道效应。形成邻近上部栅极的暴露的下表面和T形栅电极的暴露的垂直侧壁的侧壁间隔物。在衬底中形成源/漏区。在T形栅电极的顶部和源极/漏极区之上形成硅化物层。

6. 发明授权

US06806534B2 Damascene method for improved MOS transistor 失效
标题翻译：改进MOS晶体管的镶嵌方法
公开(公告)号：US06806534B2
公开(公告)日：2004-10-19
申请号：US10342423
申请日：2003-01-14
申请人： Omer H. Dokumaci , Bruce B. Doris , Oleg Gluschenkov , Jack A. Mandelman , Carl J. Radens
发明人： Omer H. Dokumaci , Bruce B. Doris , Oleg Gluschenkov , Jack A. Mandelman , Carl J. Radens
IPC分类号： H01L2976
CPC分类号： H01L29/66583 , H01L21/26586 , H01L21/28114 , H01L29/665 , H01L29/66553
摘要： A MOSFET fabrication methodology and device structure, exhibiting improved gate activation characteristics. The gate doping that may be introduced while the source drain regions are protected by a damascene mandrel to allow for a very high doping in the gate conductors, without excessively forming deep source/drain diffusions. The high gate conductor doping minimizes the effects of electrical depletion of carriers in the gate conductor. The MOSFET fabrication methodology and device structure further results in a device having a lower gate conductor width less than the minimum lithographic minimum image, and a wider upper gate conductor portion width which may be greater than the minimum lithographic image. Since the effective channel length of the MOSFET is defined by the length of the lower gate portion, and the line resistance is determined by the width of the upper gate portion, both short channel performance and low gate resistance are satisfied simultaneously.
摘要翻译： MOSFET制造方法和器件结构，表现出改进的栅极激活特性。当源极漏极区域被镶嵌心轴保护以允许栅极导体中的非常高的掺杂而不会过度地形成深的源极/漏极扩散时，可以引入栅极掺杂。高栅极导体掺杂最大限度地减小了栅极导体中载流子的电耗损的影响。 MOSFET制造方法和器件结构进一步导致具有小于最小光刻最小图像的较低栅极导体宽度的器件，以及可能大于最小光刻图像的较宽上部栅极导体部分宽度。由于MOSFET的有效沟道长度由下栅极部分的长度限定，并且线路电阻由上部栅极部分的宽度决定，所以同时满足短沟道性能和低栅极电阻。

7. 发明授权

US06841826B2 Low-GIDL MOSFET structure and method for fabrication 有权
标题翻译：低GIDL MOSFET结构及其制造方法
公开(公告)号：US06841826B2
公开(公告)日：2005-01-11
申请号：US10345472
申请日：2003-01-15
申请人： Omer H. Dokumaci , Bruce B. Doris , Oleg Gluschenkov , Jack A. Mandelman , Carl J. Radens
发明人： Omer H. Dokumaci , Bruce B. Doris , Oleg Gluschenkov , Jack A. Mandelman , Carl J. Radens
IPC分类号： H01L21/265 , H01L21/28 , H01L21/336 , H01L29/49 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062
CPC分类号： H01L29/4983 , H01L21/26586 , H01L21/28105 , H01L29/66484 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7831 , H01L29/7836 , Y10S257/90
摘要： A low-GIDL current MOSFET device structure and a method of fabrication thereof which provides a low-GIDL current. The MOSFET device structure contains a central gate conductor whose edges may slightly overlap the source/drain diffusions, and left and right side wing gate conductors which are separated from the central gate conductor by a thin insulating and diffusion barrier layer.
摘要翻译：低GIDL电流MOSFET器件结构及其制造方法，其提供低GIDL电流。 MOSFET器件结构包含中心栅极导体，其边缘可能与源极/漏极扩散稍微重叠，以及通过薄的绝缘和扩散阻挡层与中心栅极导体分离的左侧和右侧翼栅极导体。

8. 发明授权

US06717216B1 SOI based field effect transistor having a compressive film in undercut area under the channel and a method of making the device 有权
标题翻译：基于SOI的场效应晶体管在通道下方的底切区域具有压缩膜，以及制造该器件的方法
公开(公告)号：US06717216B1
公开(公告)日：2004-04-06
申请号：US10318601
申请日：2002-12-12
申请人： Bruce B. Doris , Dureseti Chidambarrao , Xavier Baie , Jack A. Mandelman , Devendra K. Sadana , Dominic J. Schepis
发明人： Bruce B. Doris , Dureseti Chidambarrao , Xavier Baie , Jack A. Mandelman , Devendra K. Sadana , Dominic J. Schepis
IPC分类号： H01L2701
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/66772 , H01L29/7842 , H01L29/78603 , H01L29/78696
摘要： Field effect transistor with increased charge carrier mobility due to stress in the current channel 22. The stress is in the direction of current flow (longitudinal). In PFET devices, the stress is compressive; in NFET devices, the stress is tensile. The stress is created by a compressive film 34 in an area 32 under the channel. The compressive film pushes up on the channel 22, causing it to bend. In PFET devices, the compressive film is disposed under ends 31 of the channel (e.g. under the source and drain), thereby causing compression in an upper portion 22A of the channel. In NFET devices, the compressive film is disposed under a middle portion 40 of the channel (e.g. under the gate), thereby causing tension in the, upper portion of the channel. Therefore, both NFET and PFET devices can be enhanced. A method for making the devices is included.
摘要翻译：场效应晶体管由于电流通道22中的应力而具有增加的电荷载流子迁移率。应力在电流方向（纵向）。在PFET器件中，应力是压缩的; 在NFET器件中，应力为拉伸。应力由通道下的区域32中的压缩膜34产生。压缩膜在通道22上向上推动，使其弯曲。在PFET器件中，压缩膜设置在通道的端部31（例如在源极和漏极下），从而在通道的上部22A中引起压缩。在NFET器件中，压缩膜设置在通道的中间部分40（例如在栅极下），从而在通道的上部产生张力。因此，可以增强NFET和PFET器件。包括制造装置的方法。

9. 发明授权

US07388259B2 Strained finFET CMOS device structures 有权
标题翻译：应变finFET CMOS器件结构
公开(公告)号：US07388259B2
公开(公告)日：2008-06-17
申请号：US10536483
申请日：2002-11-25
申请人： Bruce B. Doris , Dureseti Chidambarrao , MeiKei Ieong , Jack A. Mandelman
发明人： Bruce B. Doris , Dureseti Chidambarrao , MeiKei Ieong , Jack A. Mandelman
IPC分类号： H01L29/94
CPC分类号： H01L27/1203 , H01L21/84 , H01L29/7843 , H01L29/785
摘要： A semiconductor device structure, includes a PMOS device 200 and an NMOS device 300 disposed on a substrate 1,2, the PMOS device including a compressive layer 6 stressing an active region of the PMOS device, the NMOS device including a tensile layer 9 stressing an active region of the NMOS device, wherein the compressive layer includes a first dielectric material, the tensile layer includes a second dielectric material, and the PMOS and NMOS devices are FinFET devices 200, 300.
摘要翻译：半导体器件结构包括PMOS器件200和设置在衬底1,2上的NMOS器件300，PMOS器件包括压迫PMOS器件的有源区的压缩层6，NMOS器件包括拉伸层9，所述NMOS器件的有源区，其中所述压缩层包括第一介电材料，所述拉伸层包括第二介电材料，并且所述PMOS和NMOS器件为FinFET器件200,300。

10. 发明授权

US06884667B1 Field effect transistor with stressed channel and method for making same 失效
标题翻译：具有应力通道的场效应晶体管及其制造方法
公开(公告)号：US06884667B1
公开(公告)日：2005-04-26
申请号：US10669727
申请日：2003-09-25
申请人： Bruce B. Doris , Dureseti Chidambarrao , Xavier Baie , Jack A. Mandelman , Devendra K. Sadana , Dominic J. Schepis
发明人： Bruce B. Doris , Dureseti Chidambarrao , Xavier Baie , Jack A. Mandelman , Devendra K. Sadana , Dominic J. Schepis
IPC分类号： H01L27/08 , H01L21/336 , H01L21/8238 , H01L21/84 , H01L27/092 , H01L27/12 , H01L29/78 , H01L29/786 , H01L21/00
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/66772 , H01L29/7842 , H01L29/78603 , H01L29/78696
摘要： Field effect transistor with increased charge carrier mobility due to stress in the current channel 22. The stress is in the direction of current flow (longitudinal). In PFET device, the stress is compressive; in NFET devices, the stress is tensile. The stress is created by a compressive film 34 in an area 32 under the channel. The compressive film pushes up on the channel 22, causing it to bend. In PFET devices, the compressive film is disposed under ends 31 of the channel (e.g. under the source and drain), thereby causing compression in an upper portion 22A of the channel. In NFET devices, the compressive film is disposed under a middle portion 40 of the channel (e.g. under the gate), thereby causing tension in the, upper portion of the channel. Therefore, both NFET and PFET device can be enhanced. A method for making the devices is included.
摘要翻译：场效应晶体管由于电流通道22中的应力而具有增加的电荷载流子迁移率。应力在电流方向（纵向）。在PFET器件中，应力是压缩的; 在NFET器件中，应力为拉伸。应力由通道下的区域32中的压缩膜34产生。压缩膜在通道22上向上推动，使其弯曲。在PFET器件中，压缩膜设置在通道的端部31（例如在源极和漏极之下），从而在通道的上部22A中引起压缩。在NFET器件中，压缩膜设置在通道的中间部分40（例如在栅极下），从而在通道的上部产生张力。因此，可以增强NFET和PFET器件。包括制造装置的方法。

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