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1. 发明申请

US20110012177A1 Nanostructure For Changing Electric Mobility 审中-公开
标题翻译：改变电动移动的纳米结构
公开(公告)号：US20110012177A1
公开(公告)日：2011-01-20
申请号：US12505603
申请日：2009-07-20
申请人： Dureseti Chidambarrao , Oki Gunawan , Xiao Hu Liu , Amlan Majumdar , Lidija Sekaric , Jeffrey W. Sleight
发明人： Dureseti Chidambarrao , Oki Gunawan , Xiao Hu Liu , Amlan Majumdar , Lidija Sekaric , Jeffrey W. Sleight
IPC分类号： H01L29/775 , H01L21/335
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/775 , H01L29/7843
摘要： A structure and a method for a semiconductor including a nanostructure semiconductor channel. The semiconductor may include a dielectric and an electrode, the electrode attached to the dielectric, a semiconductor channel may be disposed proximate to the dielectric, wherein the semiconductor channel has an electric mobility and is configured to have at least one dimension, and wherein the dielectric may be configured to apply a force at the at least one dimension.
摘要翻译：一种包括纳米结构半导体通道的半导体的结构和方法。半导体可以包括电介质和电极，附着到电介质的电极，半导体沟道可以靠近电介质设置，其中半导体沟道具有电迁移率，并且被配置为具有至少一个维度，并且其中电介质可以被配置为在至少一个维度施加力。

2. 发明申请

US20100295020A1 Method For Forming A Robust Top-Down Silicon Nanowire Structure Using A Conformal Nitride And Such Structure 有权
标题翻译：使用保形氮化物和这种结构形成坚固的自上而下的硅纳米线结构的方法
公开(公告)号：US20100295020A1
公开(公告)日：2010-11-25
申请号：US12469304
申请日：2009-05-20
申请人： Tymon Barwicz , Lidija Sekaric , Jeffrey W. Sleight
发明人： Tymon Barwicz , Lidija Sekaric , Jeffrey W. Sleight
IPC分类号： H01L29/66 , H01L21/18
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/0673 , H01L29/42392 , H01L29/78696
摘要： A nanowire product and process for fabricating it has a wafer with a buried oxide (BOX) upper layer in which a well is formed and the ends of a nanowire are on the BOX layer forming a beam that spans the well. A mask coating is formed on the upper surface of the BOX layer leaving an uncoated window over a center part of the beam and also forming a mask coating around the beam intermediate ends between each end of the beam center part and a side wall of the well. Applying oxygen through the window thins the beam center part while leaving the wire intermediate ends over the well thicker and having a generally arched shape. A thermal oxide coating can be placed on the wire and also the mask on the BOX layer before oxidation.
摘要翻译：纳米线产品及其制造方法具有具有掩埋氧化物（BOX）上层的晶片，其中形成阱，并且纳米线的端部在BOX层上形成跨越阱的束。掩模涂层形成在BOX层的上表面上，在光束的中心部分上留下未涂覆的窗口，并且还在光束中心部分的每个端部和阱的侧壁之间的光束中间端部周围形成掩模涂层。通过窗户施加氧气，使梁中心部分离开，同时将钢丝中间端部覆盖在较厚的孔上并具有大致拱形的形状。在氧化之前，可以将热氧化物涂层放置在导线上以及BOX层上的掩模上。

3. 发明授权

US08080456B2 Robust top-down silicon nanowire structure using a conformal nitride 有权
标题翻译：使用保形氮化物的坚固的自顶向下的硅纳米线结构
公开(公告)号：US08080456B2
公开(公告)日：2011-12-20
申请号：US12469304
申请日：2009-05-20
申请人： Tymon Barwicz , Lidija Sekaric , Jeffrey W. Sleight
发明人： Tymon Barwicz , Lidija Sekaric , Jeffrey W. Sleight
IPC分类号： H01L21/336
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/0673 , H01L29/42392 , H01L29/78696
摘要： In one exemplary embodiment, a method for fabricating a nanowire product comprising: providing a wafer having a buried oxide (BOX) upper layer in which a well is formed, the wafer further having a nanowire having ends resting on the BOX layer such that the nanowire forms a beam spanning said well; and forming a mask coating on an upper surface of the BOX layer leaving an uncoated window over a center part of said beam over said well and also forming a mask coating around beam intermediate ends between each end of a beam center part and a side wall of said well. In another exemplary embodiment, a nanowire product comprising: a wafer having a buried oxide (BOX) upper layer in which a well having side walls is formed; a nanowire having ends resting on the BOX layer so as to form a beam spanning said well and said side walls; and a hard mask coating on an upper surface of said BOX layer and around intermediate ends of said beam between each side wall of said well and ends of a center part of said beam leaving an uncoated window over a beam center part through which oxidation of said beam center part can take place.
摘要翻译：在一个示例性实施例中，一种用于制造纳米线产品的方法，包括：提供具有其中形成阱的掩埋氧化物（BOX）上层的晶片，所述晶片还具有具有搁置在BOX层上的端部的纳米线，使得纳米线形成横跨所述井的梁; 并且在BOX层的上表面上形成掩模涂层，在所述孔的中心部分上留下未涂覆的窗口，并且还在梁的中心部分的两端和侧壁之间的梁中间端部说得好在另一个示例性实施例中，纳米线产品包括：具有掩埋氧化物（BOX）上层的晶片，其中形成具有侧壁的阱; 具有搁置在BOX层上的端部以形成横跨所述井和所述侧壁的梁的纳米线; 以及在所述BOX层的上表面上并且在所述孔的每个侧壁和所述梁的中心部分的端部之间的所述梁的中间端周围的硬掩模涂层，在光束中心部分上留下未涂覆的窗口，通过所述光束中心部分氧化所述梁中心部分可以发生。

4. 发明授权

US08871576B2 Silicon nanotube MOSFET 有权
标题翻译：硅纳米管MOSFET
公开(公告)号：US08871576B2
公开(公告)日：2014-10-28
申请号：US13036292
申请日：2011-02-28
申请人： Daniel Tekleab , Hung H. Tran , Jeffrey W. Sleight , Dureseti Chidambarrao
发明人： Daniel Tekleab , Hung H. Tran , Jeffrey W. Sleight , Dureseti Chidambarrao
IPC分类号： H01L29/49 , H01L29/06 , B82Y10/00 , H01L29/775 , H01L29/66 , H01L29/78
CPC分类号： H01L29/78 , B82Y10/00 , H01L29/0676 , H01L29/66439 , H01L29/66666 , H01L29/775 , H01L29/7827
摘要： A nanotubular MOSFET device and a method of fabricating the same are used to extend device scaling roadmap while maintaining good short channel effects and providing competitive drive current. The nanotubular MOSFET device includes a concentric tubular inner and outer gate separated from each other by a tubular shaped epitaxially grown silicon layer, and a source and drain respectively separated by spacers surrounding the tubular inner and outer gates. The method of forming the nanotubular MOSFET device includes: forming on a substrate a cylindrical shaped Si layer; forming an outer gate surrounding the cylindrical Si layer and positioned between a bottom spacer and a top spacer; growing a silicon epitaxial layer on the top spacer adjacent to a portion of the cylindrical shaped Si layer; etching an inner portion of the cylindrical shaped Si forming a hollow cylinder; forming an inner spacer at the bottom of the inner cylinder; forming an inner gate by filling a portion of the hollow cylinder; forming a sidewall spacer adjacent to the inner gate; and etching a deep trench for accessing and contacting the outer gate and drain.
摘要翻译：纳米管MOSFET器件及其制造方法用于扩展器件缩放路线图，同时保持良好的短沟道效应并提供有竞争力的驱动电流。纳米管MOSFET器件包括通过管状外延生长硅层彼此分离的同心管状内部和外部栅极，以及分别由围绕管状内部和外部门的间隔开的源极和漏极。形成纳米管MOSFET器件的方法包括：在衬底上形成圆柱形的Si层; 形成围绕圆柱形Si层并位于底部间隔件和顶部间隔件之间的外部门; 在与圆柱形Si层的一部分相邻的顶部间隔上生长硅外延层; 蚀刻形成中空圆筒的圆柱形Si的内部; 在内筒的底部形成内隔板; 通过填充中空圆筒的一部分形成内门; 形成邻近所述内门的侧壁间隔物; 并蚀刻用于访问和接触外部栅极和漏极的深沟槽。

5. 发明申请

US20080164535A1 CURVED FINFETS 有权
标题翻译：弯曲的熔体
公开(公告)号：US20080164535A1
公开(公告)日：2008-07-10
申请号：US11621228
申请日：2007-01-09
申请人： Dureseti Chidambarrao , Shreesh Narasimha , Edward J. Nowak , John J. Pekarik , Jeffrey W. Sleight , Richard Q. Williams
发明人： Dureseti Chidambarrao , Shreesh Narasimha , Edward J. Nowak , John J. Pekarik , Jeffrey W. Sleight , Richard Q. Williams
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/785 , H01L29/0649 , H01L29/66795 , H01L29/7843
摘要： A method of forming a transistor patterns a semiconductor fin on a substrate, such that the fin extends from the substrate. Then, the method forms a gate conductor over a central portion of the fin, leaving end portions of the fin exposed. Next, the end portions of the fin are doped with at least one impurity to leave the central portion of the fin as a semiconductor and form the end portions of the fin as conductors. The end portions of the fin are undercut to disconnect the end portions of the fin from the substrate, such that the fin is connected to the substrate along a central portion and is disconnected from the substrate along the end portions and that the end portions are free to move and the central portion is not free to move. A straining layer is formed on a first side of the fin and the straining layer imparts physical pressure on the fin such that the end portions are permanently moved away from a straight-line orientation with the central portion after the forming of the straining layer. Thus, the undercutting in combination with the forming of the straining layer curves the fin such that, when viewed from a top of the substrate, the fin is bowed and has a curved shape.
摘要翻译：一种形成晶体管的方法在衬底上形成半导体鳍片，使得鳍片从衬底延伸。然后，该方法在鳍片的中心部分上形成栅极导体，使翅片的端部部分露出。接下来，翅片的端部掺杂有至少一种杂质，以使翅片的中心部分作为半导体，并将翅片的端部形成为导体。翅片的端部被底切以使翅片的端部与基板断开，使得翅片沿着中心部分连接到基板，并且沿着端部与基板断开，并且端部部分是自由的移动，中央部分不能自由移动。在翅片的第一侧上形成有应变层，并且应变层在翅片上施加物理压力，使得端部在紧固层形成之后永久地与中心部分的直线取向远离。因此，与形成应变层相结合的底切使翅片弯曲，使得当从基板的顶部观察时，翅片弯曲并具有弯曲形状。

6. 发明授权

US08648330B2 Nanowire field effect transistors 有权
标题翻译：纳米线场效应晶体管
公开(公告)号：US08648330B2
公开(公告)日：2014-02-11
申请号：US13343799
申请日：2012-01-05
申请人： Sarunya Bangsaruntip , Guy Cohen , Amlan Majumdar , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Guy Cohen , Amlan Majumdar , Jeffrey W. Sleight
IPC分类号： H01L27/12 , H01L21/335 , B82Y40/00 , B82Y99/00
CPC分类号： H01L29/42392 , B82Y10/00 , B82Y40/00 , H01L29/0673 , H01L29/068 , H01L29/66439 , H01L29/775 , H01L29/78696
摘要： A method for forming a nanowire field effect transistor (FET) device includes forming a nanowire over a substrate, forming a liner material around a portion of the nanowire, forming a capping layer on the liner material, forming a first spacer adjacent to sidewalls of the capping layer and around portions of the nanowire, forming a hardmask layer on the capping layer and the first spacer, removing an exposed portion of the nanowire to form a first cavity partially defined by the gate material, epitaxially growing a semiconductor material on an exposed cross section of the nanowire in the first cavity, removing the hardmask layer and the capping layer, forming a second capping layer around the semiconductor material epitaxially grown in the first cavity to define a channel region, and forming a source region and a drain region contacting the channel region.
摘要翻译：形成纳米线场效应晶体管（FET）器件的方法包括在衬底上形成纳米线，在纳米线的一部分周围形成衬垫材料，在衬垫材料上形成覆盖层，形成邻近覆盖层和纳米线的周围部分，在覆盖层和第一间隔物上形成硬掩模层，去除纳米线的暴露部分以形成由栅极材料部分限定的第一空腔，在暴露的杂交上外延生长半导体材料在所述第一空腔中的所述纳米线的截面，去除所述硬掩模层和所述覆盖层，在所述第一空腔中外延生长的所述半导体材料周围形成第二覆盖层，以限定沟道区，以及形成与所述第二覆盖层接触的源极区和漏极区渠道区域。

7. 发明授权

US08558219B2 Nanowire field effect transistors 有权
标题翻译：纳米线场效应晶体管
公开(公告)号：US08558219B2
公开(公告)日：2013-10-15
申请号：US13606365
申请日：2012-09-07
申请人： Sarunya Bangsaruntip , Guy Cohen , Amlan Majumdar , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Guy Cohen , Amlan Majumdar , Jeffrey W. Sleight
IPC分类号： H01L21/335 , B82Y40/00 , B82Y99/00
CPC分类号： H01L29/42392 , B82Y10/00 , B82Y40/00 , H01L29/0673 , H01L29/068 , H01L29/66439 , H01L29/775 , H01L29/78696
摘要： A method for forming a nanowire field effect transistor (FET) device includes forming a nanowire over a substrate, forming a liner material around a portion of the nanowire, forming a capping layer on the liner material, forming a first spacer adjacent to sidewalls of the capping layer and around portions of the nanowire, forming a hardmask layer on the capping layer and the first spacer, removing an exposed portion of the nanowire to form a first cavity partially defined by the gate material, epitaxially growing a semiconductor material on an exposed cross section of the nanowire in the first cavity, removing the hardmask layer and the capping layer, forming a second capping layer around the semiconductor material epitaxially grown in the first cavity to define a channel region, and forming a source region and a drain region contacting the channel region.
摘要翻译：形成纳米线场效应晶体管（FET）器件的方法包括在衬底上形成纳米线，在纳米线的一部分周围形成衬垫材料，在衬垫材料上形成覆盖层，形成邻近覆盖层和纳米线的周围部分，在覆盖层和第一间隔物上形成硬掩模层，去除纳米线的暴露部分以形成由栅极材料部分限定的第一空腔，在暴露的杂交上外延生长半导体材料在所述第一空腔中的所述纳米线的截面，去除所述硬掩模层和所述覆盖层，在所述第一空腔中外延生长的所述半导体材料周围形成第二覆盖层，以限定沟道区，以及形成与所述第二覆盖层接触的源极区和漏极区渠道区域。

8. 发明申请

US20120280206A1 Nanowire Circuits in Matched Devices 有权
标题翻译：匹配器件中的纳米线电路
公开(公告)号：US20120280206A1
公开(公告)日：2012-11-08
申请号：US13554057
申请日：2012-07-20
申请人： Sarunya Bangsaruntip , Guy Cohen , Amlan Majumdar , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Guy Cohen , Amlan Majumdar , Jeffrey W. Sleight
IPC分类号： H01L27/085 , H01L21/8232
CPC分类号： H03K19/20 , B82Y10/00 , G11C11/412 , G11C11/54 , H01L27/092 , H01L27/11 , H01L27/1104 , H01L27/12 , H01L29/0665 , H01L29/0673 , H01L29/775 , H01L29/78696
摘要： A memory device includes a first nanowire connected to a first bit line node and a ground node, a first field effect transistor (FET) having a gate disposed on the first nanowire, a second FET having a gate disposed on the first nanowire, a second nanowire connected to a voltage source node and a first input node, a third FET having a gate disposed on the second nanowire, a third nanowire connected to the voltage source node and a second input node, a fourth FET having a gate disposed on the third nanowire, a fourth nanowire connected to a second bit line node and the ground node, a fifth FET having a gate disposed on the fourth nanowire, and a sixth FET having a gate disposed on the fourth nanowire.
摘要翻译：存储器件包括连接到第一位线节点和接地节点的第一纳米线，具有设置在第一纳米线上的栅极的第一场效应晶体管（FET），具有设置在第一纳米线上的栅极的第二FET，连接到电压源节点和第一输入节点的纳米线，具有设置在第二纳米线上的栅极的第三FET，连接到电压源节点的第三纳米线和第二输入节点，具有设置在第三纳米线上的栅极的第四FET 纳米线，连接到第二位线节点的第四纳米线和所述接地节点，具有设置在所述第四纳米线上的栅极的第五FET以及设置在所述第四纳米线上的栅极的第六FET。

9. 发明申请

US20110249489A1 Nanowire Circuits in Matched Devices 有权
标题翻译：匹配器件中的纳米线电路
公开(公告)号：US20110249489A1
公开(公告)日：2011-10-13
申请号：US12758939
申请日：2010-04-13
申请人： Sarunya Bangsaruntip , Guy Cohen , Amlan Majumdar , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Guy Cohen , Amlan Majumdar , Jeffrey W. Sleight
IPC分类号： G11C11/00 , H01L21/8238 , H01L21/336 , H03K19/20
CPC分类号： H03K19/20 , B82Y10/00 , G11C11/412 , G11C11/54 , H01L27/092 , H01L27/11 , H01L27/1104 , H01L27/12 , H01L29/0665 , H01L29/0673 , H01L29/775 , H01L29/78696
摘要： An inverter device includes a first nanowire connected to a voltage source node and a ground node, a first p-type field effect transistor (pFET) device having a gate disposed on the first nanowire, and a first n-type field effect transistor (nFET) device having a gate disposed on the first nanowire.
摘要翻译：逆变器装置包括连接到电压源节点和接地节点的第一纳米线，具有设置在第一纳米线上的栅极的第一p型场效应晶体管（pFET）器件和第一n型场效应晶体管（nFET ）器件，其具有设置在第一纳米线上的栅极。

10. 发明授权

US09343142B2 Nanowire floating gate transistor 有权
标题翻译：纳米线浮栅晶体管
公开(公告)号：US09343142B2
公开(公告)日：2016-05-17
申请号：US13344517
申请日：2012-01-05
申请人： Sarunya Bangsaruntip , Guy Cohen , Amlan Majumdar , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Guy Cohen , Amlan Majumdar , Jeffrey W. Sleight
IPC分类号： H01L29/66 , H01L29/788 , G11C11/56 , H01L21/28 , H01L29/423 , H01L29/06
CPC分类号： G11C11/5671 , H01L21/28273 , H01L29/0673 , H01L29/42332 , H01L29/42336 , H01L29/66825 , H01L29/7881
摘要： A floating gate transistor, memory cell, and method of fabricating a device. The floating gate transistor includes one or more gated wires substantially cylindrical in form. The floating gate transistor includes a first gate dielectric layer at least partially covering the gated wires. The floating gate transistor further includes a plurality of gate crystals discontinuously arranged upon the first gate dielectric layer. The floating gate transistor also includes a second gate dielectric layer covering the plurality of gate crystals and the first gate dielectric layer.
摘要翻译：浮栅晶体管，存储单元及其制造方法。浮栅晶体管包括一个或多个基本上圆柱形的选通线。浮置栅极晶体管包括至少部分地覆盖选通导线的第一栅极电介质层。浮置栅极晶体管还包括不连续地布置在第一栅极介电层上的多个栅极晶体。浮栅晶体管还包括覆盖多个栅极晶体和第一栅极介电层的第二栅极电介质层。

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