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1. 发明授权

US06523494B1 Apparatus for depositing low dielectric constant oxide film 失效
标题翻译：低介电常数氧化膜沉积设备
公开(公告)号：US06523494B1
公开(公告)日：2003-02-25
申请号：US09659941
申请日：2000-09-12
申请人： Dung-Ching Perng , Peter Wai-Man Lee , Thomas E. Deacon
发明人： Dung-Ching Perng , Peter Wai-Man Lee , Thomas E. Deacon
IPC分类号： H01L2176
CPC分类号： H01L21/02126 , C23C16/402 , C23C16/56 , H01L21/02203 , H01L21/02271 , H01L21/02304 , H01L21/02312 , H01L21/02315 , H01L21/02362 , H01L21/31695
摘要： A composite silicon dioxide layer with a reduced dielectric constant is formed by enhancing the surface sensitivity of a PECVD liner layer with activated oxygen. Pores form in an SACVD layer of silicon dioxide deposited from a TEOS precursor over the sensitized PECVD layer. The pores reduce the dielectric constant of the composite layer. Activated oxygen is provided to the PECVD layer in the form of ozone or an oxygen-based plasma.
摘要翻译：通过增强具有活性氧的PECVD衬垫层的表面灵敏度，形成介电常数降低的复合二氧化硅层。在由敏化的PECVD层上的TEOS前体沉积的SACVD层中形成孔。孔隙降低了复合层的介电常数。活性氧以臭氧或氧基等离子体的形式提供给PECVD层。

2. 发明授权

US6149987A Method for depositing low dielectric constant oxide films 失效
标题翻译：沉积低介电常数氧化膜的方法
公开(公告)号：US6149987A
公开(公告)日：2000-11-21
申请号：US75592
申请日：1998-04-07
申请人： Dung-Ching Perng , Peter Wai-Man Lee , Thomas E. Deacon
发明人： Dung-Ching Perng , Peter Wai-Man Lee , Thomas E. Deacon
IPC分类号： C23C16/40 , C23C16/56 , H01L21/316 , H05H1/24
CPC分类号： H01L21/02126 , C23C16/402 , C23C16/56 , H01L21/02203 , H01L21/02271 , H01L21/02304 , H01L21/02312 , H01L21/02315 , H01L21/02362 , H01L21/31695
摘要： A composite silicon dioxide layer with a reduced dielectric constant is formed by enhancing the surface sensitivity of a PECVD liner layer with activated oxygen. Pores form in an SACVD layer of silicon dioxide deposited from a TEOS precursor over the sensitized PECVD layer. The pores reduce the dielectric constant of the composite layer. Activated oxygen is provided to the PECVD layer in the form of ozone or an oxygen-based plasma.
摘要翻译：通过增强具有活性氧的PECVD衬垫层的表面灵敏度，形成介电常数降低的复合二氧化硅层。在由敏化的PECVD层上的TEOS前体沉积的SACVD层中形成孔。孔隙降低了复合层的介电常数。活性氧以臭氧或氧基等离子体的形式提供给PECVD层。

3. 发明授权

US06423630B1 Process for forming low K dielectric material between metal lines 有权
标题翻译：在金属线之间形成低K电介质材料的工艺
公开(公告)号：US06423630B1
公开(公告)日：2002-07-23
申请号：US09704164
申请日：2000-10-31
申请人： Wilbur G. Catabay , Wei-Jen Hsia , Dung-Ching Perng
发明人： Wilbur G. Catabay , Wei-Jen Hsia , Dung-Ching Perng
IPC分类号： H01L214763
CPC分类号： H01L21/76829 , H01L21/7682 , H01L21/76834 , H01L21/76837
摘要： A process is disclosed for forming low k dielectric material between and over a plurality of spaced apart metal lines previously formed over a dielectric layer of an integrated circuit structure. The steps include: depositing, over and between the plurality of metal lines, a layer of a first low k dielectric material resistant to via poisoning; then planarizing the layer of first low k dielectric material sufficiently to open voids formed in. the first low k dielectric material between the metal lines; then depositing, over the layer of first low k dielectric material and into the opened voids, a layer of second low k dielectric material capable of filling the opened voids in the layer of first low k dielectric material; and then depositing a layer of a third low k dielectric material resistant to via poisoning over the first low k dielectric material and the voids filled with the second low k dielectric material.
摘要翻译：公开了一种用于在预先形成在集成电路结构的电介质层上的多个间隔开的金属线之间和之上形成低k电介质材料的工艺。所述步骤包括：在所述多个金属线之间和之上沉积耐经过中毒的第一低k电介质材料层; 然后使第一低k电介质材料的层平坦化，以使金属线之间的第一低k电介质材料中形成的空隙开放; 然后在第一低k电介质材料的层上沉积到开放的空隙中，形成能够填充第一低k介电材料层中的开放空隙的第二低介电材料层; 然后在第一低k电介质材料和填充有第二低k电介质材料的空隙中沉积耐经过中毒的第三低k电介质材料层。

4. 发明授权

US06369418B1 Formation of a novel DRAM cell 失效
标题翻译：形成新型DRAM单元
公开(公告)号：US06369418B1
公开(公告)日：2002-04-09
申请号：US09112687
申请日：1998-07-09
申请人： Dung-Ching Perng , Yauh-Ching Liu
发明人： Dung-Ching Perng , Yauh-Ching Liu
IPC分类号： H01L27108
CPC分类号： H01L21/76237 , H01L27/10861 , H01L27/1087 , H01L28/55 , H01L29/66181
摘要： A DRAM cell capacitor is described. Capacitor formation and cell isolation methods are integrated by using support sidewalls to form vertical DRAM capacitors. Doped polysilicon adjacent to the vertical sidewalls of the support provides one DRAM cell capacitor plate. The DRAM capacitor also contains a dielectric material that contacts and partially covers the doped polysilicon capacitor plate. Doped epitaxial silicon that contacts a portion of the dielectric forms the second capacitor plate and completes the DRAM capacitor.
摘要翻译：描述DRAM单元电容器。通过使用支撑侧壁形成垂直DRAM电容器来集成电容器形成和电池隔离方法。与支撑体的垂直侧壁相邻的掺杂多晶硅提供一个DRAM单元电容器板。 DRAM电容器还包含接触并部分覆盖掺杂多晶硅电容器板的电介质材料。与电介质的一部分接触的掺杂的外延硅形成第二电容器板并完成DRAM电容器。

5. 发明授权

US06794698B1 Formation of novel DRAM cell capacitors by integration of capacitors with isolation trench sidewalls 有权
标题翻译：通过集成电容器与隔离沟槽侧壁形成新颖的DRAM单元电容器
公开(公告)号：US06794698B1
公开(公告)日：2004-09-21
申请号：US09549265
申请日：2000-04-14
申请人： Dung-Ching Perng , Yauh-Ching Liu
发明人： Dung-Ching Perng , Yauh-Ching Liu
IPC分类号： H01L27108
CPC分类号： H01L27/10861 , H01L21/76237 , H01L27/1087 , H01L28/55 , H01L29/66181 , Y10S257/905
摘要： A DRAM cell capacitor is described. Capacitor formation and cell isolation methods are integrated by using existing isolation trench sidewalls to form DRAM capacitors. A doped silicon substrate adjacent to the vertical sidewalls of the isolation trench provides one DRAM cell capacitor plate. The DRAM capacitor also contains a dielectric material that partially covers the interior vertical sidewalls of the isolation trench. A conductive layer covering the dielectric material on the vertical sidewalls of the isolation trench forms the second capacitor plate and completes the DRAM capacitor.
摘要翻译：描述DRAM单元电容器。通过使用现有的隔离沟槽侧壁来形成电容器形成和电池隔离方法来形成DRAM电容器。与隔离沟槽的垂直侧壁相邻的掺杂硅衬底提供一个DRAM单元电容器板。 DRAM电容器还包含部分地覆盖隔离沟槽的内部垂直侧壁的电介质材料。覆盖隔离沟槽的垂直侧壁上的介电材料的导电层形成第二电容器板并完成DRAM电容器。

6. 发明授权

US6090661A Formation of novel DRAM cell capacitors by integration of capacitors with isolation trench sidewalls 失效
标题翻译：通过集成电容器与隔离沟槽侧壁形成新颖的DRAM单元电容器
公开(公告)号：US6090661A
公开(公告)日：2000-07-18
申请号：US45633
申请日：1998-03-19
申请人： Dung-Ching Perng , Yauh-Ching Liu
发明人： Dung-Ching Perng , Yauh-Ching Liu
IPC分类号： H01L21/02 , H01L21/334 , H01L21/762 , H01L21/8242 , H01L21/20 , H01L21/336 , H01L31/119
CPC分类号： H01L27/10861 , H01L21/76237 , H01L28/55 , H01L29/66181 , H01L27/1087 , Y10S257/905
摘要： A DRAM cell capacitor is described. Capacitor formation and cell insolation methods are integrated by using existing isolation trench sidewalls to form DRAM capacitors. A doped silicon substrate adjacent to the vertical sidewalls of the isolation trench provides one DRAM cell capacitor plate. The DRAM capacitor also contains a dielectric material that partially covers the interior vertical sidewalls of the isolation trench. A conductive layer covering the dielectric material on the vertical sidewalls of the isolation trench forms the second capacitor plate and completes the DRAM capacitor.
摘要翻译：描述DRAM单元电容器。通过使用现有的隔离沟槽侧壁来形成电容器形成和电池隔离方法以形成DRAM电容器。与隔离沟槽的垂直侧壁相邻的掺杂硅衬底提供一个DRAM单元电容器板。 DRAM电容器还包含部分地覆盖隔离沟槽的内部垂直侧壁的电介质材料。覆盖隔离沟槽的垂直侧壁上的介电材料的导电层形成第二电容器板并完成DRAM电容器。

7. 发明授权

US6090239A Method of single step damascene process for deposition and global planarization 有权
标题翻译：用于沉积和全局平面化的单步镶嵌工艺的方法
公开(公告)号：US6090239A
公开(公告)日：2000-07-18
申请号：US365440
申请日：1999-08-02
申请人： Yauh-Ching Liu , Dung-Ching Perng
发明人： Yauh-Ching Liu , Dung-Ching Perng
IPC分类号： B24B37/04 , H01L21/321 , H01L21/768 , C23F1/02
CPC分类号： B24B37/042 , H01L21/3212 , H01L21/7684 , H01L21/76807
摘要： A modified chemical-mechanical polishing apparatus is described. The apparatus includes: (i) a polishing pad 104 providing a surface against which a surface of an integrated circuit substrate 116 is polished; (ii) an anode 103 on which the polishing pad is secured, the anode including an electrolyzable conductive material; and (iii) a voltage source 106 electrically connecting the anode to the integrated circuit substrate in such a way that when a voltage is applied from the voltage source in the presence of slurry 114 admixed with an electrolyte composition on the polishing pad, an electrolytic cell results in which the conductive material deposits on the surface of the integrated circuit substrate. A process of depositing a conductive material on and polishing a surface of an integrated circuit substrate simultaneously is also described.
摘要翻译：描述了改进的化学机械抛光装置。该设备包括：（i）抛光垫104，其提供集成电路基板116的表面被抛光的表面; （ii）固定有抛光垫的阳极103，阳极包括可电解导电材料; 以及（iii）电压源106，其以阳极与集成电路基板电连接，使得当在浆料114的存在下与电解质组合物在抛光垫上混合的电压时，从电压源施加电压，导致导电材料沉积在集成电路基板的表面上。还描述了同时将导电材料沉积在集成电路基板的表面上并在其上抛光的工艺。

8. 发明授权

US06066570A Method and apparatus for preventing formation of black silicon on edges of wafers 有权
标题翻译：防止在硅片边缘形成黑色硅的方法和装置
公开(公告)号：US06066570A
公开(公告)日：2000-05-23
申请号：US209413
申请日：1998-12-10
申请人： Dung-Ching Perng , David M. Dobuzinsky , Ting Hao Wang , Klaus Roithner
发明人： Dung-Ching Perng , David M. Dobuzinsky , Ting Hao Wang , Klaus Roithner
IPC分类号： H01L21/302 , H01L21/20 , H01L21/306 , H01L21/3065 , H01L21/308 , H01L21/316 , H01L21/00
CPC分类号： H01L21/02164 , H01L21/0217 , H01L21/02271 , H01L21/30604 , H01L21/3081 , H01L21/31612
摘要： A method for increasing chip yield by reducing black silicon deposition in accordance with the present invention includes the steps of providing a silicon wafer suitable for fabricating semiconductor chips, depositing a first layer over an entire surface of the wafer, removing a portion of the first layer to expose a region suitable for forming semiconductor devices and etching the wafer such that a remaining portion of the first layer prevents redeposition of etched material on the wafer. A semiconductor assembly for reducing black silicon deposition thereon, includes a silicon wafer suitable for fabricating semiconductor chips, the wafer having a front surface for forming semiconductor devices, a back surface and edges. A deposited layer is formed on the wafer for covering the back surface and the edges such that redeposition of silicon on the back surface and edges of the wafer during etching is prevented.
摘要翻译：根据本发明的通过减少黑硅沉积来提高芯片产量的方法包括以下步骤：提供适于制造半导体芯片的硅晶片，在晶片的整个表面上沉积第一层，去除第一层的一部分以暴露适于形成半导体器件的区域并蚀刻晶片，使得第一层的剩余部分防止蚀刻材料在晶片上的再沉积。一种用于减少黑色硅沉积的半导体组件，包括适于制造半导体芯片的硅晶片，该晶片具有用于形成半导体器件的前表面，后表面和边缘。在晶片上形成用于覆盖背面和边缘的沉积层，从而防止在蚀刻期间在背面和晶片边缘上再沉积硅。

9. 发明授权

US6004880A Method of single step damascene process for deposition and global planarization 失效
标题翻译：用于沉积和全局平面化的单步镶嵌工艺的方法
公开(公告)号：US6004880A
公开(公告)日：1999-12-21
申请号：US27307
申请日：1998-02-20
申请人： Yauh-Ching Liu , Dung-Ching Perng
发明人： Yauh-Ching Liu , Dung-Ching Perng
IPC分类号： B24B37/04 , H01L21/321 , H01L21/768 , H01L21/288 , H01L21/302
CPC分类号： B24B37/042 , H01L21/3212 , H01L21/7684 , H01L21/76807
摘要： A modified chemical-mechanical polishing apparatus is described. The apparatus includes: (i) a polishing pad for providing a surface against which a surface of an integrated circuit substrate is polished during polishing; (ii) an anode on which the polishing pad is secured, the anode including an electrolyzable conductive material; and (iii) a voltage source including a first electrical connection and a second electrical connection, the first electrical connection being connected to the anode and the second electrical connection being configured for connection to the integrated circuit substrate undergoing polishing such that when a voltage is applied from the voltage source in the presence of slurry admixed with an electrolyte composition on the polishing pad, an electrolytic cell results in which the conductive material deposits on the surface of the integrated circuit substrate. A process of depositing a conductive material on and polishing a surface of an integrated circuit substrate simultaneously is also described.
摘要翻译：描述了改进的化学机械抛光装置。该装置包括：（i）用于提供在抛光期间抛光集成电路基板的表面的表面的抛光垫; （ii）固定有抛光垫的阳极，阳极包括可电解导电材料; 和（iii）包括第一电连接和第二电连接的电压源，所述第一电连接连接到所述阳极，并且所述第二电连接被配置为连接到正在进行抛光的所述集成电路基板，使得当施加电压时在与抛光垫上的电解质组合物混合的浆料存在的情况下，电压源产生导电材料沉积在集成电路基板的表面上的电解池。还描述了同时将导电材料沉积在集成电路基板的表面上并在其上抛光的工艺。

10. 发明授权

US06365452B1 DRAM cell having a vertical transistor and a capacitor formed on the sidewalls of a trench isolation 有权
标题翻译： DRAM单元具有垂直晶体管和形成在沟槽隔离的侧壁上的电容器
公开(公告)号：US06365452B1
公开(公告)日：2002-04-02
申请号：US09724608
申请日：2000-11-28
申请人： Dung-Ching Perng , Yauh-Ching Liu
发明人： Dung-Ching Perng , Yauh-Ching Liu
IPC分类号： H01L218242
CPC分类号： H01L27/10861 , H01L21/76237 , H01L27/1087 , H01L28/55 , H01L29/66181
摘要： A DRAM cell capacitor and access transistor are described. Capacitor formation, access transistor fabrication and cell isolation methods are integrated by using isolation trench sidewalls to form DRAM capacitors and access transistors. A doped silicon substrate adjacent to the vertical sidewalls of the isolation trench provides one DRAM cell capacitor plate. The DRAM capacitor also contains a dielectric material that partially covers the interior vertical sidewalls of the isolation trench. A conductive layer covering the dielectric material on the vertical sidewalls of the isolation trench forms the second capacitor plate and completes the DRAM capacitor. A vertically oriented access transistor is formed over top of the capacitor. To accomplish this, an isolation dielectric is deposited and patterned to provide a support structure for gate electrodes of the vertical access transistor above the trench sidewall capacitors. After gate structure formation the support layer is replaced with selectively doped epitaxial silicon in which the transistor's channel, source, and drain are formed.
摘要翻译：描述了DRAM单元电容器和存取晶体管。通过使用隔离沟槽侧壁来形成DRAM电容器和存取晶体管来集成电容器形成，存取晶体管制造和电池隔离方法。与隔离沟槽的垂直侧壁相邻的掺杂硅衬底提供一个DRAM单元电容器板。 DRAM电容器还包含部分地覆盖隔离沟槽的内部垂直侧壁的电介质材料。覆盖隔离沟槽的垂直侧壁上的介电材料的导电层形成第二电容器板并完成DRAM电容器。在电容器顶部形成垂直取向的存取晶体管。为了实现这一点，沉积和图案化隔离电介质以为沟槽侧壁电容器上方的垂直存取晶体管的栅电极提供支撑结构。在门结构形成之后，通过形成晶体管的沟道，源极和漏极的选择性掺杂的外延硅替代支撑层。

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