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1. 发明授权

US09318409B1 Integrated circuit heater for reducing stress in the integrated circuit material and chip leads of the integrated circuit, and for optimizing performance of devices of the integrated circuit 有权
标题翻译：集成电路加热器，用于减少集成电路材料中的应力和集成电路的芯片引线，并优化集成电路器件的性能
公开(公告)号：US09318409B1
公开(公告)日：2016-04-19
申请号：US14496870
申请日：2014-09-25
申请人： Douglas M. Reber , Mehul D. Shroff , Edward O. Travis
发明人： Douglas M. Reber , Mehul D. Shroff , Edward O. Travis
IPC分类号： H01L21/66 , H01L23/34
CPC分类号： H01L25/065 , G01K7/00 , G01K7/427 , H01L2924/0002 , H01L2924/00
摘要： A device comprising a first detector, comprising an output, disposed at a first location of an integrated circuit chip and configured to determine a first temperature information, a chip heater, comprising an input to receive a control signal, disposed at a second location of the integrated circuit and configured to heat an area of the integrated circuit device that includes the first location and the second location, based upon the control signal, and a heater controller comprising a first input coupled to the output of the first detector to receive the first temperature information, and an output coupled to the input of the chip heater, the heater controller configured to generate the control signal based upon the first temperature information.
摘要翻译：一种包括第一检测器的装置，包括输出，设置在集成电路芯片的第一位置并且被配置为确定第一温度信息，芯片加热器，包括用于接收控制信号的输入端，所述芯片加热器设置在所述第一温度信息的第二位置处集成电路并且被配置为基于所述控制信号加热包括所述第一位置和所述第二位置的所述集成电路装置的区域;以及加热器控制器，包括耦合到所述第一检测器的输出的第一输入以接收所述第一温度信息和耦合到芯片加热器的输入的输出，加热器控制器被配置为基于第一温度信息生成控制信号。

2. 发明申请

US20160093549A1 INTEGRATED CIRCUIT HEATER FOR REDUCING STRESS IN THE INTEGRATED CIRCUIT MATERIAL AND CHIP LEADS OF THE INTEGRATED CIRCIT, AND FOR OPTIMIZING PERFORMANCE OF DEVICES OF THE INTEGRATED CIRCUIT 有权
标题翻译：用于集成电路集成电路材料和芯片引线的集成电路加热器，并优化集成电路器件的性能
公开(公告)号：US20160093549A1
公开(公告)日：2016-03-31
申请号：US14496870
申请日：2014-09-25
申请人： Douglas M. Reber , Mehul D. Shroff , Edward O. Travis
发明人： Douglas M. Reber , Mehul D. Shroff , Edward O. Travis
IPC分类号： H01L23/34
CPC分类号： H01L25/065 , G01K7/00 , G01K7/427 , H01L2924/0002 , H01L2924/00
摘要： A device comprising a first detector, comprising an output, disposed at a first location of an integrated circuit chip and configured to determine a first temperature information, a chip heater, comprising an input to receive a control signal, disposed at a second location of the integrated circuit and configured to heat an area of the integrated circuit device that includes the first location and the second location, based upon the control signal, and a heater controller comprising a first input coupled to the output of the first detector to receive the first temperature information, and an output coupled to the input of the chip heater, the heater controller configured to generate the control signal based upon the first temperature information.
摘要翻译：一种包括第一检测器的装置，包括输出，设置在集成电路芯片的第一位置并且被配置为确定第一温度信息，芯片加热器，包括用于接收控制信号的输入端，所述芯片加热器设置在所述第一温度信息的第二位置处集成电路并且被配置为基于所述控制信号加热包括所述第一位置和所述第二位置的所述集成电路装置的区域;以及加热器控制器，包括耦合到所述第一检测器的输出的第一输入以接收所述第一温度信息和耦合到芯片加热器的输入的输出，加热器控制器被配置为基于第一温度信息生成控制信号。

3. 发明授权

US09134366B2 Method for forming a packaged semiconductor device 有权
标题翻译：用于形成封装的半导体器件的方法
公开(公告)号：US09134366B2
公开(公告)日：2015-09-15
申请号：US14011160
申请日：2013-08-27
申请人： Sergio A. Ajuria , Phuc M. Nguyen , Douglas M. Reber
发明人： Sergio A. Ajuria , Phuc M. Nguyen , Douglas M. Reber
IPC分类号： H01L21/66 , G01R31/28 , H01L23/522
CPC分类号： G01R31/2884 , G01R31/2896 , H01L22/32 , H01L23/5226 , H01L24/19 , H01L2224/13
摘要： A method of fabricating a packaged semiconductor device includes integrating a plurality of singulated semiconductor die in a die carrier, and forming one or more interconnect layers on the die carrier. The interconnect layers include at least one of conductive intra-layer structures and inter-layer structures coupled to contact pads on the plurality of singulated semiconductor die. A set of landing pads is formed coupled to a first subset of the contact pads via a first set of the conductive intra-layer structures and inter-layer structures. A set of probe pads is formed coupled to a second subset of the contact pads via a second set of the conductive intra-layer structures and inter-layer structures. The die carrier is singulated to form a plurality of packaged semiconductor devices. The set of probe pads is removed during the singulating the die carrier.
摘要翻译：制造封装半导体器件的方法包括将多个单片化半导体管芯集成在管芯载体中，并在管芯载体上形成一个或多个互连层。互连层包括耦合到多个单片半导体管芯上的接触焊盘的导电层内结构和层间结构中的至少一个。一组着陆焊盘通过第一组导电层内结构和层间结构形成为耦合到接触焊盘的第一子集。通过第二组导电层内结构和层间结构，形成耦合到接触焊盘的第二子集的一组探针焊盘。将管芯载体分离以形成多个封装的半导体器件。在分离模具载体期间移除探针焊盘组。

4. 发明授权

US09032615B2 Method for forming an electrical connection between metal layers 有权
标题翻译：在金属层之间形成电连接的方法
公开(公告)号：US09032615B2
公开(公告)日：2015-05-19
申请号：US13562534
申请日：2012-07-31
申请人： Edward O. Travis , Douglas M. Reber , Mehul D. Shroff
发明人： Edward O. Travis , Douglas M. Reber , Mehul D. Shroff
IPC分类号： H01K3/10 , G06F17/50 , H01L21/768 , H01L23/522 , H01L29/41
CPC分类号： H01L21/76816 , G06F17/5077 , H01L23/5226 , H01L29/41 , H01L2924/0002 , Y10T29/49124 , Y10T29/49155 , Y10T29/49165 , H01L2924/00
摘要： A method forms an electrical connection between a first metal layer and a second metal layer. The second metal layer is above the first metal layer. A first via is formed between the first metal layer and the second metal layer. A first measure of a number of vacancies expected to reach the first via is obtained. A second via in at least one of the first metal layer and the second metal layer is formed if the measure of vacancies exceeds a first predetermined number.
摘要翻译：一种方法形成第一金属层和第二金属层之间的电连接。第二金属层在第一金属层之上。在第一金属层和第二金属层之间形成第一通孔。获得预计达到第一个通道的空缺数量的首要措施。如果空位的测量超过第一预定数量，则形成第一金属层和第二金属层中的至少一个的第二通孔。

5. 发明授权

US08703507B1 Method and apparatus to improve reliability of vias 有权
标题翻译：提高通孔可靠性的方法和装置
公开(公告)号：US08703507B1
公开(公告)日：2014-04-22
申请号：US13630996
申请日：2012-09-28
申请人： Douglas M. Reber
发明人： Douglas M. Reber
IPC分类号： G01R31/26 , H01L21/66
CPC分类号： G06F17/5068 , G06F2217/72 , H01L21/76814 , H01L23/528 , H01L2924/0002 , H01L2924/0001 , H01L2924/00
摘要： A semiconductor device comprising a first insulating layer, a first metal conductor layer formed over the first insulating layer, a second insulating layer comprising a low-k insulating material formed over the first metal conductor, a second metal conductor layer formed over the second insulating layer, vias formed in the second insulating layer connecting the first metal conductor layer to the second metal conductor layer, and a plurality of metal lines. One of the metal lines is expanded around one of the vias compared to metal lines around other ones of the vias so that predetermined areas around each of the vias meets a minimum metal density.
摘要翻译：一种半导体器件，包括第一绝缘层，形成在第一绝缘层上的第一金属导体层，包含形成在第一金属导体上的低k绝缘材料的第二绝缘层，形成在第二绝缘层上的第二金属导体层形成在连接第一金属导体层和第二金属导体层的第二绝缘层中的通孔，以及多个金属线。与围绕其他通孔的金属线相比，其中一条金属线扩展到其中一条通孔，使得每个通孔周围的预定区域达到最小金属密度。

6. 发明申请

US20140038317A1 METHOD FOR FORMING AN ELECTRICAL CONNECTION BETWEEN METAL LAYERS 有权
标题翻译：在金属层之间形成电气连接的方法
公开(公告)号：US20140038317A1
公开(公告)日：2014-02-06
申请号：US13562534
申请日：2012-07-31
申请人： Edward O. Travis , Douglas M. Reber , Mehul D. Shroff
发明人： Edward O. Travis , Douglas M. Reber , Mehul D. Shroff
IPC分类号： H01L21/768
CPC分类号： H01L21/76816 , G06F17/5077 , H01L23/5226 , H01L29/41 , H01L2924/0002 , Y10T29/49124 , Y10T29/49155 , Y10T29/49165 , H01L2924/00
摘要： A method forms an electrical connection between a first metal layer and a second metal layer. The second metal layer is above the first metal layer. A first via is formed between the first metal layer and the second metal layer. A first measure of a number of vacancies expected to reach the first via is obtained. A second via in at least one of the first metal layer and the second metal layer is formed if the measure of vacancies exceeds a first predetermined number.
摘要翻译：一种方法形成第一金属层和第二金属层之间的电连接。第二金属层在第一金属层之上。在第一金属层和第二金属层之间形成第一通孔。获得预计达到第一个通道的空缺数量的首要措施。如果空位的测量超过第一预定数量，则形成第一金属层和第二金属层中的至少一个的第二通孔。

7. 发明授权

US08581390B2 Semiconductor device with heat dissipation 有权
标题翻译：半导体器件散热
公开(公告)号：US08581390B2
公开(公告)日：2013-11-12
申请号：US13442015
申请日：2012-04-09
申请人： Edward O. Travis , Douglas M. Reber , Mehul D. Shroff
发明人： Edward O. Travis , Douglas M. Reber , Mehul D. Shroff
IPC分类号： H01L23/34 , H01L23/10
CPC分类号： H01L23/3677 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/29 , H01L24/30 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/92 , H01L25/0657 , H01L2224/13082 , H01L2224/131 , H01L2224/13147 , H01L2224/14164 , H01L2224/16225 , H01L2224/16227 , H01L2224/29015 , H01L2224/29082 , H01L2224/291 , H01L2224/29147 , H01L2224/30154 , H01L2224/30164 , H01L2224/30177 , H01L2224/73103 , H01L2224/73203 , H01L2224/81801 , H01L2224/83801 , H01L2224/9211 , H01L2225/06513 , H01L2225/06589 , H01L2924/00012 , H01L2924/00014 , H01L2924/014 , H01L2224/81 , H01L2224/83
摘要： A semiconductor assembly includes a semiconductor device and a connecting structure. The semiconductor device includes an interconnect region over a semiconductor substrate and a pillar layer having a plurality of pillar contacts on the interconnect region. The pillar layer also includes a plurality of radial heat conductors that have at least a portion overlying a heat source that is within and overlies the semiconductor substrate. Each radial heat conductor extends a length radially from the heat source that is at least twice as great as the diameter of the pillars. The connecting structure includes a connecting substrate that supports a first corresponding pillar contact that is in contact with a first pillar contact of the plurality of pillar contacts. The first connecting structure further includes a heat conductor, supported by the substrate, in contact with a first radial heat conductor of the plurality of radial heat conductors.
摘要翻译：半导体组件包括半导体器件和连接结构。半导体器件包括半导体衬底上的互连区域和在互连区域上具有多个柱状触点的柱层。柱层还包括多个径向热导体，其具有覆盖在半导体衬底内并覆盖半导体衬底的热源的至少一部分。每个径向导热体从热源的径向延伸至少两倍于柱的直径。连接结构包括支撑与多个柱接触件的第一柱接触件接触的第一对应的柱接触件的连接基板。所述第一连接结构还包括由所述基板支撑的与所述多个径向导热体的第一径向导热体接触的导热体。

8. 发明授权

US07199429B2 Semiconductor device having an organic anti-reflective coating (ARC) and method therefor 有权
标题翻译：具有有机抗反射涂层（ARC）的半导体器件及其方法
公开(公告)号：US07199429B2
公开(公告)日：2007-04-03
申请号：US11100163
申请日：2005-04-06
申请人： Douglas M. Reber , Mark D. Hall , Kurt H. Junker , Kyle W. Patterson , Tab Allen Stephens , Edward K. Theiss , Srikanteswara Dakshiina-Murthy , Marilyn Irene Wright
发明人： Douglas M. Reber , Mark D. Hall , Kurt H. Junker , Kyle W. Patterson , Tab Allen Stephens , Edward K. Theiss , Srikanteswara Dakshiina-Murthy , Marilyn Irene Wright
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/02164 , H01L21/02274 , H01L21/0276 , H01L21/0332 , H01L21/0338 , H01L21/28035 , H01L21/28123 , H01L21/31612 , H01L21/32139 , H01L29/6659 , H01L29/7833 , Y10S438/902 , Y10S438/952
摘要： In a making a semiconductor device, a patterning stack above a conductive material that is to be etched has a patterned photoresist layer that is used to pattern an underlying a tetraethyl-ortho-silicate (TEOS) layer. The TEOS layer is deposited at a lower temperature than is conventional. The low temperature TEOS layer is over an organic anti-reflective coating (ARC) that is over the conductive layer. The low temperature TEOS layer provides adhesion between the organic ARC and the photoresist, has low defectivity, operates as a hard mask, and serves as a phase shift layer that helps, in combination with the organic ARC, to reduce undesired reflection.
摘要翻译：在制造半导体器件中，待蚀刻的导电材料上方的图案化叠层具有图案化的光致抗蚀剂层，其用于对四乙基原硅酸盐（TEOS）层进行图案化。在比常规温度低的温度下沉积TEOS层。低温TEOS层位于导电层上方的有机抗反射涂层（ARC）上。低温TEOS层提供有机ARC和光致抗蚀剂之间的粘附，具有低缺陷性，作为硬掩模操作，并且用作与有机ARC组合有助于减少不期望的反射的相移层。

9. 发明授权

US06597234B2 Anti-fuse circuit and method of operation 失效
标题翻译：防熔丝电路及操作方法
公开(公告)号：US06597234B2
公开(公告)日：2003-07-22
申请号：US10017429
申请日：2001-12-14
申请人： Douglas M. Reber , Stephen R. Crown
发明人： Douglas M. Reber , Stephen R. Crown
IPC分类号： H01H3776
CPC分类号： H01L23/5252 , G11C17/18 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An anti-fuse useful in implementing redundancy in a memory utilizes a normal transistor characteristic that is generally considered undesirable in order to provide two easily detected states. The un-programmed state, which is the high impedance state, is achieved simply with a normal transistor in its non-conductive state. The programmed state, which is the low impedance state, is achieved by forcing a normal transistor to conduct current through its gate. This causes the gate dielectric to become permanently conductive. This programmed transistor then is conductive between its source and drain that is easily differentiated from the transistor that is held in its non-conductive state. The result is a fuse technology using an anti-fuse that provides for easily distinguishable programmed and un-programmed states achieved by electrical programming rather than by laser programming.
摘要翻译：用于实现存储器中冗余的反熔丝利用通常被认为是不期望的以提供两个容易检测状态的正常晶体管特性。非编程状态，即高阻抗状态，简单地用非导通状态的正常晶体管实现。通过强制正常晶体管将电流传导通过其栅极来实现低阻状态的编程状态。这导致栅极电介质变得永久导电。然后，该编程晶体管在其源极和漏极之间是导电的，其容易与保持在其非导通状态的晶体管区分开。结果是采用了一种使用反熔丝的保险丝技术，可以通过电气编程而不是通过激光编程实现轻松区分编程和非编程状态。

10. 发明授权

US06555915B1 Integrated circuit having interconnect to a substrate and method therefor 失效
标题翻译：具有与衬底互连的集成电路及其方法
公开(公告)号：US06555915B1
公开(公告)日：2003-04-29
申请号：US09986232
申请日：2001-10-22
申请人： Douglas M. Reber
发明人： Douglas M. Reber
IPC分类号： H01L2940
CPC分类号： H01L21/76895 , H01L21/76838 , H01L21/823475
摘要： A contact between a source/drain and a gate is made by making a selected portion of the gate dielectric conductive by an implant into that selected portion of the gate dielectric. The gate material is in a layer over the entire integrated circuit. Areas where gates are to connect to source/drains are indentified and the gate dielectric at those identified locations is implanted to make it conductive. The source/drains are formed so that they extend under these areas of conductive gate dielectric so that at these locations the implanted gate dielectric shorts the gate to the source/drain. This saves area on the integrated circuit, reduces the need for interconnect layers, and avoids the problems associated with depositing and etching polysilicon on an exposed silicon substrate.
摘要翻译：源极/漏极和栅极之间的接触通过使栅极电介质的选定部分通过植入物导电到该栅极电介质的该选定部分来进行。栅极材料位于整个集成电路的一层中。栅极连接到源极/漏极的区域被识别，并且植入那些识别位置处的栅极电介质以使其导电。源极/漏极形成为使得它们在导电栅极电介质的这些区域下方延伸，使得在这些位置处，注入的栅极电介质将栅极短路到源极/漏极。这节省了集成电路上的区域，减少了对互连层的需求，并且避免了在暴露的硅衬底上沉积和蚀刻多晶硅相关的问题。

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