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1. 发明授权

US07310036B2 Heat sink for integrated circuit devices 有权
标题翻译：集成电路器件的散热片
公开(公告)号：US07310036B2
公开(公告)日：2007-12-18
申请号：US10905546
申请日：2005-01-10
申请人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Terence B. Hook , Robert M. Rassel , Edmund J. Sprogis , Anthony K Stamper , William J. Murphy
发明人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Terence B. Hook , Robert M. Rassel , Edmund J. Sprogis , Anthony K Stamper , William J. Murphy
IPC分类号： H01C1/08
CPC分类号： H01C7/1013 , H01C1/084 , H01L2924/0002 , Y10T29/49083 , Y10T29/49085 , Y10T29/49099 , Y10T29/49144 , Y10T29/49147 , H01L2924/00
摘要： A resistor with heat sink is provided. The heat sink includes a conductive path having metal or other thermal conductor having a high thermal conductivity. To avoid shorting the electrical resistor to ground with the thermal conductor, a thin layer of high thermal conductivity electrical insulator is interposed between the thermal conductor and the body of the resistor. Accordingly, a resistor can carry large amounts of current because the high conductivity thermal conductor will conduct heat away from the resistor to a heat sink. Various configurations of thermal conductors and heat sinks are provided offering good thermal conductive properties in addition to reduced parasitic capacitances and other parasitic electrical effects, which would reduce the high frequency response of the electrical resistor.
摘要翻译：提供带散热片的电阻。散热器包括具有导热性高的金属或其它热导体的导电路径。为了避免使用热导体将电阻器短路接地，在热导体和电阻体之间插入有一层薄导电电绝缘体。因此，电阻器可承载大量的电流，因为高导电性热导体将热量从电阻器传导到散热器。除了降低寄生电容和其他寄生电效应之外，提供各种配置的导热体和散热片，提供良好的导热性能，这将降低电阻器的高频响应。

2. 发明授权

US08881379B2 Method of making heat sink for integrated circuit devices 有权
标题翻译：为集成电路器件制造散热片的方法
公开(公告)号：US08881379B2
公开(公告)日：2014-11-11
申请号：US13460871
申请日：2012-05-01
申请人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Terence B. Hook , Robert M. Rassel , Edmund J. Sprogis , Anthony K. Stamper , William J. Murphy
发明人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Terence B. Hook , Robert M. Rassel , Edmund J. Sprogis , Anthony K. Stamper , William J. Murphy
IPC分类号： H05B3/00 , H01C1/084 , H01C7/10
CPC分类号： H01C7/1013 , H01C1/084 , H01L2924/0002 , Y10T29/49083 , Y10T29/49085 , Y10T29/49099 , Y10T29/49144 , Y10T29/49147 , H01L2924/00
摘要： A resistor with heat sink is provided. The heat sink includes a conductive path having metal or other thermal conductor having a high thermal conductivity. To avoid shorting the electrical resistor to ground with the thermal conductor, a thin layer of high thermal conductivity electrical insulator is interposed between the thermal conductor and the body of the resistor. Accordingly, a resistor can carry large amounts of current because the high conductivity thermal conductor will conduct heat away from the resistor to a heat sink. Various configurations of thermal conductors and heat sinks are provided offering good thermal conductive properties in addition to reduced parasitic capacitances and other parasitic electrical effects, which would reduce the high frequency response of the electrical resistor.
摘要翻译：提供带散热片的电阻。散热器包括具有导热性高的金属或其它热导体的导电路径。为了避免使用热导体将电阻器短路接地，在热导体和电阻体之间插入有一层薄导电电绝缘体。因此，电阻器可承载大量的电流，因为高导电性热导体将热量从电阻器传导到散热器。除了降低寄生电容和其他寄生电效应之外，提供各种配置的导热体和散热片，提供良好的导热性能，这将降低电阻器的高频响应。

3. 发明授权

US07994895B2 Heat sink for integrated circuit devices 失效
标题翻译：散热器用于集成电路设备
公开(公告)号：US07994895B2
公开(公告)日：2011-08-09
申请号：US11777389
申请日：2007-07-13
申请人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Terence B. Hook , Robert M. Rassel , Edmund J. Sprogis , Anthony K. Stamper , William J. Murphy
发明人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Terence B. Hook , Robert M. Rassel , Edmund J. Sprogis , Anthony K. Stamper , William J. Murphy
IPC分类号： H01C1/08
CPC分类号： H01C7/1013 , H01C1/084 , H01L2924/0002 , Y10T29/49083 , Y10T29/49085 , Y10T29/49099 , Y10T29/49144 , Y10T29/49147 , H01L2924/00
摘要： A resistor with heat sink is provided. The heat sink includes a conductive path having metal or other thermal conductor having a high thermal conductivity. To avoid shorting the electrical resistor to ground with the thermal conductor, a thin layer of high thermal conductivity electrical insulator is interposed between the thermal conductor and the body of the resistor. Accordingly, a resistor can carry large amounts of current because the high conductivity thermal conductor will conduct heat away from the resistor to a heat sink. Various configurations of thermal conductors and heat sinks are provided offering good thermal conductive properties in addition to reduced parasitic capacitances and other parasitic electrical effects, which would reduce the high frequency response of the electrical resistor.
摘要翻译：提供带散热片的电阻。散热器包括具有导热性高的金属或其它热导体的导电路径。为了避免使用热导体将电阻器短路接地，在热导体和电阻体之间插入有一层薄导电电绝缘体。因此，电阻器可承载大量的电流，因为高导电性热导体将热量从电阻器传导到散热器。除了降低寄生电容和其他寄生电效应之外，提供各种配置的导热体和散热片，提供良好的导热性能，这将降低电阻器的高频响应。

4. 发明授权

US07566946B2 Precision passive circuit structure 失效
标题翻译：精密无源电路结构
公开(公告)号：US07566946B2
公开(公告)日：2009-07-28
申请号：US11865432
申请日：2007-10-01
申请人： Douglas D. Coolbaugh , Hayden C. Cranford, Jr. , Terence B. Hook , Anthony K. Stamper
发明人： Douglas D. Coolbaugh , Hayden C. Cranford, Jr. , Terence B. Hook , Anthony K. Stamper
IPC分类号： H01C10/00
CPC分类号： H01L27/0802 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A circuit having a precision passive circuit element, such as a resistor or a capacitor, with a target value of an electrical parameter is fabricated on a substrate with a plurality of independent parallel-connected passive circuit elements. The plurality of passive circuit elements are designed to have a plurality of values of the electrical parameter which are spaced or offset at or around the target value of the electrical parameter, such as three circuit elements with one having a value at the target value, one having a value above the target value, and one having a value below the target value. Each passive circuit element also has a fuse in series therewith. A reference calibration structure is also fabricated, which can be a passive circuit element having the target value of the electrical parameter, in a reference area of the substrate under the same conditions and at the same time as fabrication of the plurality of passive circuit elements. The actual component value of the reference calibration structure is then measured, and based upon the measurement a single precision passive element of the plurality of parallel passive circuit elements is selected by blowing the fuses of, and thus deselecting, the other independent parallel connected passive circuit elements.
摘要翻译：在具有多个独立并联无源电路元件的基板上制造具有目标值为电参数的精密无源电路元件（例如电阻器或电容器）的电路。多个无源电路元件被设计为具有电参数的多个值，其在电参数的目标值处或周围被间隔或偏移，例如具有值在目标值的三个电路元件，一个具有高于目标值的值，并且具有低于目标值的值。每个无源电路元件还具有与其串联的保险丝。还可以在相同条件下的基板的参考区域中以及在制造多个无源电路元件的同时，制造参考校准结构，其可以是具有电参数的目标值的无源电路元件。然后测量参考校准结构的实际分量值，并且基于测量，多个并联无源电路元件中的单精度无源元件通过吹入另一个独立并联无源电路的熔丝并因此取消选择来选择元素。

5. 发明授权

US07300807B2 Structure and method for providing precision passive elements 失效
标题翻译：提供精密无源元件的结构和方法
公开(公告)号：US07300807B2
公开(公告)日：2007-11-27
申请号：US10709109
申请日：2004-04-14
申请人： Douglas D Coolbaugh , Hayden C. Cranford, Jr. , Terence B. Hook , Anthony K. Stamper
发明人： Douglas D Coolbaugh , Hayden C. Cranford, Jr. , Terence B. Hook , Anthony K. Stamper
IPC分类号： H01L21/66
CPC分类号： H01L27/0802 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A circuit having a precision passive circuit element, such as a resistor or a capacitor, with a target value of an electrical parameter is fabricated on a substrate with a plurality of independent parallel-connected passive circuit elements. The plurality of passive circuit elements are designed to have a plurality of values of the electrical parameter which are spaced or offset at or around the target value of the electrical parameter, such as three circuit elements with one having a value at the target value, one having a value above the target value, and one having a value below the target value. Each passive circuit element also has a fuse in series therewith. A reference calibration structure is also fabricated, which can be a passive circuit element having the target value of the electrical parameter, in a reference area of the substrate under the same conditions and at the same time as fabrication of the plurality of passive circuit elements. The actual component value of the reference calibration structure is then measured, and based upon the measurement a single precision passive element of the plurality of parallel passive circuit elements is selected by blowing the fuses of, and thus deselecting, the other independent parallel connected passive circuit elements.
摘要翻译：在具有多个独立并联无源电路元件的基板上制造具有目标值为电参数的精密无源电路元件（例如电阻器或电容器）的电路。多个无源电路元件被设计为具有电参数的多个值，其在电参数的目标值处或周围被间隔或偏移，例如具有值在目标值的三个电路元件，一个具有高于目标值的值，并且具有低于目标值的值。每个无源电路元件还具有与其串联的保险丝。还可以在相同条件下的基板的参考区域中以及在制造多个无源电路元件的同时，制造参考校准结构，其可以是具有电参数的目标值的无源电路元件。然后测量参考校准结构的实际分量值，并且基于测量，多个并联无源电路元件中的单精度无源元件通过吹入另一个独立并联无源电路的熔丝并因此取消选择来选择元素。

6. 发明授权

US07928513B2 Protection against charging damage in hybrid orientation transistors 有权
标题翻译：在混合取向晶体管中防止充电损坏
公开(公告)号：US07928513B2
公开(公告)日：2011-04-19
申请号：US12317310
申请日：2008-12-22
申请人： Terence B. Hook , Anda C. Mocuta , Jeffrey W. Sleight , Anthony K. Stamper
发明人： Terence B. Hook , Anda C. Mocuta , Jeffrey W. Sleight , Anthony K. Stamper
IPC分类号： H01L27/12
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823878 , H01L27/0251 , H01L27/0629 , H01L27/1203 , H01L27/1207
摘要： A chip can include a CMOS structure having a bulk device disposed in a first region of a semiconductor substrate in conductive communication with an underlying bulk region of the substrate, the first region and the bulk region having a first crystal orientation. An SOI device is disposed in a semiconductor-on-insulator (“SOI”) layer separated from the bulk region of the substrate by a buried dielectric layer, the SOI layer having a different crystal orientation from the first crystal orientation. In one example, the bulk device includes a p-type field effect transistor (“PFET”) and the SOI device includes an n-type field effect transistor (“NFET”) device. Alternatively, the bulk device can include an NFET and the SOI device can include a PFET. When the SOI device has a gate conductor in conductive communication with a gate conductor of the bulk device, charging damage can occur to the SOI device, except for the presence of diodes in reverse-biased conductive communication with the bulk region. The diodes are operable to conduct a discharge current to the bulk region when either a voltage on the gate conductor or a voltage on the source or drain region of the SOI device exceeds a diode's breakdown voltage.
摘要翻译：芯片可以包括CMOS结构，其具有设置在半导体衬底的第一区域中的体器件，其与衬底的下面的体区域导电连通，第一区域和体区具有第一晶体取向。 SOI器件设置在绝缘体上半导体（“SOI”）层中，其通过掩埋电介质层与衬底的本体区域分离，SOI层具有与第一晶体取向不同的晶体取向。在一个示例中，体器件包括p型场效应晶体管（“PFET”），并且SOI器件包括n型场效应晶体管（“NFET”）器件。或者，体器件可以包括NFET，并且SOI器件可以包括PFET。当SOI器件具有与本体器件的栅极导体导通的栅极导体时，除了存在与体区域反向偏置导电连通的二极管之外，SOI器件可能发生充电损坏。当栅极导体上的电压或SOI器件的源极或漏极区域上的电压超过二极管的击穿电压时，二极管可操作以将放电电流传导到体区。

7. 发明授权

US07879650B2 Method of providing protection against charging damage in hybrid orientation transistors 有权
标题翻译：在混合取向晶体管中提供防止充电损坏的方法
公开(公告)号：US07879650B2
公开(公告)日：2011-02-01
申请号：US12002807
申请日：2007-12-19
申请人： Terence B. Hook , Anda C. Mocuta , Jeffrey W. Sleight , Anthony K. Stamper
发明人： Terence B. Hook , Anda C. Mocuta , Jeffrey W. Sleight , Anthony K. Stamper
IPC分类号： H01L21/8238
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823878 , H01L27/0251 , H01L27/0629 , H01L27/1203 , H01L27/1207
摘要： In a method of fabricating a CMOS structure, a bulk device can be formed in a first region in conductive communication with an underlying bulk region of the substrate. A first gate conductor may overlie the first region. An SOI device can be formed which has a source drain conduction path in a SOI layer, i.e., a semiconductor layer that is separated from the bulk region by a buried dielectric region. The crystal orientations of the SOI layer and the bulk region can be different. A first diode can be formed in a second region of the substrate in conductive communication with the bulk region. The first diode may be connected in a reverse-biased orientation to a first gate conductor above the SOI layer, such that a voltage on the gate conductor that exceeds the breakdown voltage can be discharged through the first diode to the bulk region of the substrate. A second diode may be formed in a third region of the substrate in conductive communication with the bulk region. The second diode may be connected in a reverse-biased orientation to a source region or a drain region of an NFET.
摘要翻译：在制造CMOS结构的方法中，本体器件可以形成在与衬底的下面的主体区域导电连通的第一区域中。第一栅极导体可以覆盖在第一区域上。可以形成在SOI层中具有源极漏极传导路径的SOI器件，即通过掩埋电介质区域与本体区域分离的半导体层。 SOI层和体区的晶体取向可以不同。第一二极管可以形成在衬底的与体区导电连通的第二区域中。第一二极管可以以反向偏置的方式连接到SOI层上方的第一栅极导体，使得超过击穿电压的栅极导体上的电压可以通过第一二极管放电到衬底的主体区域。第二二极管可以形成在衬底的与体区导电连通的第三区域中。第二二极管可以以反向偏置的方式连接到NFET的源极区域或漏极区域。

8. 发明授权

US07492016B2 Protection against charging damage in hybrid orientation transistors 失效
标题翻译：在混合取向晶体管中防止充电损坏
公开(公告)号：US07492016B2
公开(公告)日：2009-02-17
申请号：US11308513
申请日：2006-03-31
申请人： Terence B. Hook , Anda C. Mocuta , Jeffrey W. Sleight , Anthony K. Stamper
发明人： Terence B. Hook , Anda C. Mocuta , Jeffrey W. Sleight , Anthony K. Stamper
IPC分类号： H01L23/62
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823878 , H01L27/0251 , H01L27/0629 , H01L27/1203 , H01L27/1207
摘要： A chip includes a CMOS structure having a bulk device disposed in a first region of a semiconductor substrate in conductive communication with an underlying bulk region of the substrate, the first region and the bulk region having a first crystal orientation. A SOI device is disposed in a semiconductor-on-insulator (“SOI”) layer separated from the bulk region of the substrate by a buried dielectric layer, the SOI layer having a different crystal orientation from the first crystal orientation. In one example, the bulk device includes a p-type field effect transistor (“PFET”) and the SOI device includes an n-type field effect transistor (“NFET”) device. Alternatively, the bulk device can include an NFET and the SOI device can include a PFET. When the SOI device has a gate conductor in conductive communication with a gate conductor of the bulk device, charging damage can occur to the SOI device, except for the presence of diodes in reverse-biased conductive communication with the bulk region. The diodes are operable to conduct a discharge current to the bulk region when either a voltage on the gate conductor or a voltage on the source or drain region of the SOI device exceeds a diode's breakdown voltage.
摘要翻译：芯片包括CMOS结构，其具有设置在半导体衬底的与衬底的下面的主体区域导电连通的第一区域中的本体器件，第一区域和主体区域具有第一晶体取向。 SOI器件设置在绝缘体上半导体（“SOI”）层中，该绝缘体绝缘体（“SOI”）层通过掩埋电介质层与衬底的主体区域分离，SOI层具有与第一晶体取向不同的晶体取向。在一个示例中，体器件包括p型场效应晶体管（“PFET”），并且SOI器件包括n型场效应晶体管（“NFET”）器件。或者，体器件可以包括NFET，并且SOI器件可以包括PFET。当SOI器件具有与本体器件的栅极导体导通的栅极导体时，除了存在与体区域反向偏置导电连通的二极管之外，SOI器件可能发生充电损坏。当栅极导体上的电压或SOI器件的源极或漏极区域上的电压超过二极管的击穿电压时，二极管可操作以将放电电流传导到体区。

9. 发明申请

US20090179269A1 Protection against charging damage in hybrid orientation transistors 有权
标题翻译：在混合取向晶体管中防止充电损坏
公开(公告)号：US20090179269A1
公开(公告)日：2009-07-16
申请号：US12317310
申请日：2008-12-22
申请人： Terence B. Hook , Anda C. Mocuta , Jeffrey W. Sleight , Anthony K. Stamper
发明人： Terence B. Hook , Anda C. Mocuta , Jeffrey W. Sleight , Anthony K. Stamper
IPC分类号： H01L27/12
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823878 , H01L27/0251 , H01L27/0629 , H01L27/1203 , H01L27/1207
摘要： A chip can include a CMOS structure having a bulk device disposed in a first region of a semiconductor substrate in conductive communication with an underlying bulk region of the substrate, the first region and the bulk region having a first crystal orientation. An SOI device is disposed in a semiconductor-on-insulator (“SOI”) layer separated from the bulk region of the substrate by a buried dielectric layer, the SOI layer having a different crystal orientation from the first crystal orientation. In one example, the bulk device includes a p-type field effect transistor (“PFET”) and the SOI device includes an n-type field effect transistor (“NFET”) device. Alternatively, the bulk device can include an NFET and the SOI device can include a PFET. When the SOI device has a gate conductor in conductive communication with a gate conductor of the bulk device, charging damage can occur to the SOI device, except for the presence of diodes in reverse-biased conductive communication with the bulk region. The diodes are operable to conduct a discharge current to the bulk region when either a voltage on the gate conductor or a voltage on the source or drain region of the SOI device exceeds a diode's breakdown voltage.
摘要翻译：芯片可以包括CMOS结构，其具有设置在半导体衬底的第一区域中的体器件，其与衬底的下面的体区域导电连通，第一区域和体区具有第一晶体取向。 SOI器件设置在绝缘体上半导体（“SOI”）层中，其通过掩埋电介质层与衬底的本体区域分离，SOI层具有与第一晶体取向不同的晶体取向。在一个示例中，体器件包括p型场效应晶体管（“PFET”），并且SOI器件包括n型场效应晶体管（“NFET”）器件。或者，体器件可以包括NFET，并且SOI器件可以包括PFET。当SOI器件具有与本体器件的栅极导体导通的栅极导体时，除了存在与体区域反向偏置导电连通的二极管之外，SOI器件可能发生充电损坏。当栅极导体上的电压或SOI器件的源极或漏极区域上的电压超过二极管的击穿电压时，二极管可操作以将放电电流传导到体区。

10. 发明授权

US07166904B2 Structure and method for local resistor element in integrated circuit technology 有权
标题翻译：集成电路技术中局部电阻元件的结构与方法
公开(公告)号：US07166904B2
公开(公告)日：2007-01-23
申请号：US10708023
申请日：2004-02-03
申请人： Jason P. Gill , Terence B. Hook , Randy W. Mann , William J. Murphy , William R. Tonti , Steven H. Voldman
发明人： Jason P. Gill , Terence B. Hook , Randy W. Mann , William J. Murphy , William R. Tonti , Steven H. Voldman
IPC分类号： H01L29/00
CPC分类号： H01L27/11 , H01L27/0288 , H01L27/0802 , H01L27/1112 , H01L27/1203 , H01L29/7304 , H01L29/7378 , H01L29/7391 , H01L29/78 , Y10S257/903 , Y10S257/904
摘要： A method and system for forming a semiconductor device having superior ESD protection characteristics. A resistive material layer is disposed within a contact hole on at least one of the contact stud upper and lower surface. In preferred embodiments, the integral resistor has a resistance value of between about one Ohm and about ten Ohms, or between 10 and 100 Ohms. Embodiments of the resistive layer include sputtered silicon material, a tunnel oxide, a tunnel nitride, a silicon-implanted oxide, a silicon-implanted nitride, or an amorphous polysilicon. Embodiments of the invention include SRAMs, bipolar transistors, SOI lateral diodes, MOSFETs and SiGe Transistors.
摘要翻译：一种用于形成具有优异的ESD保护特性的半导体器件的方法和系统。电阻材料层设置在触头螺柱上下表面中的至少一个上的接触孔内。在优选实施例中，积分电阻器的电阻值介于约1欧姆至约10欧姆之间，或10欧姆至100欧姆之间。电阻层的实施例包括溅射硅材料，隧道氧化物，隧道氮化物，硅注入氧化物，注入硅的氮化物或非晶多晶硅。本发明的实施例包括SRAM，双极晶体管，SOI横向二极管，MOSFET和SiGe晶体管。

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