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1. 发明授权

US07633785B2 Semiconductor memory device and method of generating chip enable signal thereof 有权
标题翻译：半导体存储器件及其制造芯片使能信号的方法
公开(公告)号：US07633785B2
公开(公告)日：2009-12-15
申请号：US11775245
申请日：2007-07-10
申请人： Doo-Gon Kim , Youn-Cheul Kim
发明人： Doo-Gon Kim , Youn-Cheul Kim
IPC分类号： G11C5/02
CPC分类号： H03K19/20 , G11C7/1045 , G11C7/20 , G11C7/22
摘要： Provided are a semiconductor memory device and a method of generating a chip enable signal thereof. The device includes a plurality of memory chips and an interface chip that are stacked. Each of the memory chips includes a control signal setting unit, which sets input signals applied to first and second input nodes as less significant 2-bit control signals of n-bit control signals, performs a logic AND operation on the less significant 2-bit control signals to generate AND operated signals, performs a logic XOR operation on each of the AND operated signals and each bit signal of more significant n−2-bit input signals applied to third to n-th input nodes to set the n−2-bit control signals, outputs the signal applied to the second input node through a first output node, inverts the signal applied to the first input node to output the inverted signal through a second output node, and outputs the more significant n−2-bit input signals through third through n-th output nodes, respectively. The first through n-th output nodes of one of two adjacent memory chips are respectively connected to the first through n-th input nodes of the other of the two adjacent memory chips.
摘要翻译：提供一种半导体存储器件及其产生芯片使能信号的方法。该装置包括堆叠的多个存储器芯片和接口芯片。每个存储器芯片包括控制信号设置单元，其将施加到第一和第二输入节点的输入信号设置为较低有效的n位控制信号的2位控制信号，对较不重要的2位执行逻辑与运算控制信号以产生与操作信号，对每个AND运算信号和施加到第三至第n输入节点的更有效的n-2位输入信号的每个比特信号执行逻辑异或运算，以设置n-2- 通过第一输出节点输出施加到第二输入节点的信号，将施加到第一输入节点的信号反相，通过第二输出节点输出反相信号，并输出更重要的n-2位输入分别通过第三到第n个输出节点发出信号。两个相邻存储器芯片中的一个的第一至第n输出节点分别连接到两个相邻存储器芯片中另一个的第一至第n输入节点。

2. 发明授权

US08531909B2 Delay-locked loop having loop bandwidth dependency on operating frequency 有权
标题翻译：具有环路带宽依赖于工作频率的延迟锁定环路
公开(公告)号：US08531909B2
公开(公告)日：2013-09-10
申请号：US12818929
申请日：2010-06-18
申请人： Youn-Cheul Kim
发明人： Youn-Cheul Kim
IPC分类号： G11C7/22 , G11C8/18
CPC分类号： G11C7/22 , G11C7/222 , H03L7/0816
摘要： Circuits, methods, and apparatus that vary one or more attributes or parameters of a closed-loop clock circuit as a function of a characteristic of its operating frequency. One example provides a delay-locked loop having a loop bandwidth that can be varied as a function of its operating frequency. In this specific example, operating frequency is determined. This determination may be made directly, either by measuring operating frequency, or indirectly, by taking a measurement or reading, such as by reading a value for column address select latency. Once the operating frequency is determined, the loop bandwidth can be set. In one example, the loop bandwidth is set by adjusting the depth of the delay-locked loop's loop filter.
摘要翻译：根据其工作频率的特性，改变闭环时钟电路的一个或多个属性或参数的电路，方法和装置。一个示例提供具有可以作为其工作频率的函数而变化的环路带宽的延迟锁定环路。在该具体示例中，确定工作频率。可以通过测量操作频率或间接地通过进行测量或读取来例如通过读取列地址选择延迟的值来直接进行该确定。一旦确定了工作频率，就可以设置环路带宽。在一个示例中，通过调整延迟锁定环的环路滤波器的深度来设置环路带宽。

3. 发明授权

US07433263B2 Multi-port semiconductor device and method thereof 有权
标题翻译：多端口半导体器件及其方法
公开(公告)号：US07433263B2
公开(公告)日：2008-10-07
申请号：US11798709
申请日：2007-05-16
申请人： Youn-Cheul Kim
发明人： Youn-Cheul Kim
IPC分类号： G11C8/00
CPC分类号： G11C7/1075 , G11C7/22 , G11C7/222
摘要： A multi-port semiconductor device and method thereof are provided. In an example, the multi-port memory device may include a clock generating unit receiving an external clock signal having a given frequency and a given phase, the clock generating unit generating a plurality of local clock signals by adjusting at least one of the given frequency and given phrase of the received external clock signal such that at least one of the plurality of local clock signals have at least one of a different frequency and a different phase as compared to the given frequency and given phrase, respectively, of the received external clock signal.
摘要翻译：提供了一种多端口半导体器件及其方法。在一个示例中，多端口存储器件可以包括时钟产生单元，其接收具有给定频率和给定相位的外部时钟信号，时钟产生单元通过调整给定频率中的至少一个来产生多个本地时钟信号并且给出所接收的外部时钟信号的短语，使得与所分配的接收的外部时钟的给定频率和给定短语相比，多个本地时钟信号中的至少一个分别具有不同频率和不同相位中的至少一个信号。

4. 发明申请

US20110309866A1 DELAY-LOCKED LOOP HAVING A LOOP BANDWIDTH DEPENDENCY ON PHASE ERROR 有权
标题翻译：延迟锁定环路具有相位误差的带宽依赖性
公开(公告)号：US20110309866A1
公开(公告)日：2011-12-22
申请号：US12818945
申请日：2010-06-18
申请人： Youn-Cheul Kim
发明人： Youn-Cheul Kim
IPC分类号： H03L7/06
CPC分类号： G11C8/18 , H03L7/00 , H03L7/0812 , H03L7/10
摘要： Circuits, methods, and apparatus that vary one or more attributes or parameters of a closed-loop clock circuit as a function of a characteristic of its phase error. One example provides a delay-locked loop having a loop bandwidth that can be varied as a function of its phase error. In this specific example, current phase error is determined. This determination may be made directly, either by measuring phase error, or indirectly, by determining if phase error is within one or more ranges of values. Once the phase error is determined, the loop bandwidth can be set. In one example, the loop bandwidth is set by adjusting the depth, type, or depth and type of the delay-locked loop's loop filter. In this way, large phase errors can be reduced quickly by increasing loop bandwidth, while small phase errors can be used to decrease loop bandwidth, thereby improving jitter performance.
摘要翻译：作为其相位误差的特征的函数，可以改变闭环时钟电路的一个或多个属性或参数的电路，方法和装置。一个示例提供具有可以作为其相位误差的函数而变化的环路带宽的延迟锁定环路。在该具体示例中，确定当前相位误差。可以通过测量相位误差或间接地通过确定相位误差是否在一个或多个值范围内来直接进行该确定。一旦确定了相位误差，就可以设置环路带宽。在一个示例中，通过调整延迟锁定环的环路滤波器的深度，类型，深度和类型来设置环路带宽。以这种方式，可以通过增加环路带宽来快速减小大相位误差，而可以使用小的相位误差来降低环路带宽，从而提高抖动性能。

5. 发明授权

US07441167B2 Memory module with parallel testing 失效
公开(公告)号：US07441167B2
公开(公告)日：2008-10-21
申请号：US11811551
申请日：2007-06-11
申请人： Youn-Cheul Kim , Hee-Joo Choi , Kae-Won Ha , Joon-Hee Lee
发明人： Youn-Cheul Kim , Hee-Joo Choi , Kae-Won Ha , Joon-Hee Lee
IPC分类号： G11C29/00
CPC分类号： G11C29/40 , G11C29/28 , G11C2029/2602
摘要： Each memory chip of a memory module tests a total of N data bits from X memory blocks for efficient testing and outputs N/X data bits from one of the memory blocks. A memory module includes a plurality of memory chips and a plurality of comparison units. Each comparison unit is disposed within a respective memory chip for testing a plurality of data bits from a plurality of memory blocks. In addition, each comparison unit outputs data bits from one of the memory blocks within the respective memory chip.

6. 发明申请

US20070201297A1 Multi-port memory device and method of controlling the same 有权
标题翻译：多端口存储器件及其控制方法
公开(公告)号：US20070201297A1
公开(公告)日：2007-08-30
申请号：US11375568
申请日：2006-03-15
申请人： Youn-Cheul Kim
发明人： Youn-Cheul Kim
IPC分类号： G11C8/00
CPC分类号： G11C8/16 , G11C7/1075 , G11C7/22 , G11C7/222 , G11C11/12
摘要： A multi-port memory device providing various frequencies for ports is disclosed. The multi-port memory device includes a memory core, a clock generator and a plurality of ports. The clock generator generates an internal clock signal based on an external clock signal. Each of the ports has a local clock generator that generates a local clock signal having a predetermined frequency based on the internal clock signal and accesses the memory core in response to the local clock signal. The multi-port memory device may generate various frequencies for ports without increasing the number of pins for receiving clock signals.
摘要翻译：公开了一种为端口提供各种频率的多端口存储器件。多端口存储器件包括存储器核心，时钟发生器和多个端口。时钟发生器基于外部时钟信号产生内部时钟信号。每个端口具有本地时钟发生器，其基于内部时钟信号产生具有预定频率的本地时钟信号，并且响应于本地时钟信号访问存储器核心。多端口存储器装置可以在不增加用于接收时钟信号的引脚数量的情况下为端口生成各种频率。

7. 发明授权

US08513991B2 Delay-locked loop having a loop bandwidth dependency on phase error 有权
标题翻译：具有循环带宽依赖于相位误差的延迟锁定环路
公开(公告)号：US08513991B2
公开(公告)日：2013-08-20
申请号：US12818945
申请日：2010-06-18
申请人： Youn-Cheul Kim
发明人： Youn-Cheul Kim
IPC分类号： H03L7/06
CPC分类号： G11C8/18 , H03L7/00 , H03L7/0812 , H03L7/10
摘要： Circuits, methods, and apparatus that vary one or more attributes or parameters of a closed-loop clock circuit as a function of a characteristic of its phase error. One example provides a delay-locked loop having a loop bandwidth that can be varied as a function of its phase error. In this specific example, current phase error is determined. This determination may be made directly, either by measuring phase error, or indirectly, by determining if phase error is within one or more ranges of values. Once the phase error is determined, the loop bandwidth can be set. In one example, the loop bandwidth is set by adjusting the depth, type, or depth and type of the delay-locked loop's loop filter. In this way, large phase errors can be reduced quickly by increasing loop bandwidth, while small phase errors can be used to decrease loop bandwidth, thereby improving jitter performance.
摘要翻译：作为其相位误差的特征的函数，可以改变闭环时钟电路的一个或多个属性或参数的电路，方法和装置。一个示例提供具有可以作为其相位误差的函数而变化的环路带宽的延迟锁定环路。在该具体示例中，确定当前相位误差。可以通过测量相位误差或间接地通过确定相位误差是否在一个或多个值范围内来直接进行该确定。一旦确定了相位误差，就可以设置环路带宽。在一个示例中，通过调整延迟锁定环的环路滤波器的深度，类型，深度和类型来设置环路带宽。以这种方式，可以通过增加环路带宽来快速减小大相位误差，而可以使用小的相位误差来降低环路带宽，从而提高抖动性能。

8. 发明申请

US20110310682A1 DELAY-LOCKED LOOP HAVING LOOP BANDWIDTH DEPENDENCY ON OPERATING FREQUENCY 有权
标题翻译：具有环路带宽的延迟环路操作频率依赖
公开(公告)号：US20110310682A1
公开(公告)日：2011-12-22
申请号：US12818929
申请日：2010-06-18
申请人： Youn-Cheul Kim
发明人： Youn-Cheul Kim
IPC分类号： G11C7/00 , H03L7/06
CPC分类号： G11C7/22 , G11C7/222 , H03L7/0816
摘要： Circuits, methods, and apparatus that vary one or more attributes or parameters of a closed-loop clock circuit as a function of a characteristic of its operating frequency. One example provides a delay-locked loop having a loop bandwidth that can be varied as a function of its operating frequency. In this specific example, operating frequency is determined. This determination may be made directly, either by measuring operating frequency, or indirectly, by taking a measurement or reading, such as by reading a value for column address select latency. Once the operating frequency is determined, the loop bandwidth can be set. In one example, the loop bandwidth is set by adjusting the depth of the delay-locked loop's loop filter.
摘要翻译：根据其工作频率的特性，改变闭环时钟电路的一个或多个属性或参数的电路，方法和装置。一个示例提供具有可以作为其工作频率的函数而变化的环路带宽的延迟锁定环路。在该具体示例中，确定工作频率。可以通过测量操作频率或间接地通过进行测量或读取来例如通过读取列地址选择延迟的值来直接进行该确定。一旦确定了工作频率，就可以设置环路带宽。在一个示例中，通过调整延迟锁定环的环路滤波器的深度来设置环路带宽。

9. 发明授权

US08046665B2 Memory device employing dual clocking for generating systematic code and method thereof 有权
标题翻译：采用双时钟生成系统代码的存储器件及其方法
公开(公告)号：US08046665B2
公开(公告)日：2011-10-25
申请号：US12000837
申请日：2007-12-18
申请人： Hoe-ju Chung , Youn-Cheul Kim
发明人： Hoe-ju Chung , Youn-Cheul Kim
IPC分类号： G11C29/00
CPC分类号： G06F11/1004
摘要： A memory device may include a memory core block, a data patch unit, a Cyclic Redundancy Check (CRC) generating unit, and/or a serializer. The data patch unit may be configured to patch parallel data read from the memory core block in response to a first read pulse. The CRC generating unit may be configured to generate the CRC code based on the parallel data in response to a second read pulse, the second read pulse delayed by a period of time from if the first read pulse is generated. The serializer may be configured to convert the parallel data to serial data in response to the first read pulse, and/or arrange the CRC code in a order for a number of bits of the serial data to generate a systematic code.
摘要翻译：存储器设备可以包括存储器核心块，数据块单元，循环冗余校验（CRC）生成单元和/或串行器。数据补丁单元可以被配置为响应于第一读取脉冲来对从存储器核心块读取的并行数据进行补丁。 CRC生成单元可以被配置为响应于第二读取脉冲而基于并行数据生成CRC代码，第二读取脉冲从产生第一读取脉冲的时间段延迟了一段时间。序列化器可以被配置为响应于第一读取脉冲将并行数据转换为串行数据，和/或按照串行数据的位的顺序排列CRC码以生成系统代码。

10. 发明申请

US20070242554A1 Multi-port semiconductor device and method thereof 有权
标题翻译：多端口半导体器件及其方法
公开(公告)号：US20070242554A1
公开(公告)日：2007-10-18
申请号：US11798709
申请日：2007-05-16
申请人： Youn-Cheul Kim
发明人： Youn-Cheul Kim
IPC分类号： G11C8/00
CPC分类号： G11C7/1075 , G11C7/22 , G11C7/222
摘要： A multi-port semiconductor device and method thereof are provided. In an example, the multi-port memory device may include a clock generating unit receiving an external clock signal having a given frequency and a given phase, the clock generating unit generating a plurality of local clock signals by adjusting at least one of the given frequency and given phrase of the received external clock signal such that at least one of the plurality of local clock signals have at least one of a different frequency and a different phase as compared to the given frequency and given phrase, respectively, of the received external clock signal.
摘要翻译：提供了一种多端口半导体器件及其方法。在一个示例中，多端口存储器件可以包括时钟产生单元，其接收具有给定频率和给定相位的外部时钟信号，时钟产生单元通过调整给定频率中的至少一个来产生多个本地时钟信号并且给出所接收的外部时钟信号的短语，使得与所分配的接收的外部时钟的给定频率和给定短语相比，多个本地时钟信号中的至少一个分别具有不同频率和不同相位中的至少一个信号。

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