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1. 发明授权

US07441167B2 Memory module with parallel testing 失效
公开(公告)号：US07441167B2
公开(公告)日：2008-10-21
申请号：US11811551
申请日：2007-06-11
申请人： Youn-Cheul Kim , Hee-Joo Choi , Kae-Won Ha , Joon-Hee Lee
发明人： Youn-Cheul Kim , Hee-Joo Choi , Kae-Won Ha , Joon-Hee Lee
IPC分类号： G11C29/00
CPC分类号： G11C29/40 , G11C29/28 , G11C2029/2602
摘要： Each memory chip of a memory module tests a total of N data bits from X memory blocks for efficient testing and outputs N/X data bits from one of the memory blocks. A memory module includes a plurality of memory chips and a plurality of comparison units. Each comparison unit is disposed within a respective memory chip for testing a plurality of data bits from a plurality of memory blocks. In addition, each comparison unit outputs data bits from one of the memory blocks within the respective memory chip.

2. 发明授权

US07246280B2 Memory module with parallel testing 失效
标题翻译：内存模块并行测试
公开(公告)号：US07246280B2
公开(公告)日：2007-07-17
申请号：US11086059
申请日：2005-03-22
申请人： Youn-Cheul Kim , Hee-Joo Choi , Kae-Won Ha , Joon-Hee Lee
发明人： Youn-Cheul Kim , Hee-Joo Choi , Kae-Won Ha , Joon-Hee Lee
IPC分类号： G11C29/00
CPC分类号： G11C29/40 , G11C29/28 , G11C2029/2602
摘要： Each memory chip of a memory module tests a total of N data bits from X memory blocks for efficient testing and outputs N/X test data bits from one of the memory blocks. A memory module includes a plurality of memory chips and a plurality of comparison units. Each comparison unit is disposed within a respective memory chip for testing a plurality of test data bits from a plurality of memory blocks. In addition, each comparison unit outputs test data bits from one of the memory blocks within the respective memory chip.
摘要翻译：存储器模块的每个存储器芯片测试来自X个存储器块的总共N个数据位用于有效测试，并从其中一个存储器块输出N / X个测试数据位。存储器模块包括多个存储器芯片和多个比较单元。每个比较单元设置在相应的存储器芯片内，用于从多个存储器块测试多个测试数据位。此外，每个比较单元从相应的存储器芯片内的一个存储器块输出测试数据位。

3. 发明申请

US20080005631A1 Memory module with parallel testing 失效
标题翻译：内存模块并行测试
公开(公告)号：US20080005631A1
公开(公告)日：2008-01-03
申请号：US11811551
申请日：2007-06-11
申请人： Youn-Cheul Kim , Hee-Joo Choi , Kae-Won Ha , Joon-Hee Lee
发明人： Youn-Cheul Kim , Hee-Joo Choi , Kae-Won Ha , Joon-Hee Lee
IPC分类号： G11C29/08
CPC分类号： G11C29/40 , G11C29/28 , G11C2029/2602
摘要： Each memory chip of a memory module tests a total of N data bits from X memory blocks for efficient testing and outputs N/X data bits from one of the memory blocks. A memory module includes a plurality of memory chips and a plurality of comparison units. Each comparison unit is disposed within a respective memory chip for testing a plurality of data bits from a plurality of memory blocks. In addition, each comparison unit outputs data bits from one of the memory blocks within the respective memory chip.
摘要翻译：存储器模块的每个存储器芯片测试来自X个存储器块的总共N个数据位用于有效测试，并从其中一个存储器块输出N / X数据位。存储器模块包括多个存储器芯片和多个比较单元。每个比较单元设置在相应的存储器芯片内，用于从多个存储器块测试多个数据位。此外，每个比较单元从相应的存储器芯片内的一个存储块输出数据位。

4. 发明申请

US20050216809A1 Memory module with parallel testing 失效
标题翻译：内存模块并行测试
公开(公告)号：US20050216809A1
公开(公告)日：2005-09-29
申请号：US11086059
申请日：2005-03-22
申请人： Youn-Cheul Kim , Hee-Joo Choi , Kae-Won Ha , Joon-Hee Lee
发明人： Youn-Cheul Kim , Hee-Joo Choi , Kae-Won Ha , Joon-Hee Lee
IPC分类号： G01R31/28 , G06F11/00 , G06F12/16 , G11C29/00 , G11C29/28 , G11C29/34 , G11C29/40
CPC分类号： G11C29/40 , G11C29/28 , G11C2029/2602
摘要： Each memory chip of a memory module tests a total of N data bits from X memory blocks for efficient testing and outputs N/X test data bits from one of the memory blocks. A memory module includes a plurality of memory chips and a plurality of comparison units. Each comparison unit is disposed within a respective memory chip for testing a plurality of test data bits from a plurality of memory blocks. In addition, each comparison unit outputs test data bits from one of the memory blocks within the respective memory chip.
摘要翻译：存储器模块的每个存储器芯片测试来自X个存储器块的总共N个数据位用于有效测试，并从其中一个存储器块输出N / X个测试数据位。存储器模块包括多个存储器芯片和多个比较单元。每个比较单元设置在相应的存储器芯片内，用于从多个存储器块测试多个测试数据位。此外，每个比较单元从相应的存储器芯片内的一个存储器块输出测试数据位。

5. 发明授权

US09231593B2 Apparatus for compensating for process variation of resistor in electronic circuit 有权
标题翻译：用于补偿电子电路中电阻器工艺变化的装置
公开(公告)号：US09231593B2
公开(公告)日：2016-01-05
申请号：US13270384
申请日：2011-10-11
申请人： Jeong-Ho Lee , Seung-Pyo Hong , Ju-Ho Son , Seung-Ho Jang , Hyun-Tae Gill , Joon-Hee Lee , Yi-Ju Roh
发明人： Jeong-Ho Lee , Seung-Pyo Hong , Ju-Ho Son , Seung-Ho Jang , Hyun-Tae Gill , Joon-Hee Lee , Yi-Ju Roh
IPC分类号： H03L5/00 , H03K19/003
CPC分类号： H03K19/00384
摘要： An electronic circuit apparatus for compensating for a process variation of a resistor in an electronic circuit is provided. The electronic circuit includes a detecting part for generating a tune voltage corresponding to a process variation value of the at least one resistor, and a compensating part for compensating for a process variation of the at least one resistor using the tune voltage.
摘要翻译：提供了用于补偿电子电路中的电阻器的工艺变化的电子电路装置。电子电路包括用于产生对应于至少一个电阻器的过程变化值的调谐电压的检测部分和用于使用调谐电压来补偿至少一个电阻器的工艺变化的补偿部分。

6. 发明申请

US20120142177A1 METHODS OF MANUFACTURING A WIRING STRUCTURE AND METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造布线结构的方法及制造半导体器件的方法
公开(公告)号：US20120142177A1
公开(公告)日：2012-06-07
申请号：US13299538
申请日：2011-11-18
申请人： Jee-Yong Kim , Joon-Hee Lee , Jeong-Hyuk Choi , Jai-Hyuk Song , Seung-Wan Hong , Hwa-Eon Shin , Jong-Hyun Park , Woo-Jung Kim , Jae-Sung Ahn , Jung-Hwan Lee
发明人： Jee-Yong Kim , Joon-Hee Lee , Jeong-Hyuk Choi , Jai-Hyuk Song , Seung-Wan Hong , Hwa-Eon Shin , Jong-Hyun Park , Woo-Jung Kim , Jae-Sung Ahn , Jung-Hwan Lee
IPC分类号： H01L21/28
CPC分类号： H01L29/78 , H01L21/76826 , H01L21/76828 , H01L21/76834 , H01L21/76849 , H01L27/10855 , H01L27/10885 , H01L27/10894 , H01L27/11543
摘要： A method of manufacturing a wiring structure and a semiconductor device, the method of manufacturing a wiring structure including forming a first insulating interlayer on a substrate; forming a contact plug in an opening in the first insulating interlayer; forming a second insulating interlayer on the contact plug and the first insulating interlayer; removing a portion of the second insulating interlayer to form an opening therethrough such that the opening exposes the contact plug; filling a portion of the opening to form a wiring such that the wiring is electrically connected to the contact plug; and forming a diffusion barrier layer pattern on the wiring such that the diffusion barrier layer pattern fills a remaining portion of the opening.
摘要翻译：一种制造布线结构和半导体器件的方法，包括在基板上形成第一绝缘中间层的布线结构的制造方法; 在所述第一绝缘夹层中的开口中形成接触塞; 在所述接触塞和所述第一绝缘夹层上形成第二绝缘中间层; 去除所述第二绝缘中间层的一部分以形成穿过其中的开口，使得所述开口暴露所述接触插塞; 填充开口的一部分以形成布线，使得布线电连接到接触插塞; 以及在所述布线上形成扩散阻挡层图案，使得所述扩散阻挡层图案填充所述开口的剩余部分。

7. 发明授权

US07898007B2 Semiconductor devices including line patterns separated by cutting regions 有权
标题翻译：半导体器件包括由切割区分开的线图案
公开(公告)号：US07898007B2
公开(公告)日：2011-03-01
申请号：US11961551
申请日：2007-12-20
申请人： Sung-Bok Lee , Joon-Hee Lee
发明人： Sung-Bok Lee , Joon-Hee Lee
IPC分类号： H01L23/52
CPC分类号： H01L27/11568 , H01L27/0207 , H01L27/115
摘要： Semiconductor devices are provided. A semiconductor device can include a substrate and a plurality of dummy line patterns on the substrate that extend in a first direction parallel with one another. Each of the dummy line patterns can include a plurality of sub-line patterns aligned along the first direction and which are separated from each other by at least one cutting region therebetween. The dummy line patterns can include first and second dummy line patterns which are adjacent to each other in a second direction that is perpendicular to the first direction. At least one of the cutting regions between a pair of sub-line patterns of the first dummy line pattern is aligned with and bounded by one of the sub-line patterns of the second dummy line pattern in the second direction.
摘要翻译：提供半导体器件。半导体器件可以包括衬底和在基板上的彼此平行的第一方向上延伸的多个虚拟线图案。虚线图案中的每一个可以包括沿着第一方向排列的多个子线图案，并且通过其间的至少一个切割区域彼此分离。假线图案可以包括在垂直于第一方向的第二方向上彼此相邻的第一和第二假线图案。第一虚线图案的一对子线图案之间的切割区域中的至少一个与第二虚线图案的第二方向上的一条子线图形对准并限定在第二方向上。

8. 发明申请

US20070108498A1 Non-volatile memory devices having floating gates and related methods of forming the same 失效
标题翻译：具有浮动栅极的非易失性存储器件及其相关方法
公开(公告)号：US20070108498A1
公开(公告)日：2007-05-17
申请号：US11594327
申请日：2006-11-08
申请人： Joon-Hee Lee , Jong-Ho Park , Jin-Hyun Shin , Sung-Hoi Hur , Yong-Seok Kim , Jong-Won Kim
发明人： Joon-Hee Lee , Jong-Ho Park , Jin-Hyun Shin , Sung-Hoi Hur , Yong-Seok Kim , Jong-Won Kim
IPC分类号： H01L29/788
CPC分类号： H01L29/7881 , H01L27/115 , H01L27/11521 , H01L29/42324
摘要： A nonvolatile memory device may include a substrate having a cell region, and a cell device isolation layer on the cell region of the substrate to define a cell active region. A floating gate may include a lower floating gate and an upper floating gate sequentially stacked on the cell active region, and a tunnel insulation pattern may be between the floating gate and the cell active region. A control gate electrode may be on the floating gate, and a blocking insulation pattern may be between the control gate electrode and the floating gate. More particularly, the upper floating gate may include a flat portion on the lower floating gate and a pair of wall portions extending upward from both edges of the flat portion adjacent to the cell device isolation layer. Moreover, a width of an upper portion of a space surrounded by the flat portion and the pair of wall portions may be larger than a width of a lower portion of the space. Related methods are also discussed.
摘要翻译：非易失性存储器件可以包括具有单元区域的衬底和在衬底的单元区域上的单元器件隔离层，以限定电池活性区域。浮置栅极可以包括顺序堆叠在单元有源区上的下浮置栅极和上浮置栅极，并且隧道绝缘图案可以在浮栅和电池有源区之间。控制栅极电极可以在浮置栅极上，并且阻挡绝缘图案可以在控制栅电极和浮栅之间。更具体地说，上部浮动栅极可以包括在下部浮动栅极上的平坦部分和从邻近电池器件隔离层的平坦部分的两个边缘向上延伸的一对壁部分。此外，由平坦部分和一对壁部分围绕的空间的上部的宽度可以大于空间的下部的宽度。还讨论了相关方法。

9. 发明授权

US09484354B2 Semiconductor device including different orientations of memory cell array and peripheral circuit transistors 有权
标题翻译：包括存储单元阵列和外围电路晶体管的不同取向的半导体器件
公开(公告)号：US09484354B2
公开(公告)日：2016-11-01
申请号：US14637538
申请日：2015-03-04
申请人： Sung-Hun Lee , Jong-Ho Park , Joon-Hee Lee , Hee-Jueng Lee
发明人： Sung-Hun Lee , Jong-Ho Park , Joon-Hee Lee , Hee-Jueng Lee
IPC分类号： H01L29/792 , H01L27/115 , H01L29/04
CPC分类号： H01L27/11573 , H01L27/11565 , H01L27/11575 , H01L27/11582 , H01L29/045
摘要： A memory device includes a memory cell on a first region of a substrate. An active region is in a second region neighboring the first region of the substrate, and an extension direction of the active region has an acute angle with the direction of the substrate. A transistor serving as a peripheral circuit is on the second region of the substrate. In the memory device, defects or failures due to a crystal defects or a dislocation of the substrate may decrease.
摘要翻译：存储器件包括在衬底的第一区域上的存储器单元。有源区域位于与衬底的第一区域相邻的第二区域中，并且有源区域的延伸方向与衬底的<110>方向成锐角。用作外围电路的晶体管位于衬底的第二区域上。在存储器件中，由于晶体缺陷或衬底的位错导致的缺陷或故障可能降低。

10. 发明授权

US09281414B2 Vertical cell-type semiconductor device having protective pattern 有权
标题翻译：具有保护图案的垂直单元型半导体器件
公开(公告)号：US09281414B2
公开(公告)日：2016-03-08
申请号：US14151288
申请日：2014-01-09
申请人： Jin-Yeon Won , Joon-Hee Lee , Seung-Woo Paek , Dong-Seog Eun
发明人： Jin-Yeon Won , Joon-Hee Lee , Seung-Woo Paek , Dong-Seog Eun
IPC分类号： H01L29/792 , H01L27/115 , H01L29/66
CPC分类号： H01L29/42344 , H01L27/1157 , H01L27/11582 , H01L29/66833 , H01L29/7926
摘要： According to example embodiments of inventive concepts, a semiconductor device includes: a substrate, and a stacked structure including interlayer insulating layers and gate electrodes alternately stacked on the substrate. The stacked structure defines a through-hole over the substrate. The gate electrodes each include a first portion between the through-hole and a second portion of the gate electrodes. A channel pattern may be in the through-hole. A tunneling layer may surround the channel pattern. A charge trap layer may surround the tunneling layer, and protective patterns may surround the first portions of the gate electrodes. The protective patterns may be between the first portions of the gate electrodes and the charge trap layer.
摘要翻译：根据本发明构思的示例性实施例，半导体器件包括：衬底，以及包括层间绝缘层和交替层叠在衬底上的栅电极的堆叠结构。堆叠结构在衬底上限定通孔。栅电极各自包括在通孔和栅电极的第二部分之间的第一部分。通道图案可以在通孔中。隧道层可围绕通道图案。电荷陷阱层可围绕隧道层，并且保护图案可围绕栅电极的第一部分。保护图案可以在栅电极的第一部分和电荷陷阱层之间。

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