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1. 发明授权

US08677099B2 Reconfigurable processor with predicate signal activated operation configuration memory and separate routing configuration memory 有权
标题翻译：具有谓词信号的可重配置处理器激活操作配置存储器和单独的路由配置存储器
公开(公告)号：US08677099B2
公开(公告)日：2014-03-18
申请号：US12563350
申请日：2009-09-21
申请人： Il-hyun Park , Soo-jung Ryu , Dong-hoon Yoo , Yeon-gon Cho , Bernhard Egger , Woong Seo
发明人： Il-hyun Park , Soo-jung Ryu , Dong-hoon Yoo , Yeon-gon Cho , Bernhard Egger , Woong Seo
IPC分类号： G06F9/30
CPC分类号： G06F15/7867 , G06F9/30072 , Y02D10/12 , Y02D10/13
摘要： Provided are a reconfigurable processor and operating method thereof. The reconfigurable processor may use a configuration memory distributed to each operation unit. The distributed configuration memory may be separated into a distributed operation configuration memory including configuration information about an operation of a function unit, and a distributed routing configuration memory including configuration information about routing. The distributed operation configuration memory may be activated according to a predicate signal.
摘要翻译：提供了一种可重构处理器及其操作方法。可重构处理器可以使用分配给每个操作单元的配置存储器。分布式配置存储器可以被分成包括关于功能单元的操作的配置信息的分布式操作配置存储器，以及包括关于路由的配置信息的分布式路由配置存储器。可以根据谓词信号激活分布式操作配置存储器。

2. 发明授权

US08516231B2 Interrupt handling apparatus and method for equal-model processor and processor including the interrupt handling apparatus 有权
标题翻译：包含中断处理装置的等模型处理器和处理器的中断处理装置和方法
公开(公告)号：US08516231B2
公开(公告)日：2013-08-20
申请号：US12695266
申请日：2010-01-28
申请人： Il-hyun Park , Soo-jung Ryu , Dong-hoon Yoo , Yeon-gon Cho , Bernhard Egger
发明人： Il-hyun Park , Soo-jung Ryu , Dong-hoon Yoo , Yeon-gon Cho , Bernhard Egger
IPC分类号： G06F15/00 , G06F9/00 , G06F9/44
CPC分类号： G06F9/3836 , G06F9/327
摘要： An interrupt support determining apparatus and method for an equal-model processor, and a processor including the interrupt support determining apparatus are provided. The interrupt support determining apparatus determines whether an instruction input to a processor decoder is a multiple latency instruction, compares a current latency of the instruction with a remaining latency if the instruction is a multiple latency instruction, and updates the current latency to the remaining latency if the current latency is greater than the remaining latency.
摘要翻译：提供了一种用于等模型处理器的中断支持确定装置和方法，以及包括中断支持确定装置的处理器。中断支持确定装置确定输入到处理器解码器的指令是否是多等待时间指令，如果指令是多等待时间指令，则将指令的当前等待时间与剩余延迟进行比较，并将当前等待时间更新为剩余延迟，如果当前的延迟大于剩余的延迟。

3. 发明申请

US20100174885A1 RECONFIGURABLE PROCESSOR AND OPERATING METHOD OF THE SAME 有权
标题翻译：可重构加工器及其操作方法
公开(公告)号：US20100174885A1
公开(公告)日：2010-07-08
申请号：US12563350
申请日：2009-09-21
申请人： Il-hyun PARK , Soo-jung Ryu , Dong-hoon Yoo , Yeon-gon Cho , Bernhard Egger , Woon Seo
发明人： Il-hyun PARK , Soo-jung Ryu , Dong-hoon Yoo , Yeon-gon Cho , Bernhard Egger , Woon Seo
IPC分类号： G06F15/76 , G06F9/00
CPC分类号： G06F15/7867 , G06F9/30072 , Y02D10/12 , Y02D10/13
摘要： Provided are a reconfigurable processor and operating method thereof. The reconfigurable processor may use a configuration memory distributed to each operation unit. The distributed configuration memory may be separated into a distributed operation configuration memory including configuration information about an operation of a function unit, and a distributed routing configuration memory including configuration information about routing. The distributed operation configuration memory may be activated according to a predicate signal.
摘要翻译：提供了一种可重构处理器及其操作方法。可重构处理器可以使用分配给每个操作单元的配置存储器。分布式配置存储器可以被分成包括关于功能单元的操作的配置信息的分布式操作配置存储器，以及包括关于路由的配置信息的分布式路由配置存储器。可以根据谓词信号激活分布式操作配置存储器。

4. 发明授权

US08495345B2 Computing apparatus and method of handling interrupt 有权
标题翻译：处理中断的计算设备和方法
公开(公告)号：US08495345B2
公开(公告)日：2013-07-23
申请号：US12639663
申请日：2009-12-16
申请人： Dong-hoon Yoo , Soo-jung Ryu , Yeon-gon Cho , Bernhard Egger , Il-hyun Park
发明人： Dong-hoon Yoo , Soo-jung Ryu , Yeon-gon Cho , Bernhard Egger , Il-hyun Park
IPC分类号： G06F15/80
CPC分类号： G06F9/3879 , G06F9/4812
摘要： A computing apparatus and method of handling an interrupt are provided. The computing apparatus includes a coarse-grained array, a host processor, and an interrupt supervisor. When an interrupt occurs in the coarse-grained array while performing a loop operation, the host processor processes the interrupt, and the interrupt supervisor may perform mode switching between the coarse-grained array and the host processor.
摘要翻译：提供了一种处理中断的计算装置和方法。计算装置包括粗粒子阵列，主处理器和中断主管。当执行循环操作时，在粗粒度阵列中发生中断时，主机处理器处理中断，中断主管可以在粗粒度阵列与主机处理器之间执行模式切换。

5. 发明申请

US20100199076A1 COMPUTING APPARATUS AND METHOD OF HANDLING INTERRUPT 有权
标题翻译：计算机和处理中断方法
公开(公告)号：US20100199076A1
公开(公告)日：2010-08-05
申请号：US12639663
申请日：2009-12-16
申请人： Dong-hoon YOO , Soo-jung Ryu , Yeon-gon Cho , Bernhard Egger , Il-hyun Park
发明人： Dong-hoon YOO , Soo-jung Ryu , Yeon-gon Cho , Bernhard Egger , Il-hyun Park
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3879 , G06F9/4812
摘要： A computing apparatus and method of handling an interrupt are provided. The computing apparatus includes a coarse-grained array, a host processor, and an interrupt supervisor. When an interrupt occurs in the coarse-grained array while performing a loop operation, the host processor processes the interrupt, and the interrupt supervisor may perform mode switching between the coarse-grained array and the host processor.
摘要翻译：提供了一种处理中断的计算装置和方法。计算装置包括粗粒子阵列，主处理器和中断主管。当执行循环操作时，在粗粒度阵列中发生中断时，主机处理器处理中断，中断主管可以在粗粒度阵列与主机处理器之间执行模式切换。

6. 发明授权

US07577218B2 Signal acquisition apparatus and method for reducing false alarm rate 失效
标题翻译：用于降低误报率的信号采集装置和方法
公开(公告)号：US07577218B2
公开(公告)日：2009-08-18
申请号：US11315120
申请日：2005-12-23
申请人： Yun-young Kim , Jae-hyun Koo , Yeon-gon Cho , Jae-ho Roh
发明人： Yun-young Kim , Jae-hyun Koo , Yeon-gon Cho , Jae-ho Roh
IPC分类号： H04B1/10
CPC分类号： H04L27/2656 , H04B1/70755 , H04B1/7077 , H04B1/7093 , H04L7/042 , H04L27/2675
摘要： A signal acquisition apparatus and method for reducing a false alarm rate are disclosed. The apparatus includes a comparator for detecting a first peak by comparing a correlation value of a received signal with a first threshold and detecting second peaks in a sample interval of the detected first peak based on a second threshold which is different from the first threshold. Thus, a signal is acquired based on a number of the detected second peaks. Accordingly, the false alarm rate due to the noise can be reduced while the detection probability is maintained even at a high SNR.
摘要翻译：公开了一种用于降低误报率的信号采集装置和方法。该装置包括比较器，用于通过将接收信号的相关值与第一阈值进行比较来检测第一峰值，并且基于与第一阈值不同的第二阈值检测检测到的第一峰值的采样间隔中的第二峰值。因此，基于检测到的第二峰值的数量获取信号。因此，即使在高信噪比下也能够保持由于噪声引起的误报率，同时保持检测概率。

7. 发明授权

US07571376B2 Viterbi decoder for executing trace-back work in parallel and decoding method 失效
标题翻译：用于并行执行追溯工作的维特比解码器和解码方法
公开(公告)号：US07571376B2
公开(公告)日：2009-08-04
申请号：US11340490
申请日：2006-01-27
申请人： Yeon-gon Cho , Jun-haeng Cho , Dong-won Kwak
发明人： Yeon-gon Cho , Jun-haeng Cho , Dong-won Kwak
IPC分类号： H03M13/03
CPC分类号： H03M13/4169 , H03M13/6502
摘要： A Viterbi decoder for executing a trace-back work in parallel and a decoding method. The Viterbi decoder includes a branch metric calculator which calculates a branch metric from a branch code passing each state on a trellis diagram and a predetermined input code, at least one adder/comparator/selector which adds the branch metric to a path metric of a previous state, detects a minimum value of the addition result values as a path metric of a current state, and detects state transition values corresponding to a path from which the minimum value has been detected, a path metric memory which stores the path metric detected by the at least one adder/comparator/selector, a plurality of trace-back memories which sequentially store the state transition values detected by the at least one adder/comparator/selector, and if the plurality of trace-back memories store the state transition values by a preset trace-back depth, a trace-back controller executes a trace-back work in parallel in each of the plurality of trace-back memories.
摘要翻译：用于并行执行追溯工作的维特比解码器和解码方法。维特比解码器包括一个分支度量计算器，该分支量度计算器从通过格状图和预定输入代码上的每个状态的分支代码计算分支度量，至少一个加法器/比较器/选择器，其将分支度量添加到先前状态，检测相加结果值的最小值作为当前状态的路径度量，并且检测与从其检测到最小值的路径相对应的状态转换值;路径度量存储器，其存储由至少一个加法器/比较器/选择器，多个追溯存储器，其顺序地存储由至少一个加法器/比较器/选择器检测的状态转换值，并且如果多个追溯存储器将状态转换值存储在预设回溯深度，追溯控制器在多个回溯存储器中的每一个中并行地执行追溯工作。

8. 发明申请

US20060140314A1 Signal acquisition apparatus and method for reducing false alarm rate 失效
公开(公告)号：US20060140314A1
公开(公告)日：2006-06-29
申请号：US11315120
申请日：2005-12-23
申请人： Yun-young Kim , Jae-hyun Koo , Yeon-gon Cho , Jae-ho Roh
发明人： Yun-young Kim , Jae-hyun Koo , Yeon-gon Cho , Jae-ho Roh
IPC分类号： H04L27/06
CPC分类号： H04L27/2656 , H04B1/70755 , H04B1/7077 , H04B1/7093 , H04L7/042 , H04L27/2675
摘要： A signal acquisition apparatus and method for reducing a false alarm rate are disclosed. The apparatus includes a comparator for detecting a first peak by comparing a correlation value of a received signal with a first threshold and detecting second peaks in a sample interval of the detected first peak based on a second threshold which is different from the first threshold. Thus, a signal is acquired based on a number of the detected second peaks. Accordingly, the false alarm rate due to the noise can be reduced while the detection probability is maintained even at a high SNR.

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