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1. 发明授权

US09191065B2 Integrated repeater for integratedly relaying various types of communication signals, and integrated relay system 有权
公开(公告)号：US09191065B2
公开(公告)日：2015-11-17
申请号：US13696281
申请日：2011-04-28
申请人： Seok-Young Kong , Dong-Uk Park , Seong-Hee Suh , Jae-Seon Jang
发明人： Seok-Young Kong , Dong-Uk Park , Seong-Hee Suh , Jae-Seon Jang
IPC分类号： H04B3/36 , H04B10/29 , H04B7/155
摘要： The present invention relates to an integrated repeater and an integrated relay system. The integrated repeater of the present invention receives a signal from a main repeater for relaying signals transmitted from upper devices, and comprises a demultiplexer configured to demultiplex the multiplexed signal of an Ethernet signal and a mobile communication signal received from the main repeater, and separate the signals into the mobile communication signal and the Ethernet signal; a first converter configured to convert the mobile communication signal separated from the demultiplexer into a radio frequency (RF) signal, and transmit the converted RF signal; a second converter configured to convert the Ethernet signal separated from the demultiplexer into a wireless LAN signal, and transmit the converted wireless LAN signal; and a switching unit configured to deliver a signal received from the main repeater to either the demultiplexer or the second converter, depending on whether a fault of the mobile communication signal is generated.

2. 发明授权

US08314763B2 Display device transferring data signal with clock 有权
标题翻译：显示设备用时钟传输数据信号
公开(公告)号：US08314763B2
公开(公告)日：2012-11-20
申请号：US12167393
申请日：2008-07-03
申请人： Jae-Jin Park , Dong-Uk Park , Jin-Ho Seo
发明人： Jae-Jin Park , Dong-Uk Park , Jin-Ho Seo
IPC分类号： G09G3/36
CPC分类号： G09G3/2096 , G09G3/3685 , G09G5/008 , G09G2330/06
摘要： A display device includes; a panel, a timing controller generating an embedded clock data signal combining image data and a clock signal, and a column driver driving the panel in response to the embedded clock data signal. The data bits within the embedded clock data signal are communicated at one of three voltage levels in a three-level signaling scheme, and the timing controller determines one of the three voltage levels for a current data bit (DIN[n]) within the embedded clock data signal in relation to a voltage level of a previous data bit (DIN[n−1]) within the embedded clock data signal.
摘要翻译：显示装置包括：面板，产生组合图像数据和时钟信号的嵌入式时钟数据信号的定时控制器和响应于嵌入的时钟数据信号驱动面板的列驱动器。嵌入式时钟数据信号中的数据位以三电平信令方案中的三个电压电平中的一个通信，并且定时控制器确定嵌入式时钟数据信号中当前数据位（DIN [n]）的三个电压电平之一时钟数据信号相对于嵌入式时钟数据信号中的先前数据位（DIN [n-1]）的电压电平。

3. 发明授权

US07248077B2 Current driver circuits for reducing substrate noise and methods of operating the same 失效
标题翻译：用于降低衬底噪声的电流驱动电路及其操作方法
公开(公告)号：US07248077B2
公开(公告)日：2007-07-24
申请号：US11186115
申请日：2005-07-21
申请人： Dong-Uk Park
发明人： Dong-Uk Park
IPC分类号： H03K19/0175
CPC分类号： H03K19/0013 , H03K19/018521
摘要： A current driver circuit includes a pull-down switch unit that is coupled between a node and a first reference potential and is operative to switch between an on-state and an off-state responsive to an input signal. A pull-up switch unit is coupled between the node and a second reference potential and is operative to switch between an on-state and an off-state, complementary to the pull-down switch unit. A turn-on speed of the pull-up switch unit is slower than that of the pull-down switch unit, and a turn-off speed of the pull-up switch unit is faster than that of the pull-down switch unit.
摘要翻译：电流驱动器电路包括耦合在节点和第一参考电位之间并且响应于输入信号在导通状态和截止状态之间切换的下拉开关单元。上拉开关单元耦合在节点和第二参考电位之间，并且可操作以在与下拉开关单元互补的导通状态和截止状态之间切换。上拉开关单元的导通速度比下拉开关单元的开启速度慢，并且上拉开关单元的关断速度比下拉开关单元快。

4. 发明申请

US20060222131A1 Method for sampling reverse data and a reverse data sampling circuit for performing the same 审中-公开
标题翻译：用于对反向数据进行采样的方法和用于执行相反数据的反向数据采样电路
公开(公告)号：US20060222131A1
公开(公告)日：2006-10-05
申请号：US11369033
申请日：2006-03-06
申请人： Dong-Uk Park
发明人： Dong-Uk Park
IPC分类号： H04L7/00
CPC分类号： H04L7/0338
摘要： A method for sampling reverse data and a reverse data sampling circuit for performing the same are provided. The reverse data sampling method of a host interface device includes generating a multi-phase clock; sampling clocks corresponding to respective phases of the multi-phase clock at a transition of a reverse data signal to generate clock sampling signals; sampling the reverse data signal at a transition of the clocks corresponding to the respective phases of the multi-phase clock to generate data sampling signals; selecting a sampling clock from the clocks corresponding to the respective phases of the multi-phase clock by using the clock sampling signals and the data sampling signals; and sampling reverse data at a transition of the sampling clock.
摘要翻译：提供了用于对反向数据进行采样的方法和用于执行相反数据的反向数据采样电路。主机接口装置的反向数据采样方法包括：生成多相时钟; 在反向数据信号的转变处对应于多相时钟的相位的采样时钟，以产生时钟采样信号; 在与多相时钟的相位相对应的时钟的转变处对反向数据信号进行采样，以产生数据采样信号; 通过使用时钟采样信号和数据采样信号从与多相时钟的相位相对应的时钟中选择采样时钟; 并在采样时钟的转变时采样反向数据。

5. 发明申请

US20060214690A1 Current drive circuit and method of boosting current using the same 失效
公开(公告)号：US20060214690A1
公开(公告)日：2006-09-28
申请号：US11363338
申请日：2006-02-27
申请人： Dong-Uk Park
发明人： Dong-Uk Park
IPC分类号： H03K19/094
CPC分类号： H03K19/00384
摘要： A current drive circuit includes a differential voltage detector configured to detect a voltage level of a drive node and configured to compare the voltage level of the drive node with a voltage level of a reference voltage to generate a comparison signal, a control logic circuit configured to generate a control signal to provide a current to the drive node based on the comparison signal, and a current driver configured to provide the current to the drive node or provide the current from the drive node based on the control signal. The voltage level of the drive node rapidly reaches the voltage level of the reference voltage.

6. 发明申请

US20060017464A1 Current driver circuits for reducing substrate noise and methods of operating the same 失效
标题翻译：用于降低衬底噪声的电流驱动电路及其操作方法
公开(公告)号：US20060017464A1
公开(公告)日：2006-01-26
申请号：US11186115
申请日：2005-07-21
申请人： Dong-Uk Park
发明人： Dong-Uk Park
IPC分类号： H03K19/0175
CPC分类号： H03K19/0013 , H03K19/018521
摘要： A current driver circuit includes a pull-down switch unit that is coupled between a node and a first reference potential and is operative to switch between an on-state and an off-state responsive to an input signal. A pull-up switch unit is coupled between the node and a second reference potential and is operative to switch between an on-state and an off-state, complementary to the pull-down switch unit. A turn-on speed of the pull-up switch unit is slower than that of the pull-down switch unit, and a turn-off speed of the pull-up switch unit is faster than that of the pull-down switch unit.
摘要翻译：电流驱动器电路包括耦合在节点和第一参考电位之间并且响应于输入信号在导通状态和截止状态之间切换的下拉开关单元。上拉开关单元耦合在节点和第二参考电位之间，并且可操作以在与下拉开关单元互补的导通状态和截止状态之间切换。上拉开关单元的导通速度比下拉开关单元的开启速度慢，并且上拉开关单元的关断速度比下拉开关单元快。

7. 发明申请

US20130044585A1 INTEGRATED REPEATER FOR INTEGRATEDLY RELAYING VARIOUS TYPES OF COMMUNICATION SIGNALS, AND INTEGRATED RELAY SYSTEM 有权
公开(公告)号：US20130044585A1
公开(公告)日：2013-02-21
申请号：US13696281
申请日：2011-04-28
申请人： Seok-Young Kong , Dong-Uk Park , Seong-Hee Suh , Jae-Seon Jang
发明人： Seok-Young Kong , Dong-Uk Park , Seong-Hee Suh , Jae-Seon Jang
IPC分类号： H04W24/04
CPC分类号： H04W24/04 , H04B3/36 , H04B7/155 , H04B10/29 , H04L12/64 , H04L49/20
摘要： The present invention relates to an integrated repeater and an integrated relay system. The integrated repeater of the present invention receives a signal from a main repeater for relaying signals transmitted from upper devices, and comprises a demultiplexer configured to demultiplex the multiplexed signal of an Ethernet signal and a mobile communication signal received from the main repeater, and separate the signals into the mobile communication signal and the Ethernet signal; a first converter configured to convert the mobile communication signal separated from the demultiplexer into a radio frequency (RF) signal, and transmit the converted RF signal; a second converter configured to convert the Ethernet signal separated from the demultiplexer into a wireless LAN signal, and transmit the converted wireless LAN signal; and a switching unit configured to deliver a signal received from the main repeater to either the demultiplexer or the second converter, depending on whether a fault of the mobile communication signal is generated.

8. 发明申请

US20110292207A1 NETWORK SWITCH CONTROL DIGITAL VIDEO RECORDER 有权
标题翻译：网络切换控制数字视频录像机
公开(公告)号：US20110292207A1
公开(公告)日：2011-12-01
申请号：US13117212
申请日：2011-05-27
申请人： Song-Nam Bae , Dong-Uk Park , Byung-Yun Lee
发明人： Song-Nam Bae , Dong-Uk Park , Byung-Yun Lee
IPC分类号： H04N7/18
CPC分类号： H04N7/181
摘要： A network switch control digital video recorder (DVR) is provided. The network switch control DVR includes a network switch module configured to include a plurality of ports via which data is input to or output from at least one camera, a network storage, an external computer, and a DVR module and to multiplex data input or output via the plurality of ports; and the DVR module configured to control the input or output of data to or from the network switch module by monitoring a state of the input or output of data via the plurality of ports.
摘要翻译：提供网络交换机控制数字录像机（DVR）。网络交换机控制DVR包括网络交换机模块，该网络交换机模块被配置为包括多个端口，经由该端口将数据输入至少一个摄像机，网络存储器，外部计算机和DVR模块，或者从数据输入或输出经由多个端口; 并且所述DVR模块被配置为通过监视经由所述多个端口的数据的输入或输出的状态来控制到/从所述网络交换机模块的数据的输入或输出。

9. 发明申请

US20090132843A1 CURRENT MODE BUS INTERFACE SYSTEM, METHOD OF PERFORMING A MODE TRANSITION AND MODE CONTROL SIGNAL GENERATOR FOR THE SAME 审中-公开
标题翻译：电流模式总线接口系统，执行模式转换的方法和模式控制信号发生器
公开(公告)号：US20090132843A1
公开(公告)日：2009-05-21
申请号：US12350647
申请日：2009-01-08
申请人： Dong-Uk Park
发明人： Dong-Uk Park
IPC分类号： G06F1/32
CPC分类号： G06F13/4072
摘要： A current mode bus interface system includes a host interface device configured to transmit a reference current and a clock current, and to transmit a data current during a first transfer mode, and to receive a reverse direction data current and compare the reverse direction data current with the reference current to generate a reverse direction data voltage during a second transfer mode; and a client interface device configured to receive the reference current and the clock current and compare the reference current with the clock current to generate a clock voltage, to receive the data current and compare the data current with the reference current to generate a data voltage during the first transfer mode, and to transmit the reverse direction data current through a conducting wire over which the data current is received during the second transfer mode.
摘要翻译：电流模式总线接口系统包括被配置为传送参考电流和时钟电流并且在第一传输模式期间传输数据电流的主机接口设备，并且接收反向数据电流并且将反向数据电流与所述参考电流在第二传送模式期间产生反向数据电压; 以及客户端接口装置，被配置为接收参考电流和时钟电流，并将参考电流与时钟电流进行比较以产生时钟电压，以接收数据电流并将数据电流与参考电流进行比较以在数据电压期间产生数据电压第一传送模式，并且通过在第二传送模式期间接收数据电流的导线传输反向数据电流。

10. 发明申请

US20080218292A1 Low voltage data transmitting circuit and associated methods 审中-公开
标题翻译：低压数据传输电路及相关方法
公开(公告)号：US20080218292A1
公开(公告)日：2008-09-11
申请号：US12073313
申请日：2008-03-04
申请人： Dong-Uk Park , Jin-Ho Seo , Jae-Jin Park
发明人： Dong-Uk Park , Jin-Ho Seo , Jae-Jin Park
IPC分类号： H01P5/12
CPC分类号： G06F13/4086
摘要： A low voltage data transmitting circuit (LVDTC) may be connected to a first transmission line that transmits a first voltage signal to a receiver and a second transmission line that transmits a second voltage signal to the receiver. The LVDTC includes a first resistor coupled to the first transmission line, a second resistor coupled to the second transmission line, and a control unit coupled to the first transmission line and the second transmission line, the control unit being configured to control voltage levels of the first and second voltage signals such that the voltage levels of the first and second voltage signals are higher than a ground voltage level of the receiver, wherein the first and second voltage signals may constitute a differential pair.
摘要翻译：低压数据发送电路（LVDTC）可以连接到向接收机发送第一电压信号的第一传输线和向接收机发送第二电压信号的第二传输线。 LVDTC包括耦合到第一传输线的第一电阻器，耦合到第二传输线的第二电阻器和耦合到第一传输线路和第二传输线路的控制单元，该控制单元被配置为控制第一和第二电压信号，使得第一和第二电压信号的电压电平高于接收器的接地电压电平，其中第一和第二电压信号可以构成差分对。

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