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1. 发明授权

US08300003B2 Driver for reducing a noise, display device having the driver, and method thereof 失效
标题翻译：用于降低噪声的驱动器，具有驱动器的显示装置及其方法
公开(公告)号：US08300003B2
公开(公告)日：2012-10-30
申请号：US12073684
申请日：2008-03-07
申请人： Dong-Uk Park
发明人： Dong-Uk Park
IPC分类号： G09G3/36
CPC分类号： G09G3/20 , G09G2310/08 , G09G2330/06
摘要： A driver may include a plurality of data output units and/or a multi-phase clock generator. The plurality of data output units may be configured to output data based on a plurality of clock signals. The multi-phase clock generator may be configured to receive a master clock signal to generate the plurality of clock signals having different phases in a period of the master clock signal and/or to provide the clock signals to the data output units. A number of the clock signals may correspond to a number of the data output units.
摘要翻译：驱动器可以包括多个数据输出单元和/或多相时钟发生器。多个数据输出单元可以被配置为基于多个时钟信号输出数据。多相时钟发生器可以被配置为接收主时钟信号以在主时钟信号的周期中产生具有不同相位的多个时钟信号和/或向数据输出单元提供时钟信号。多个时钟信号可以对应于多个数据输出单元。

2. 发明授权

US07675322B2 Level shifting circuits for generating output signals having similar duty cycle ratios 有权
标题翻译：用于产生具有相似占空比的输出信号的电平移动电路
公开(公告)号：US07675322B2
公开(公告)日：2010-03-09
申请号：US12070841
申请日：2008-02-21
申请人： Dong-Uk Park
发明人： Dong-Uk Park
IPC分类号： H03K19/0175
CPC分类号： H03K3/00 , H03K3/35613
摘要： A level shifting circuit includes a level shifting unit and an output buffer unit. The level shifting unit generates first and second output signals responsive to first and second input signals. The first and second input signals range between first and second voltage levels, and the first and second input signals are a first differential pair. The first and second output signals range between the first voltage level and a third voltage level greater than the second voltage level, and the first and second output signals are a second differential pair. The output buffer unit inverts the first and second output signals to provide third and fourth output signals, respectively. Duty ratios of the first and second output signals are determined based on delay times of the first and second input signals.
摘要翻译：电平移位电路包括电平移位单元和输出缓冲单元。电平转换单元响应于第一和第二输入信号产生第一和第二输出信号。第一和第二输入信号在第一和第二电压电平之间的范围内，第一和第二输入信号是第一差分对。第一和第二输出信号在第一电压电平和大于第二电压电平的第三电压电平之间的范围内，第一和第二输出信号是第二差分对。输出缓冲器单元反转第一和第二输出信号以分别提供第三和第四输出信号。基于第一和第二输入信号的延迟时间来确定第一和第二输出信号的占空比。

3. 发明申请

US20090251184A1 DUTY CYCLE CORRECTION CIRCUIT APPARATUS 失效
标题翻译：占空比校正电路设备
公开(公告)号：US20090251184A1
公开(公告)日：2009-10-08
申请号：US12401786
申请日：2009-03-11
申请人： Dong-uk PARK
发明人： Dong-uk PARK
IPC分类号： H03K5/04
CPC分类号： H03K5/13 , H03K5/1565 , H03L7/0812 , H03L7/099
摘要： A duty cycle correction circuit apparatus includes a flip-flop, a feedback unit connected between an input node and an output node of the flip-flop to invert an output signal of the flip-flop and to output the inverted signal as an output signal of the feedback unit, and a selection unit to select and output one of a first clock signal and a second clock signal to the flip-flop in response to the output signal of the feedback unit, wherein the first clock signal has a half-period phase difference with respect to the second clock signal. Using clock signals with a half-period phase difference therebetween and a simple digital circuit, the duty cycle correction circuit can correct a duty ratio to 50:50 regardless of an initial condition.
摘要翻译：占空比校正电路装置包括触发器，反馈单元，连接在触发器的输入节点和输出节点之间，以反转触发器的输出信号，并输出反相信号作为输出信号反馈单元和选择单元，用于响应于反馈单元的输出信号，向触发器选择并输出第一时钟信号和第二时钟信号中的一个，其中第一时钟信号具有半周期相位相对于第二时钟信号的差。使用其半周期相位差的时钟信号和简单的数字电路，占空比校正电路可以将占空比校正为50:50，而与初始条件无关。

4. 发明授权

US07579871B2 Current drive circuit and method of boosting current using the same 失效
标题翻译：电流驱动电路及使用其的升压电流的方法
公开(公告)号：US07579871B2
公开(公告)日：2009-08-25
申请号：US11363338
申请日：2006-02-27
申请人： Dong-Uk Park
发明人： Dong-Uk Park
IPC分类号： H03K19/0175 , H03B1/00
CPC分类号： H03K19/00384
摘要： A current drive circuit includes a differential voltage detector configured to detect a voltage level of a drive node and configured to compare the voltage level of the drive node with a voltage level of a reference voltage to generate a comparison signal, a control logic circuit configured to generate a control signal to provide a current to the drive node based on the comparison signal, and a current driver configured to provide the current to the drive node or provide the current from the drive node based on the control signal. The voltage level of the drive node rapidly reaches the voltage level of the reference voltage.
摘要翻译：电流驱动电路包括：差分电压检测器，被配置为检测驱动节点的电压电平，并配置为将驱动节点的电压电平与参考电压的电压电平进行比较以产生比较信号;控制逻辑电路，被配置为生成控制信号以基于比较信号向驱动节点提供电流，以及当前驱动器，其被配置为基于控制信号向驱动节点提供电流或者提供来自驱动节点的电流。驱动节点的电压电平迅速达到参考电压的电压电平。

5. 发明申请

US20080225029A1 Driver for reducing a noise, display device having the driver, and method thereof 失效
标题翻译：用于降低噪声的驱动器，具有驱动器的显示装置及其方法
公开(公告)号：US20080225029A1
公开(公告)日：2008-09-18
申请号：US12073684
申请日：2008-03-07
申请人： Dong-Uk Park
发明人： Dong-Uk Park
IPC分类号： G09G5/00
CPC分类号： G09G3/20 , G09G2310/08 , G09G2330/06
摘要： A driver may include a plurality of data output units and/or a multi-phase clock generator. The plurality of data output units may be configured to output data based on a plurality of clock signals. The multi-phase clock generator may be configured to receive a master clock signal to generate the plurality of clock signals having different phases in a period of the master clock signal and/or to provide the clock signals to the data output units. A number of the clock signals may correspond to a number of the data output units.
摘要翻译：驱动器可以包括多个数据输出单元和/或多相时钟发生器。多个数据输出单元可以被配置为基于多个时钟信号输出数据。多相时钟发生器可以被配置为接收主时钟信号以在主时钟信号的周期中产生具有不同相位的多个时钟信号和/或向数据输出单元提供时钟信号。多个时钟信号可以对应于多个数据输出单元。

6. 发明授权

US09232417B2 Integrated repeater for integratedly relaying various types of communication signals, and integrated relay system 有权
公开(公告)号：US09232417B2
公开(公告)日：2016-01-05
申请号：US13696281
申请日：2011-04-28
申请人： Seok-Young Kong , Dong-Uk Park , Seong-Hee Suh , Jae-Seon Jang
发明人： Seok-Young Kong , Dong-Uk Park , Seong-Hee Suh , Jae-Seon Jang
IPC分类号： H04B3/36 , H04B10/29 , H04B7/155 , H04W24/04
CPC分类号： H04W24/04 , H04B3/36 , H04B7/155 , H04B10/29 , H04L12/64 , H04L49/20
摘要： The present invention relates to an integrated repeater and an integrated relay system. The integrated repeater of the present invention receives a signal from a main repeater for relaying signals transmitted from upper devices, and comprises a demultiplexer configured to demultiplex the multiplexed signal of an Ethernet signal and a mobile communication signal received from the main repeater, and separate the signals into the mobile communication signal and the Ethernet signal; a first converter configured to convert the mobile communication signal separated from the demultiplexer into a radio frequency (RF) signal, and transmit the converted RF signal; a second converter configured to convert the Ethernet signal separated from the demultiplexer into a wireless LAN signal, and transmit the converted wireless LAN signal; and a switching unit configured to deliver a signal received from the main repeater to either the demultiplexer or the second converter, depending on whether a fault of the mobile communication signal is generated.

7. 发明申请

US20150229467A1 HIGH-SPEED INTERFACE APPARATUS AND DESKEW METHOD THEREOF 有权
标题翻译：高速接口设备及其方法
公开(公告)号：US20150229467A1
公开(公告)日：2015-08-13
申请号：US14513949
申请日：2014-10-14
申请人： HAN SOO LEE , SUNG JUN KIM , CHAE RYUNG KIM , DONG UK PARK , Youn Woong CHUNG , JUNG MYUNG CHOI , HAN KYUL LIM , GYEONG HAN CHA
发明人： HAN SOO LEE , SUNG JUN KIM , CHAE RYUNG KIM , DONG UK PARK , Youn Woong CHUNG , JUNG MYUNG CHOI , HAN KYUL LIM , GYEONG HAN CHA
IPC分类号： H04L7/00 , H04L25/40 , H04L25/14
CPC分类号： H04L7/0041 , G01R31/31725 , H03K5/131 , H03K2005/00058 , H04L7/0016 , H04L25/14
摘要： A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode.
摘要翻译：提供了一种校正装置中的偏斜的高速接口装置和方法。高速发射机包括通过时钟信道产生和发送时钟信号的发送D-PHY模块，响应于去歪斜请求信号产生偏斜同步码和测试数据，发送后面是测试数据的歪斜同步码通过数据信道，并且在普通模式下通过数据信道发送正常的同步码，然后是普通数据。

8. 发明授权

US08587654B2 Network switch control digital video recorder 有权
标题翻译：网络开关控制数字录像机
公开(公告)号：US08587654B2
公开(公告)日：2013-11-19
申请号：US13117212
申请日：2011-05-27
申请人： Song-Nam Bae , Dong-Uk Park , Byung-Yun Lee
发明人： Song-Nam Bae , Dong-Uk Park , Byung-Yun Lee
IPC分类号： H04N7/18 , H04N5/76 , G06F12/14
CPC分类号： H04N7/181
摘要： A network switch control digital video recorder (DVR) is provided. The network switch control DVR includes a network switch module configured to include a plurality of ports via which data is input to or output from at least one camera, a network storage, an external computer, and a DVR module and to multiplex data input or output via the plurality of ports; and the DVR module configured to control the input or output of data to or from the network switch module by monitoring a state of the input or output of data via the plurality of ports.
摘要翻译：提供网络交换机控制数字录像机（DVR）。网络交换机控制DVR包括网络交换机模块，该网络交换机模块被配置为包括多个端口，经由该端口将数据输入至少一个摄像机，网络存储器，外部计算机和DVR模块，或者从数据输入或输出经由多个端口; 并且所述DVR模块被配置为通过监视经由所述多个端口的数据的输入或输出的状态来控制到/从所述网络交换机模块的数据的输入或输出。

9. 发明授权

US07492189B2 Current mode bus interface system, method of performing a mode transition and mode control signal generator for the same 失效
标题翻译：电流模式总线接口系统，执行模式转换的方法和模式控制信号发生器
公开(公告)号：US07492189B2
公开(公告)日：2009-02-17
申请号：US11357550
申请日：2006-02-17
申请人： Dong-Uk Park
发明人： Dong-Uk Park
IPC分类号： H03K19/0175
CPC分类号： G06F13/4072
摘要： A current mode bus interface system includes a host interface device configured to transmit a reference current and a clock current, and to transmit a data current during a first transfer mode, and to receive a reverse direction data current and compare the reverse direction data current with the reference current to generate a reverse direction data voltage during a second transfer mode; and a client interface device configured to receive the reference current and the clock current and compare the reference current with the clock current to generate a clock voltage, to receive the data current and compare the data current with the reference current to generate a data voltage during the first transfer mode, and to transmit the reverse direction data current through a conducting wire over which the data current is received during the second transfer mode.
摘要翻译：电流模式总线接口系统包括被配置为传送参考电流和时钟电流并且在第一传输模式期间传输数据电流的主机接口设备，并且接收反向数据电流并且将反向数据电流与所述参考电流在第二传送模式期间产生反向数据电压; 以及客户端接口装置，被配置为接收参考电流和时钟电流，并将参考电流与时钟电流进行比较以产生时钟电压，以接收数据电流并将数据电流与参考电流进行比较以在数据电压期间产生数据电压第一传送模式，并且通过在第二传送模式期间接收数据电流的导线传输反向数据电流。

10. 发明申请

US20090015537A1 DISPLAY DEVICE TRANSFERRING DATA SIGNAL WITH CLOCK 有权
标题翻译：显示设备传输数据信号与时钟
公开(公告)号：US20090015537A1
公开(公告)日：2009-01-15
申请号：US12167393
申请日：2008-07-03
申请人： Jae-Jin PARK , Dong-Uk PARK , Jin-Ho SEO
发明人： Jae-Jin PARK , Dong-Uk PARK , Jin-Ho SEO
IPC分类号： G09G3/36
CPC分类号： G09G3/2096 , G09G3/3685 , G09G5/008 , G09G2330/06
摘要： A display device includes; a panel, a timing controller generating an embedded clock data signal combining image data and a clock signal, and a column driver driving the panel in response to the embedded clock data signal. The data bits within the embedded clock data signal are communicated at one of three voltage levels in a three-level signaling scheme, and the timing controller determines one of the three voltage levels for a current data bit (DIN[n]) within the embedded clock data signal in relation to a voltage level of a previous data bit (DIN[n−1]) within the embedded clock data signal.
摘要翻译：显示装置包括：面板，产生组合图像数据和时钟信号的嵌入式时钟数据信号的定时控制器和响应于嵌入的时钟数据信号驱动面板的列驱动器。嵌入式时钟数据信号中的数据位以三电平信令方案中的三个电压电平中的一个通信，并且定时控制器确定嵌入式时钟数据信号中当前数据位（DIN [n]）的三个电压电平之一时钟数据信号相对于嵌入式时钟数据信号中的先前数据位（DIN [n-1]）的电压电平。

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