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1. 发明授权

US08208335B2 Semiconductor memory device and system including the same 有权
标题翻译：半导体存储器件及其系统
公开(公告)号：US08208335B2
公开(公告)日：2012-06-26
申请号：US12821515
申请日：2010-06-23
申请人： Dong-Hyuk Lee , Jung-Bae Lee , Doo-Gon Kim , Cheol Kim
发明人： Dong-Hyuk Lee , Jung-Bae Lee , Doo-Gon Kim , Cheol Kim
IPC分类号： G11C7/00
CPC分类号： G11C29/50 , G11C11/401 , G11C11/406 , G11C11/40618 , G11C11/40622 , G11C29/24 , G11C29/50016 , G11C2211/4061
摘要： A semiconductor memory device includes a cell array unit having a plurality of banks each having a plurality of blocks, and a refresh controller configured to set at least one of the blocks as a test block, perform a refresh operation on the blocks except for the test block in a self-refresh operation period, determine a refresh period of the test block, and then set another one of the blocks as the test block.
摘要翻译：半导体存储器件包括具有多个块的单元阵列单元，每个单元具有多个块，以及刷新控制器，被配置为将至少一个块设置为测试块，对除了测试之外的块执行刷新操作在自刷新操作期间块，确定测试块的刷新周期，然后将另一个块设置为测试块。

2. 发明申请

US20110116335A1 SEMICONDUCTOR MEMORY DEVICE AND SYSTEM INCLUDING THE SAME 有权
标题翻译：半导体存储器件和系统，包括它们
公开(公告)号：US20110116335A1
公开(公告)日：2011-05-19
申请号：US12821515
申请日：2010-06-23
申请人： Dong Hyuk LEE , Jung-Bae Lee , Doo-Gon Kim , Cheol Kim
发明人： Dong Hyuk LEE , Jung-Bae Lee , Doo-Gon Kim , Cheol Kim
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C29/50 , G11C11/401 , G11C11/406 , G11C11/40618 , G11C11/40622 , G11C29/24 , G11C29/50016 , G11C2211/4061
摘要： A semiconductor memory device includes a cell array unit having a plurality of banks each having a plurality of blocks, and a refresh controller configured to set at least one of the blocks as a test block, perform a refresh operation on the blocks except for the test block in a self-refresh operation period, determine a refresh period of the test block, and then set another one of the blocks as the test block.
摘要翻译：半导体存储器件包括具有多个块的单元阵列单元，每个单元具有多个块，以及刷新控制器，被配置为将至少一个块设置为测试块，对除了测试之外的块执行刷新操作在自刷新操作期间块，确定测试块的刷新周期，然后将另一个块设置为测试块。

3. 发明授权

US07778085B2 Method of erasing in non-volatile memory device 有权
标题翻译：在非易失性存储器件中擦除的方法
公开(公告)号：US07778085B2
公开(公告)日：2010-08-17
申请号：US12136968
申请日：2008-06-11
申请人： Doo-Gon Kim , Ki-Tae Park , Yeong-Taek Lee
发明人： Doo-Gon Kim , Ki-Tae Park , Yeong-Taek Lee
IPC分类号： G11C16/06
CPC分类号： G11C16/14
摘要： An erasing method of post-programming in a nonvolatile memory device. The method includes post-programming dummy memory cells; verifying whether threshold voltages of the dummy memory cells are greater than or equal to a first voltage; post-programming normal memory cells; and verifying whether threshold voltages of the normal memory cells are greater than or equal to a second voltage. The first voltage is different from the second voltage.
摘要翻译：一种在非易失性存储器件中进行后编程的擦除方法。该方法包括后编程虚拟存储器单元; 验证所述伪存储单元的阈值电压是否大于或等于第一电压; 后编程正常记忆单元; 以及验证所述正常存储单元的阈值电压是否大于或等于第二电压。第一电压与第二电压不同。

4. 发明授权

US07539041B2 Floating body semiconductor memory device and method of operating the same 有权
标题翻译：浮体半导体存储器件及其操作方法
公开(公告)号：US07539041B2
公开(公告)日：2009-05-26
申请号：US11781331
申请日：2007-07-23
申请人： Doo-Gon Kim , Duk-Ha Park , Myoung-Gon Kang
发明人： Doo-Gon Kim , Duk-Ha Park , Myoung-Gon Kang
IPC分类号： G11C11/24
CPC分类号： G11C11/4091 , G11C11/4094 , G11C2211/4016
摘要： A semiconductor memory device includes a memory cell array having first and second blocks, respectively including first and second memory cells with floating bodies. The first memory cell is connected between a first bit line and a source line, and the second memory cell is connected between a second bit line and the source line. A sense amplifier equalizes the sense bit line and the inverted sense bit line to be an equalization voltage during an equalization operation, pre-charges the sense bit line and the inverted sense bit line to first and second pre-charge voltages during a pre-charge operation, and amplifies a voltage difference between the sense bit line and the inverted sense bit line during read and write operations. The first pre-charge voltage is higher than the equalization voltage and the second pre-charge voltage is higher than the equalization voltage and lower than the first pre-charge voltage.
摘要翻译：半导体存储器件包括具有第一和第二块的存储单元阵列，分别包括具有浮体的第一和第二存储单元。第一存储单元连接在第一位线和源极线之间，第二存储单元连接在第二位线和源极线之间。在均衡操作期间，感测放大器将感测位线和反相感测位线均衡为均衡电压，在预充电期间将感测位线和反相检测位线预充电到第一和第二预充电电压并且在读取和写入操作期间放大感测位线和反相感测位线之间的电压差。第一预充电电压高于均衡电压，第二预充电电压高于均衡电压并低于第一预充电电压。

5. 发明申请

US20080151633A1 Method of Programming in a Non-Volatile Memory Device and Non-Volatile Memory Device for Performing the Same 有权
标题翻译：在非易失性存储器件中编程的方法和用于执行其的非易失性存储器件
公开(公告)号：US20080151633A1
公开(公告)日：2008-06-26
申请号：US11955891
申请日：2007-12-13
申请人： Ki-Tae Park , Yeong-Taek Lee , Ki-Nam Kim , Doo-Gon Kim
发明人： Ki-Tae Park , Yeong-Taek Lee , Ki-Nam Kim , Doo-Gon Kim
IPC分类号： G11C16/06
CPC分类号： G11C16/3418 , G11C16/24 , G11C16/3427
摘要： Provided are methods for programming in a non-volatile memory device, using incremental step pulses as a program voltage that is applied to a selected wordline. Methods may include applying a precharge voltage to an even bitline and an odd bitline such that the even bitline and the odd bitline are alternately charged with the precharge voltage and a boosted voltage that is higher than the precharge voltage. Methods may further include applying a bitline voltage corresponding to program data to a selected bitline of the even bitline and the odd bitline.
摘要翻译：提供了用于在非易失性存储器件中进行编程的方法，其使用增量步长脉冲作为施加到选定字线的编程电压。方法可以包括将预充电电压施加到偶数位线和奇数位线，使得偶数位线和奇数位线以预充电电压和高于预充电电压的升压电压交替地充电。方法还可以包括将对应于程序数据的位线电压应用于偶位线和奇数位线的选定位线。

6. 发明授权

US08031544B2 Semiconductor memory device with three-dimensional array and repair method thereof 有权
标题翻译：具有三维阵列的半导体存储器件及其修复方法
公开(公告)号：US08031544B2
公开(公告)日：2011-10-04
申请号：US12336827
申请日：2008-12-17
申请人： Doo-Gon Kim , Ki-Tae Park
发明人： Doo-Gon Kim , Ki-Tae Park
IPC分类号： G11C29/00
CPC分类号： G11C29/808
摘要： A nonvolatile memory device includes a three-dimensional (3D) cell array, a column selection circuit and a fuse block. The 3D cell array includes multiple cell arrays located in corresponding stacked substrate layers, the cell arrays sharing a bit line. The column selection circuit selects a memory unit included in the 3D cell array. The fuse block controls the column selection circuit to repair defective columns with one of multiple redundant bit lines located in the 3D cell array.
摘要翻译：非易失性存储器件包括三维（3D）单元阵列，列选择电路和熔丝块。 3D单元阵列包括位于对应的堆叠衬底层中的多个单元阵列，单元阵列共享位线。列选择电路选择包括在3D单元阵列中的存储单元。熔丝块控制列选择电路，以修复位于3D单元阵列中的多个冗余位线之一的有缺陷的列。

7. 发明申请

US20110235432A1 METHOD OF ERASING IN NON-VOLATILE MEMORY DEVICE 有权
标题翻译：非易失性存储器件中的擦除方法
公开(公告)号：US20110235432A1
公开(公告)日：2011-09-29
申请号：US13153285
申请日：2011-06-03
申请人： Doo-Gon Kim , Ki-Tae Park , Yeong-Taek Lee
发明人： Doo-Gon Kim , Ki-Tae Park , Yeong-Taek Lee
IPC分类号： G11C16/28
CPC分类号： G11C16/14
摘要： An erasing method of post-programming in a nonvolatile memory device. The method includes post-programming dummy memory cells; verifying whether threshold voltages of the dummy memory cells are greater than or equal to a first voltage; post-programming normal memory cells; and verifying whether threshold voltages of the normal memory cells are greater than or equal to a second voltage. The first voltage is different from the second voltage.
摘要翻译：一种在非易失性存储器件中进行后编程的擦除方法。该方法包括后编程虚拟存储器单元; 验证所述伪存储单元的阈值电压是否大于或等于第一电压; 后编程正常记忆单元; 以及验证所述正常存储单元的阈值电压是否大于或等于第二电压。第一电压与第二电压不同。

8. 发明授权

US07957199B2 Method of erasing in non-volatile memory device 有权
标题翻译：在非易失性存储器件中擦除的方法
公开(公告)号：US07957199B2
公开(公告)日：2011-06-07
申请号：US12833098
申请日：2010-07-09
申请人： Doo-Gon Kim , Ki-Tae Park , Yeong-Taek Lee
发明人： Doo-Gon Kim , Ki-Tae Park , Yeong-Taek Lee
IPC分类号： G11C16/06
CPC分类号： G11C16/14
摘要： An erasing method in a nonvolatile memory device is disclosed. The method includes post-programming dummy memory cells; verifying whether threshold voltages of the dummy memory cells are greater than or equal to a first voltage; post-programming normal memory cells; and verifying whether threshold voltages of the normal memory cells are greater than or equal to a second voltage. The first voltage is different from the second voltage, and the post-programming of the dummy memory cells comprises: applying a program voltage to a plurality of dummy word lines coupled to the dummy memory cells to post-program the dummy memory cells; and applying a pass voltage to a plurality of normal word lines coupled to the normal memory cells so that the normal memory cells are not post-programmed.
摘要翻译：公开了一种非易失性存储器件中的擦除方法。该方法包括后编程虚拟存储器单元; 验证所述伪存储单元的阈值电压是否大于或等于第一电压; 后编程正常记忆单元; 以及验证所述正常存储单元的阈值电压是否大于或等于第二电压。第一电压与第二电压不同，并且虚拟存储单元的后编程包括：将程序电压施加到耦合到虚拟存储器单元的多个虚拟字线，以对虚拟存储器单元进行后编程; 以及对耦合到所述正常存储器单元的多个正常字线施加通过电压，使得所述正常存储器单元未被编程。

9. 发明授权

US07672166B2 Method of programming in a non-volatile memory device and non-volatile memory device for performing the same 有权
标题翻译：在非易失性存储器件和用于执行该非易失性存储器件的非易失性存储器件中进行编程的方法
公开(公告)号：US07672166B2
公开(公告)日：2010-03-02
申请号：US11955891
申请日：2007-12-13
申请人： Ki-Tae Park , Yeong-Taek Lee , Ki-Nam Kim , Doo-Gon Kim
发明人： Ki-Tae Park , Yeong-Taek Lee , Ki-Nam Kim , Doo-Gon Kim
IPC分类号： G11C16/06
CPC分类号： G11C16/3418 , G11C16/24 , G11C16/3427
摘要： Provided are methods for programming in a non-volatile memory device, using incremental step pulses as a program voltage that is applied to a selected wordline. Methods may include applying a precharge voltage to an even bitline and an odd bitline such that the even bitline and the odd bitline are alternately charged with the precharge voltage and a boosted voltage that is higher than the precharge voltage. Methods may further include applying a bitline voltage corresponding to program data to a selected bitline of the even bitline and the odd bitline.
摘要翻译：提供了用于在非易失性存储器件中进行编程的方法，其使用增量步长脉冲作为施加到选定字线的编程电压。方法可以包括将预充电电压施加到偶数位线和奇数位线，使得偶数位线和奇数位线以预充电电压和高于预充电电压的升压电压交替地充电。方法还可以包括将对应于程序数据的位线电压应用于偶位线和奇数位线的选定位线。

10. 发明授权

US09903901B2 Leakage current detection device and nonvolatile memory device having the same 有权
公开(公告)号：US09903901B2
公开(公告)日：2018-02-27
申请号：US14681137
申请日：2015-04-08
申请人： Byung-Gil Jeon , Doo-Gon Kim
发明人： Byung-Gil Jeon , Doo-Gon Kim
IPC分类号： G01R31/02 , G11C29/02 , G11C29/50 , G11C11/16 , G11C13/00
CPC分类号： G01R31/025 , G11C11/1673 , G11C13/00 , G11C29/023 , G11C29/025 , G11C29/026 , G11C29/50008 , G11C2029/5006
摘要： A leakage current detection device includes a test detection circuit, a reference detection circuit, a comparator, and a latch circuit. The test detection circuit is coupled between a test node and a test line, provides a voltage to the test node to charge the test line, floats the test node and the test line, and decreases a voltage of the test node based on leakage current of the test line. The reference detection circuit is coupled between a reference node and a reference line, provides the voltage to the reference node to charge the reference line, floats the reference node and the reference line, and decreases a voltage of the reference node based on self-discharge of the reference line. The comparator outputs a comparison signal by comparing voltages of the test node and the reference node. The latch circuit latches the comparison signal to output a test result signal.

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