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1. 发明授权

US07338849B2 Methods of fabricating flash memory devices and flash memory devices fabricated thereby 有权
标题翻译：制造闪存器件和闪存器件的方法
公开(公告)号：US07338849B2
公开(公告)日：2008-03-04
申请号：US11261820
申请日：2005-10-28
申请人： Dong-Chan Kim , Chang-Jin Kang , Kyeong-Koo Chi , Dong-Hyun Kim
发明人： Dong-Chan Kim , Chang-Jin Kang , Kyeong-Koo Chi , Dong-Hyun Kim
IPC分类号： H01L21/8238 , H01L29/788
CPC分类号： H01L27/11521 , H01L27/115
摘要： Methods of fabricating a flash memory device and flash memory devices fabricated thereby are provided. One of the methods includes forming an isolation layer in a semiconductor substrate to define a plurality of parallel active regions in the semiconductor substrate. A plurality of first conductive layer patterns are formed on the active regions. The first conductive layer patterns are spaced apart from each other in a lengthwise direction of the active regions. An insulating layer is conformally formed on the semiconductor substrate and the first conductive layer patterns. A second conductive layer is formed on the insulating layer. The second conductive layer is patterned until the insulating layer is exposed to form a plurality of parallel second conductive layer patterns. The second conductive layer patterns cross the active regions and the isolation layer to overlap the first conductive layer patterns.
摘要翻译：提供了制造闪速存储器件的方法和由此制造的闪存器件。一种方法包括在半导体衬底中形成隔离层以在半导体衬底中限定多个平行的有源区。在有源区上形成多个第一导电层图案。第一导电层图案在活性区域的长度方向上彼此间隔开。在半导体衬底和第一导电层图案上共形形成绝缘层。在绝缘层上形成第二导电层。图案化第二导电层直到绝缘层暴露以形成多个平行的第二导电层图案。第二导电层图案与有源区和隔离层交叉，以与第一导电层图案重叠。

2. 发明申请

US20060094188A1 Methods of fabricating flash memory devices and flash memory devices fabricated thereby 有权
标题翻译：制造闪存器件和闪存器件的方法
公开(公告)号：US20060094188A1
公开(公告)日：2006-05-04
申请号：US11261820
申请日：2005-10-28
申请人： Dong-Chan Kim , Chang-Jin Kang , Kyeong-Koo Chi , Dong-Hyun Kim
发明人： Dong-Chan Kim , Chang-Jin Kang , Kyeong-Koo Chi , Dong-Hyun Kim
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L27/115
摘要： Methods of fabricating a flash memory device and flash memory devices fabricated thereby are provided. One of the methods includes forming an isolation layer in a semiconductor substrate to define a plurality of parallel active regions in the semiconductor substrate. A plurality of first conductive layer patterns are formed on the active regions. The first conductive layer patterns are spaced apart from each other in a lengthwise direction of the active regions. An insulating layer is conformally formed on the semiconductor substrate and the first conductive layer patterns. A second conductive layer is formed on the insulating layer. The second conductive layer is patterned until the insulating layer is exposed to form a plurality of parallel second conductive layer patterns. The second conductive layer patterns cross the active regions and the isolation layer to overlap the first conductive layer patterns.
摘要翻译：提供了制造闪速存储器件的方法和由此制造的闪存器件。一种方法包括在半导体衬底中形成隔离层以在半导体衬底中限定多个平行的有源区。在有源区上形成多个第一导电层图案。第一导电层图案在活性区域的长度方向上彼此间隔开。在半导体衬底和第一导电层图案上共形形成绝缘层。在绝缘层上形成第二导电层。图案化第二导电层直到绝缘层暴露以形成多个平行的第二导电层图案。第二导电层图案与有源区和隔离层交叉，以与第一导电层图案重叠。

3. 发明授权

US07479445B2 Methods of forming field effect transistors having t-shaped gate electrodes using carbon-based etching masks 有权
标题翻译：使用碳基蚀刻掩模形成具有t形栅电极的场效应晶体管的方法
公开(公告)号：US07479445B2
公开(公告)日：2009-01-20
申请号：US11247937
申请日：2005-10-11
申请人： Dong-Chan Kim , Chang-Jin Kang , Kyeong-Koo Chi , Sung-Hoon Chung
发明人： Dong-Chan Kim , Chang-Jin Kang , Kyeong-Koo Chi , Sung-Hoon Chung
IPC分类号： H01L21/28 , H01L21/335
CPC分类号： H01L29/1037 , H01L21/823437 , H01L21/823456 , H01L29/76
摘要： Methods of forming field effect transistors include forming a first electrically insulating layer comprising mostly carbon on a surface of a semiconductor substrate and patterning the first electrically insulating layer to define an opening therein. A trench is formed in the substrate by etching the surface of the substrate using the patterned first electrically insulating layer as an etching mask. The trench is filled with a gate electrode. The first electrically insulating layer is patterned in an ambient containing oxygen. This oxygen-containing ambient supports further oxidation of trench-based isolation regions within the substrate when they are exposed by openings within the first electrically insulating layer.
摘要翻译：形成场效应晶体管的方法包括在半导体衬底的表面上形成主要包含碳的第一电绝缘层，并且图案化第一电绝缘层以在其中限定开口。通过使用图案化的第一电绝缘层作为蚀刻掩模蚀刻衬底的表面，在衬底中形成沟槽。沟槽填充有栅电极。第一电绝缘层在含有氧的环境中被图案化。当这种含氧环境通过第一电绝缘层内的开口露出时，支撑衬底内基于沟槽的隔离区的进一步氧化。

4. 发明授权

US07384843B2 Method of fabricating flash memory device including control gate extensions 失效
标题翻译：包括控制门扩展的闪存设备的制造方法
公开(公告)号：US07384843B2
公开(公告)日：2008-06-10
申请号：US11260377
申请日：2005-10-28
申请人： Dong-Chan Kim , Chang-Jin Kang , Kyeong-Koo Chi , Seung-Pil Chung
发明人： Dong-Chan Kim , Chang-Jin Kang , Kyeong-Koo Chi , Seung-Pil Chung
IPC分类号： H01L21/336
CPC分类号： H01L27/11524 , H01L21/28273 , H01L27/11521
摘要： A method of manufacturing a semiconductor memory device comprises forming floating gates on active regions of a semiconductor substrate and forming a capping layer on the floating gates. An isolation layer located in the semiconductor substrate between the floating gates is anisotropically etched using the capping layer as an etch mask to form recessed regions. The recessed regions are formed to have a width smaller than a distance between the floating gates, and bottom surfaces positioned below bottom surfaces of the floating gates. Control gate electrodes are formed across the active regions over the floating gates and the control gate electrodes have control gate extensions formed within the recessed regions between the floating gates.
摘要翻译：制造半导体存储器件的方法包括在半导体衬底的有源区上形成浮置栅极，并在浮置栅极上形成封盖层。使用覆盖层作为蚀刻掩模对位于浮置栅极之间的半导体衬底中的隔离层进行各向异性蚀刻，以形成凹陷区域。凹陷区域形成为具有小于浮动栅极之间的距离的宽度，以及位于浮动栅极的底表面下方的底表面的宽度。控制栅电极形成在浮动栅极之上的有源区域两侧，并且控制栅电极具有形成在浮置栅极之间的凹陷区域内的控制栅延伸。

5. 发明授权

US07125766B2 Method of forming capacitor for semiconductor device 有权
标题翻译：形成半导体器件电容器的方法
公开(公告)号：US07125766B2
公开(公告)日：2006-10-24
申请号：US11062546
申请日：2005-02-23
申请人： Dong-Chan Kim , Chang-Jin Kang , Byeong-Yun Nam , Kyeong-Koo Chi
发明人： Dong-Chan Kim , Chang-Jin Kang , Byeong-Yun Nam , Kyeong-Koo Chi
IPC分类号： H01L21/8242
CPC分类号： H01L28/91 , H01L27/10814 , H01L27/10817 , H01L27/10855
摘要： A method of forming a capacitor for a semiconductor device is disclosed. According to the method, a silicon germanium layer and an oxide layer are used as mold layers for forming a storage electrode. The oxide layer and the silicon germanium layer are anisotropically etched to form an opening and then the silicon germanium layer is further isotropically etched to form a recessed portion of the opening, such that the recessed portion of the opening formed in the silicon germanium layer is wider than at least some portion of the opening through the oxide layer. Thus, the mold layers are used to form a storage electrode having a lower portion which is wider than an upper portion thereof.
摘要翻译：公开了一种形成用于半导体器件的电容器的方法。根据该方法，使用硅锗层和氧化物层作为用于形成存储电极的模具层。各向异性蚀刻氧化物层和硅锗层以形成开口，然后进一步各向同性地蚀刻硅锗层以形成开口的凹部，使得形成在硅锗层中的开口的凹部变宽比通过氧化物层的开口的至少一部分。因此，模具层用于形成具有比其上部宽的下部的存储电极。

6. 发明申请

US20060128099A1 Method of fabricating flash memory device including control gate extensions 失效
标题翻译：包括控制门扩展的闪存设备的制造方法
公开(公告)号：US20060128099A1
公开(公告)日：2006-06-15
申请号：US11260377
申请日：2005-10-28
申请人： Dong-Chan Kim , Chang-Jin Kang , Kyeong-Koo Chi , Seung-Pil Chung
发明人： Dong-Chan Kim , Chang-Jin Kang , Kyeong-Koo Chi , Seung-Pil Chung
IPC分类号： H01L21/336
CPC分类号： H01L27/11524 , H01L21/28273 , H01L27/11521
摘要： A method of manufacturing a semiconductor memory device comprises forming floating gates on active regions of a semiconductor substrate and forming a capping layer on the floating gates. An isolation layer located in the semiconductor substrate between the floating gates is anisotropically etched using the capping layer as an etch mask to form recessed regions. The recessed regions are formed to have a width smaller than a distance between the floating gates, and bottom surfaces positioned below bottom surfaces of the floating gates. Control gate electrodes are formed across the active regions over the floating gates and the control gate electrodes have control gate extensions formed within the recessed regions between the floating gates.
摘要翻译：制造半导体存储器件的方法包括在半导体衬底的有源区上形成浮置栅极，并在浮置栅极上形成封盖层。使用覆盖层作为蚀刻掩模对位于浮置栅极之间的半导体衬底中的隔离层进行各向异性蚀刻，以形成凹陷区域。凹陷区域形成为具有小于浮动栅极之间的距离的宽度，以及位于浮动栅极的底表面下方的底表面的宽度。控制栅电极形成在浮动栅极之上的有源区域两侧，并且控制栅电极具有形成在浮置栅极之间的凹陷区域内的控制栅延伸。

7. 发明申请

US20060079076A1 Methods of forming field effect transistors having t-shaped gate electrodes using carbon-based etching masks 有权
公开(公告)号：US20060079076A1
公开(公告)日：2006-04-13
申请号：US11247937
申请日：2005-10-11
申请人： Dong-Chan Kim , Chang-Jin Kang , Kyeong-Koo Chi , Sung-Hoon Chung
发明人： Dong-Chan Kim , Chang-Jin Kang , Kyeong-Koo Chi , Sung-Hoon Chung
IPC分类号： H01L21/3205 , H01L21/336 , H01L21/8234
CPC分类号： H01L29/1037 , H01L21/823437 , H01L21/823456 , H01L29/76
摘要： Methods of forming field effect transistors include forming a first electrically insulating layer comprising mostly carbon on a surface of a semiconductor substrate and patterning the first electrically insulating layer to define an opening therein. A trench is formed in the substrate by etching the surface of the substrate using the patterned first electrically insulating layer as an etching mask. The trench is filled with a gate electrode. The first electrically insulating layer is patterned in an ambient containing oxygen. This oxygen-containing ambient supports further oxidation of trench-based isolation regions within the substrate when they are exposed by openings within the first electrically insulating layer.

8. 发明申请

US20050245026A1 Method of forming capacitor for semiconductor device 有权
标题翻译：形成半导体器件电容器的方法
公开(公告)号：US20050245026A1
公开(公告)日：2005-11-03
申请号：US11062546
申请日：2005-02-23
申请人： Dong-Chan Kim , Chang-Jin Kang , Byeong-Yun Nam , Kyeong-Koo Chi
发明人： Dong-Chan Kim , Chang-Jin Kang , Byeong-Yun Nam , Kyeong-Koo Chi
IPC分类号： H01L27/108 , H01L21/02 , H01L21/8242
CPC分类号： H01L28/91 , H01L27/10814 , H01L27/10817 , H01L27/10855
摘要： A method of forming a capacitor for a semiconductor device is disclosed. According to the method, a silicon germanium layer and an oxide layer are used as mold layers for forming a storage electrode. The oxide layer and the silicon germanium layer are anisotropically etched to form an opening and then the silicon germanium layer is further isotropically etched to form a recessed portion of the opening, such that the recessed portion of the opening formed in the silicon germanium layer is wider than at least some portion of the opening through the oxide layer. Thus, the mold layers are used to form a storage electrode having a lower portion which is wider than an upper portion thereof.
摘要翻译：公开了一种形成用于半导体器件的电容器的方法。根据该方法，使用硅锗层和氧化物层作为用于形成存储电极的模具层。各向异性蚀刻氧化物层和硅锗层以形成开口，然后进一步各向同性地蚀刻硅锗层以形成开口的凹部，使得形成在硅锗层中的开口的凹部变宽比通过氧化物层的开口的至少一部分。因此，模具层用于形成具有比其上部宽的下部的存储电极。

9. 发明授权

US07618899B2 Method of patterning a matrix into a substrate via multiple, line-and-space, sacrificial, hard mask layers 有权
标题翻译：通过多个线，空间，牺牲的硬掩模层将基体图案化成衬底的方法
公开(公告)号：US07618899B2
公开(公告)日：2009-11-17
申请号：US11847223
申请日：2007-08-29
申请人： Seung-Pil Chung , Dong-Chan Kim , Chang-Jin Kang , Heung-Sik Park
发明人： Seung-Pil Chung , Dong-Chan Kim , Chang-Jin Kang , Heung-Sik Park
IPC分类号： H01L21/31 , H01L21/308
CPC分类号： H01L21/0332 , H01L21/0337 , H01L21/3081 , H01L21/3086
摘要： Methods of fabricating a semiconductor integrated circuit device are disclosed. The methods of fabricating a semiconductor integrated circuit device include forming a hard mask layer on a base layer, forming a line sacrificial hard mask layer on the hard mask layer in a first direction, coating a high molecular organic material layer on the line sacrificial hard mask layer pattern, patterning the high molecular organic material layer and the line sacrificial hard mask layer pattern in a second direction, forming a matrix sacrificial hard mask layer pattern, forming a hard mask layer pattern by patterning the hard mask layer with the matrix sacrificial hard mask layer pattern as an etching mask and forming a lower pattern by patterning the base layer using the hard mask layer pattern as an etch mask. The method according to the invention is simpler and less expensive than conventional methods.
摘要翻译：公开了制造半导体集成电路器件的方法。制造半导体集成电路器件的方法包括在基底层上形成硬掩模层，在第一方向上在硬掩模层上形成线牺牲硬掩模层，在牺牲硬掩模上涂覆高分子有机材料层层状图案，在第二方向上图案化高分子有机材料层和线牺牲硬掩模层图案，形成矩阵牺牲硬掩模层图案，通过用基体牺牲硬掩模图案化硬掩模层形成硬掩模层图案层图案作为蚀刻掩模，并且通过使用硬掩模层图案作为蚀刻掩模对基底层进行图案化来形成下图案。根据本发明的方法比常规方法更简单和便宜。

10. 发明申请

US20050112819A1 Methods of forming capacitor structures including L-shaped cavities and related structures 有权
标题翻译：形成电容器结构的方法包括L形腔和相关结构
公开(公告)号：US20050112819A1
公开(公告)日：2005-05-26
申请号：US10977385
申请日：2004-10-29
申请人： Dong-Chan Kim , Chang-Jin Kang , Byeong-Yun Nam , Kyeong-Koo Ghi , Eun-Ae Chung , Sung-II Cho
发明人： Dong-Chan Kim , Chang-Jin Kang , Byeong-Yun Nam , Kyeong-Koo Ghi , Eun-Ae Chung , Sung-II Cho
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/91
摘要： Methods of forming capacitor structures may include forming an insulating layer on a substrate, forming a first capacitor electrode on the insulating layer, forming a capacitor dielectric layer on portions of the first capacitor electrode, and forming a second capacitor electrode on the capacitor dielectric layer such that the capacitor dielectric layer is between the first and second capacitor electrodes. More particularly, the first capacitor electrode may define a cavity therein wherein the cavity has a first portion parallel with respect to the substrate and a second portion perpendicular with respect to the substrate. Related structures are also discussed.
摘要翻译：形成电容器结构的方法可以包括在衬底上形成绝缘层，在绝缘层上形成第一电容器电极，在第一电容器电极的部分上形成电容器电介质层，以及在电容器电介质层上形成第二电容器电极，电容器介电层位于第一和第二电容器电极之间。更具体地，第一电容器电极可以在其中限定空腔，其中腔具有相对于衬底平行的第一部分和相对于衬底垂直的第二部分。还讨论了相关结构。

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