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1. 发明授权

US07312130B2 Methods of forming capacitor structures including L-shaped cavities 有权
标题翻译：形成电容器结构的方法包括L形腔
公开(公告)号：US07312130B2
公开(公告)日：2007-12-25
申请号：US10977385
申请日：2004-10-29
申请人： Dong-Chan Kim , Chang-Jin Kang , Byeong-Yun Nam , Kyeong-Koo Ghi , Eun-Ae Chung , Sung-Il Cho
发明人： Dong-Chan Kim , Chang-Jin Kang , Byeong-Yun Nam , Kyeong-Koo Ghi , Eun-Ae Chung , Sung-Il Cho
IPC分类号： H01L21/20
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/91
摘要： Methods of forming capacitor structures may include forming an insulating layer on a substrate, forming a first capacitor electrode on the insulating layer, forming a capacitor dielectric layer on portions of the first capacitor electrode, and forming a second capacitor electrode on the capacitor dielectric layer such that the capacitor dielectric layer is between the first and second capacitor electrodes. More particularly, the first capacitor electrode may define a cavity therein wherein the cavity has a first portion parallel with respect to the substrate and a second portion perpendicular with respect to the substrate. Related structures are also discussed.
摘要翻译：形成电容器结构的方法可以包括在衬底上形成绝缘层，在绝缘层上形成第一电容器电极，在第一电容器电极的部分上形成电容器电介质层，以及在电容器电介质层上形成第二电容器电极，电容器介电层位于第一和第二电容器电极之间。更具体地，第一电容器电极可以在其中限定空腔，其中腔具有相对于衬底平行的第一部分和相对于衬底垂直的第二部分。还讨论了相关结构。

2. 发明申请

US20050112819A1 Methods of forming capacitor structures including L-shaped cavities and related structures 有权
标题翻译：形成电容器结构的方法包括L形腔和相关结构
公开(公告)号：US20050112819A1
公开(公告)日：2005-05-26
申请号：US10977385
申请日：2004-10-29
申请人： Dong-Chan Kim , Chang-Jin Kang , Byeong-Yun Nam , Kyeong-Koo Ghi , Eun-Ae Chung , Sung-II Cho
发明人： Dong-Chan Kim , Chang-Jin Kang , Byeong-Yun Nam , Kyeong-Koo Ghi , Eun-Ae Chung , Sung-II Cho
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/91
摘要： Methods of forming capacitor structures may include forming an insulating layer on a substrate, forming a first capacitor electrode on the insulating layer, forming a capacitor dielectric layer on portions of the first capacitor electrode, and forming a second capacitor electrode on the capacitor dielectric layer such that the capacitor dielectric layer is between the first and second capacitor electrodes. More particularly, the first capacitor electrode may define a cavity therein wherein the cavity has a first portion parallel with respect to the substrate and a second portion perpendicular with respect to the substrate. Related structures are also discussed.
摘要翻译：形成电容器结构的方法可以包括在衬底上形成绝缘层，在绝缘层上形成第一电容器电极，在第一电容器电极的部分上形成电容器电介质层，以及在电容器电介质层上形成第二电容器电极，电容器介电层位于第一和第二电容器电极之间。更具体地，第一电容器电极可以在其中限定空腔，其中腔具有相对于衬底平行的第一部分和相对于衬底垂直的第二部分。还讨论了相关结构。

3. 发明授权

US07125766B2 Method of forming capacitor for semiconductor device 有权
标题翻译：形成半导体器件电容器的方法
公开(公告)号：US07125766B2
公开(公告)日：2006-10-24
申请号：US11062546
申请日：2005-02-23
申请人： Dong-Chan Kim , Chang-Jin Kang , Byeong-Yun Nam , Kyeong-Koo Chi
发明人： Dong-Chan Kim , Chang-Jin Kang , Byeong-Yun Nam , Kyeong-Koo Chi
IPC分类号： H01L21/8242
CPC分类号： H01L28/91 , H01L27/10814 , H01L27/10817 , H01L27/10855
摘要： A method of forming a capacitor for a semiconductor device is disclosed. According to the method, a silicon germanium layer and an oxide layer are used as mold layers for forming a storage electrode. The oxide layer and the silicon germanium layer are anisotropically etched to form an opening and then the silicon germanium layer is further isotropically etched to form a recessed portion of the opening, such that the recessed portion of the opening formed in the silicon germanium layer is wider than at least some portion of the opening through the oxide layer. Thus, the mold layers are used to form a storage electrode having a lower portion which is wider than an upper portion thereof.
摘要翻译：公开了一种形成用于半导体器件的电容器的方法。根据该方法，使用硅锗层和氧化物层作为用于形成存储电极的模具层。各向异性蚀刻氧化物层和硅锗层以形成开口，然后进一步各向同性地蚀刻硅锗层以形成开口的凹部，使得形成在硅锗层中的开口的凹部变宽比通过氧化物层的开口的至少一部分。因此，模具层用于形成具有比其上部宽的下部的存储电极。

4. 发明申请

US20050245026A1 Method of forming capacitor for semiconductor device 有权
标题翻译：形成半导体器件电容器的方法
公开(公告)号：US20050245026A1
公开(公告)日：2005-11-03
申请号：US11062546
申请日：2005-02-23
申请人： Dong-Chan Kim , Chang-Jin Kang , Byeong-Yun Nam , Kyeong-Koo Chi
发明人： Dong-Chan Kim , Chang-Jin Kang , Byeong-Yun Nam , Kyeong-Koo Chi
IPC分类号： H01L27/108 , H01L21/02 , H01L21/8242
CPC分类号： H01L28/91 , H01L27/10814 , H01L27/10817 , H01L27/10855
摘要： A method of forming a capacitor for a semiconductor device is disclosed. According to the method, a silicon germanium layer and an oxide layer are used as mold layers for forming a storage electrode. The oxide layer and the silicon germanium layer are anisotropically etched to form an opening and then the silicon germanium layer is further isotropically etched to form a recessed portion of the opening, such that the recessed portion of the opening formed in the silicon germanium layer is wider than at least some portion of the opening through the oxide layer. Thus, the mold layers are used to form a storage electrode having a lower portion which is wider than an upper portion thereof.
摘要翻译：公开了一种形成用于半导体器件的电容器的方法。根据该方法，使用硅锗层和氧化物层作为用于形成存储电极的模具层。各向异性蚀刻氧化物层和硅锗层以形成开口，然后进一步各向同性地蚀刻硅锗层以形成开口的凹部，使得形成在硅锗层中的开口的凹部变宽比通过氧化物层的开口的至少一部分。因此，模具层用于形成具有比其上部宽的下部的存储电极。

5. 发明申请

US20060040443A1 Methods of forming capacitor electrodes using fluorine and oxygen 失效
标题翻译：使用氟和氧形成电容器电极的方法
公开(公告)号：US20060040443A1
公开(公告)日：2006-02-23
申请号：US11154152
申请日：2005-06-16
申请人： Sung-Il Cho , Jong-Kyu Kim , Byeong-Yun Nam , Kyeong-Koo Chi , Cheol-Kyu Lee
发明人： Sung-Il Cho , Jong-Kyu Kim , Byeong-Yun Nam , Kyeong-Koo Chi , Cheol-Kyu Lee
IPC分类号： H01L21/8244
CPC分类号： H01L28/60 , H01L21/32136 , H01L21/32139 , H01L27/10852 , H01L27/11502 , H01L27/11507
摘要： A method of forming a capacitor can include etching a metal-nitride layer in an environment comprising fluorine and oxygen to form a capacitor electrode.
摘要翻译：形成电容器的方法可以包括在包括氟和氧的环境中蚀刻金属氮化物层以形成电容器电极。

6. 发明授权

US07329574B2 Methods of forming capacitor electrodes using fluorine and oxygen 失效
标题翻译：使用氟和氧形成电容器电极的方法
公开(公告)号：US07329574B2
公开(公告)日：2008-02-12
申请号：US11154152
申请日：2005-06-16
申请人： Sung-Il Cho , Jong-Kyu Kim , Byeong-Yun Nam , Kyeong-Koo Chi , Cheol-Kyu Lee
发明人： Sung-Il Cho , Jong-Kyu Kim , Byeong-Yun Nam , Kyeong-Koo Chi , Cheol-Kyu Lee
IPC分类号： H01L21/8242
CPC分类号： H01L28/60 , H01L21/32136 , H01L21/32139 , H01L27/10852 , H01L27/11502 , H01L27/11507
摘要： A method of forming a capacitor can include etching a metal-nitride layer in an environment comprising fluorine and oxygen to form a capacitor electrode.
摘要翻译：形成电容器的方法可以包括在包括氟和氧的环境中蚀刻金属氮化物层以形成电容器电极。

7. 发明授权

US07226867B2 Method of etching a metal layer using a mask, a metallization method for a semiconductor device, a method of etching a metal layer, and an etching gas 失效
标题翻译：使用掩模蚀刻金属层的方法，半导体器件的金属化方法，蚀刻金属层的方法和蚀刻气体
公开(公告)号：US07226867B2
公开(公告)日：2007-06-05
申请号：US10419075
申请日：2003-04-21
申请人： Seung-Young Son , Cheol-Kyu Lee , Chang-Jin Kang , Byeong-Yun Nam
发明人： Seung-Young Son , Cheol-Kyu Lee , Chang-Jin Kang , Byeong-Yun Nam
IPC分类号： H01L21/302
CPC分类号： C23F4/00 , H01L21/32136 , H01L21/32139
摘要： Methods for etching a metal layer and a metallization method of a semiconductor device using an etching gas that includes Cl2 and N2 are provided. A mask layer is formed on the metal layer, the etching gas is supplied to the metal layer, and the metal layer is etched by the etching gas using the mask layer as an etch mask. The metal layer may be formed of aluminum or an aluminum alloy. Cl2 and N2 may be mixed at a ratio of 1:1 to 1:10. The etching gas may also include additional gases such as inactive gases or gases that include the elements H, O, F, He, or C. In addition, N2 may be supplied at a flow rate of from 45–65% of the total flow rate of the etching gas, which results in a reduction in the occurrence of micro-loading and cone-shaped defects in semiconductor devices.
摘要翻译：提供了蚀刻金属层的方法和使用包括Cl 2 N 2和N 2 N的蚀刻气体的半导体器件的金属化方法。在金属层上形成掩模层，将蚀刻气体供给到金属层，并使用掩模层作为蚀刻掩模，通过蚀刻气体蚀刻金属层。金属层可以由铝或铝合金形成。 Cl 2 N 2和N 2可以1:1至1:10的比例混合。蚀刻气体还可以包括另外的气体，例如包括元素H，O，F，He或C的惰性气体或气体。此外，N 2可以以蚀刻气体总流量的45-65％，这导致半导体器件中的微负载和锥形缺陷的发生减少。

8. 发明授权

US5693546A Methods of forming thin film transistors having lightly-doped drain and source regions therein 失效
标题翻译：形成其中具有轻掺杂漏极和源极区的薄膜晶体管的方法
公开(公告)号：US5693546A
公开(公告)日：1997-12-02
申请号：US659315
申请日：1996-06-06
申请人： Byeong-Yun Nam , Sang-Won Lee , Jin-Hong Kim
发明人： Byeong-Yun Nam , Sang-Won Lee , Jin-Hong Kim
IPC分类号： H01L21/336 , H01L29/786 , H01L21/265
CPC分类号： H01L29/66757 , H01L29/78621
摘要： Methods of forming field effect transistors include the steps of forming a composite of layers including an amorphous silicon layer (a--Si), a silicon dioxide layer thereon and a silicon nitride layer on the silicon dioxide layer. A polycrystalline silicon conductive layer is then formed on the silicon nitride layer by depositing and patterning polycrystalline silicon. The polycrystalline silicon conductive layer is then oxidized using thermal oxidation techniques to form an oxide outerlayer. During this step, a portion of the polycrystalline silicon conductive layer will be consumed to define a gate electrode. Dopants of first conductivity type are then implanted into a top surface of the silicon nitride layer, using the oxide outerlayer and the gate electrode as a mask, to form relatively lightly doped preliminary source and drain regions in the amorphous silicon layer. The oxide outerlayer is then removed preferably using a buffered oxide etchant (BOE) solution which does not etch silicon nitride. Following this, dopants of first conductivity type are again implanted into the amorphous silicon layer, using the gate electrode as a mask. The second implantation step causes the formation of a field effect transistor having self-aligned source and drain regions, self-aligned lightly doped source and drain region extensions (LDS, LDD) and a channel region therebetween which has the same length as the gate electrode. By forming the channel region to have the same length as the gate electrode, improved device characteristics can be achieved.
摘要翻译：形成场效应晶体管的方法包括以下步骤：在二氧化硅层上形成包括非晶硅层（a-Si），二氧化硅层和氮化硅层的层的复合物。然后通过沉积和构图多晶硅在氮化硅层上形成多晶硅导电层。然后使用热氧化技术氧化多晶硅导电层以形成氧化物外层。在该步骤期间，多晶硅导电层的一部分将被消耗以限定栅电极。然后，使用氧化物外层和栅电极作为掩模，将第一导电类型的掺杂剂注入到氮化硅层的顶表面中，以在非晶硅层中形成相对轻掺杂的初始源极和漏极区。然后优选使用不蚀刻氮化硅的缓冲氧化物蚀刻剂（BOE）溶液去除氧化物外层。接下来，使用栅电极作为掩模，再次将第一导电类型的掺杂剂注入到非晶硅层中。第二注入步骤导致形成具有自对准的源区和漏区，自对准的轻掺杂源极和漏极延伸（LDS，LDD）的场效应晶体管及其间具有与栅电极相同长度的沟道区。通过形成与栅电极具有相同长度的沟道区，可以实现改进的器件特性。

9. 发明授权

US07867841B2 Methods of forming semiconductor devices with extended active regions 有权
标题翻译：形成具有扩展活性区域的半导体器件的方法
公开(公告)号：US07867841B2
公开(公告)日：2011-01-11
申请号：US11968242
申请日：2008-01-02
申请人： Dong-Chan Lim , Byeong-Yun Nam , Soo-Ik Jang , In-Soo Jung
发明人： Dong-Chan Lim , Byeong-Yun Nam , Soo-Ik Jang , In-Soo Jung
IPC分类号： H01L21/8238
CPC分类号： H01L21/76283 , H01L21/84 , H01L27/10873 , H01L27/1203
摘要： A method of forming a semiconductor device can include forming a trench in a semiconductor substrate to define an active region. The trench is filled with a first device isolation layer. A portion of the first device isolation layer is etched to recess a top surface of the first device isolation layer below an adjacent top surface of the active region of the semiconductor substrate and to partially expose a sidewall of the active region. The exposed sidewall of the active region is epitaxially grown to form an extension portion of the active region that extends partially across the top surface of the first device isolation layer in the trench. A second device isolation layer is formed on the recessed first device isolation layer in the trench. The second device isolation layer is etched to expose a top surface of the extension portion of the active region and leave a portion of the second device isolation layer between extension portions of active regions on opposite sides of the trench. An interlayer dielectric is formed on the semiconductor substrate and the second device isolation layer. A conductive contact is formed extending through the interlayer dielectric layer and directly contacting at least a portion of both the active region and the extension portion of the active region overlying the second device isolation layer.
摘要翻译：形成半导体器件的方法可以包括在半导体衬底中形成沟槽以限定有源区。沟槽填充有第一器件隔离层。第一器件隔离层的一部分被蚀刻以将第一器件隔离层的顶表面凹陷在半导体衬底的有源区的相邻顶表面下方并且部分地暴露有源区的侧壁。有源区的暴露的侧壁被外延生长以形成有源区的延伸部分，部分地延伸穿过沟槽中的第一器件隔离层的顶表面。第二器件隔离层形成在沟槽中凹陷的第一器件隔离层上。蚀刻第二器件隔离层以暴露有源区的延伸部分的顶表面，并且将第二器件隔离层的一部分留在沟槽的相对侧上的有源区的延伸部分之间。在半导体衬底和第二器件隔离层上形成层间电介质。形成延伸穿过层间介电层并且直接接触覆盖在第二器件隔离层上的有源区域和有源区域的延伸部分的至少一部分的导电接触。

10. 发明授权

US06953744B2 Methods of fabricating integrated circuit devices providing improved short prevention 有权
公开(公告)号：US06953744B2
公开(公告)日：2005-10-11
申请号：US10706647
申请日：2003-11-12
申请人： Hyoung-Joon Kim , Young-Wook Park , Byeong-Yun Nam
发明人： Hyoung-Joon Kim , Young-Wook Park , Byeong-Yun Nam
IPC分类号： H01L21/28 , H01L21/302 , H01L21/3065 , H01L21/3205 , H01L21/60 , H01L21/768 , H01L21/8242 , H01L23/522 , H01L27/10 , H01L27/108 , H01L21/4763
CPC分类号： H01L21/76831 , H01L21/76885 , H01L21/76897 , H01L27/10855 , H01L27/10885
摘要： The present invention provides methods of fabricating integrated circuit devices that include a microelectronic substrate and a conductive layer disposed on the microelectronic substrate. An insulating layer is disposed on the conductive layer and the insulating layer includes an overhanging portion that extends beyond the conductive layer. A sidewall insulating region is disposed laterally adjacent to a sidewall of the conductive layer and extends between the overhanging portion of the insulating layer and the microelectronic substrate.

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