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1. 发明授权

US07867841B2 Methods of forming semiconductor devices with extended active regions 有权
标题翻译：形成具有扩展活性区域的半导体器件的方法
公开(公告)号：US07867841B2
公开(公告)日：2011-01-11
申请号：US11968242
申请日：2008-01-02
申请人： Dong-Chan Lim , Byeong-Yun Nam , Soo-Ik Jang , In-Soo Jung
发明人： Dong-Chan Lim , Byeong-Yun Nam , Soo-Ik Jang , In-Soo Jung
IPC分类号： H01L21/8238
CPC分类号： H01L21/76283 , H01L21/84 , H01L27/10873 , H01L27/1203
摘要： A method of forming a semiconductor device can include forming a trench in a semiconductor substrate to define an active region. The trench is filled with a first device isolation layer. A portion of the first device isolation layer is etched to recess a top surface of the first device isolation layer below an adjacent top surface of the active region of the semiconductor substrate and to partially expose a sidewall of the active region. The exposed sidewall of the active region is epitaxially grown to form an extension portion of the active region that extends partially across the top surface of the first device isolation layer in the trench. A second device isolation layer is formed on the recessed first device isolation layer in the trench. The second device isolation layer is etched to expose a top surface of the extension portion of the active region and leave a portion of the second device isolation layer between extension portions of active regions on opposite sides of the trench. An interlayer dielectric is formed on the semiconductor substrate and the second device isolation layer. A conductive contact is formed extending through the interlayer dielectric layer and directly contacting at least a portion of both the active region and the extension portion of the active region overlying the second device isolation layer.
摘要翻译：形成半导体器件的方法可以包括在半导体衬底中形成沟槽以限定有源区。沟槽填充有第一器件隔离层。第一器件隔离层的一部分被蚀刻以将第一器件隔离层的顶表面凹陷在半导体衬底的有源区的相邻顶表面下方并且部分地暴露有源区的侧壁。有源区的暴露的侧壁被外延生长以形成有源区的延伸部分，部分地延伸穿过沟槽中的第一器件隔离层的顶表面。第二器件隔离层形成在沟槽中凹陷的第一器件隔离层上。蚀刻第二器件隔离层以暴露有源区的延伸部分的顶表面，并且将第二器件隔离层的一部分留在沟槽的相对侧上的有源区的延伸部分之间。在半导体衬底和第二器件隔离层上形成层间电介质。形成延伸穿过层间介电层并且直接接触覆盖在第二器件隔离层上的有源区域和有源区域的延伸部分的至少一部分的导电接触。

2. 发明申请

US20080157262A1 SEMICONDUCTOR DEVICES WITH EXTENDED ACTIVE REGIONS AND METHODS OF FORMING THE SAME 有权
标题翻译：具有扩展活动区域的半导体器件及其形成方法
公开(公告)号：US20080157262A1
公开(公告)日：2008-07-03
申请号：US11968242
申请日：2008-01-02
申请人： Dong-Chan Lim , Byeong-Yun Nam , Soo-Ik Jang , In-Soo Jung
发明人： Dong-Chan Lim , Byeong-Yun Nam , Soo-Ik Jang , In-Soo Jung
IPC分类号： H01L27/00 , H01L21/76
CPC分类号： H01L21/76283 , H01L21/84 , H01L27/10873 , H01L27/1203
摘要： A method of forming a semiconductor device can include forming a trench in a semiconductor substrate to define an active region. The trench is filled with a first device isolation layer. A portion of the first device isolation layer is etched to recess a top surface of the first device isolation layer below an adjacent top surface of the active region of the semiconductor substrate and to partially expose a sidewall of the active region. The exposed sidewall of the active region is epitaxially grown to form an extension portion of the active region that extends partially across the top surface of the first device isolation layer in the trench. A second device isolation layer is formed on the recessed first device isolation layer in the trench. The second device isolation layer is etched to expose a top surface of the extension portion of the active region and leave a portion of the second device isolation layer between extension portions of active regions on opposite sides of the trench. An interlayer dielectric is formed on the semiconductor substrate and the second device isolation layer. A conductive contact is formed extending through the interlayer dielectric layer and directly contacting at least a portion of both the active region and the extension portion of the active region overlying the second device isolation layer.
摘要翻译：形成半导体器件的方法可以包括在半导体衬底中形成沟槽以限定有源区。沟槽填充有第一器件隔离层。第一器件隔离层的一部分被蚀刻以将第一器件隔离层的顶表面凹陷在半导体衬底的有源区的相邻顶表面下方并且部分地暴露有源区的侧壁。有源区的暴露的侧壁被外延生长以形成有源区的延伸部分，部分地延伸穿过沟槽中的第一器件隔离层的顶表面。第二器件隔离层形成在沟槽中凹陷的第一器件隔离层上。蚀刻第二器件隔离层以暴露有源区的延伸部分的顶表面，并且将第二器件隔离层的一部分留在沟槽的相对侧上的有源区的延伸部分之间。在半导体衬底和第二器件隔离层上形成层间电介质。形成延伸穿过层间介电层并且直接接触覆盖在第二器件隔离层上的有源区域和有源区域的延伸部分的至少一部分的导电接触。

3. 发明授权

US08497157B2 Method of manufacturing a semiconductor device and method of manufacturing a semiconductor package including the same 有权
标题翻译：制造半导体器件的方法及其制造方法
公开(公告)号：US08497157B2
公开(公告)日：2013-07-30
申请号：US13459468
申请日：2012-04-30
申请人： Kwang-Jin Moon , Byung-Lyul Park , Do-Sun Lee , Gil-Heyun Choi , Suk-Chul Bang , Dong-Chan Lim , Deok-Young Jung
发明人： Kwang-Jin Moon , Byung-Lyul Park , Do-Sun Lee , Gil-Heyun Choi , Suk-Chul Bang , Dong-Chan Lim , Deok-Young Jung
IPC分类号： H01L21/00 , H01L21/324
CPC分类号： H01L21/2885 , H01L21/76898 , H01L25/0657 , H01L2224/16145 , H01L2224/16225 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/15311
摘要： In a method of manufacturing a semiconductor device, a front end of line (FEOL) process may be performed on a semiconductor substrate to form a semiconductor structure. A back end of line (BEOL) process may be performed on the semiconductor substrate to form a wiring structure electrically connected to the semiconductor structure, thereby formed a semiconductor chip. A hole may be formed through a part of the semiconductor chip. A preliminary plug may have a dimple in the hole. The preliminary plug may be expanded into the dimple by a thermal treatment process to form a plug. Thus, the plug may not have a protrusion protruding from the upper surface of the semiconductor chip, so that the plug may be formed by the single CMP process.
摘要翻译：在制造半导体器件的方法中，可以在半导体衬底上执行前端（FEOL）工艺以形成半导体结构。可以在半导体基板上进行后端（BEOL）处理，以形成与半导体结构电连接的布线结构，从而形成半导体芯片。可以通过半导体芯片的一部分形成孔。初步插头可能在孔中有一个凹坑。预先塞子可以通过热处理过程扩展到凹坑中以形成塞子。因此，插头可以不具有从半导体芯片的上表面突出的突起，从而可以通过单个CMP工艺形成插头。

4. 发明申请

US20120132986A1 SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120132986A1
公开(公告)日：2012-05-31
申请号：US13251676
申请日：2011-10-03
申请人： Pil-Kyu Kang , Dae-Lok Bae , Gil-Heyun Choi , Suk-Chul Bang , Byung-Lyul Park , Kwang-Jin Moon , Dong-Chan Lim , Deok-Young Jung
发明人： Pil-Kyu Kang , Dae-Lok Bae , Gil-Heyun Choi , Suk-Chul Bang , Byung-Lyul Park , Kwang-Jin Moon , Dong-Chan Lim , Deok-Young Jung
IPC分类号： H01L29/78 , H01L27/092 , H01L21/8238
CPC分类号： H01L27/088 , H01L21/823487 , H01L27/1207
摘要： A semiconductor device includes a substrate having a plurality of horizontal channel transistors formed thereon, an insulation layer structure on the substrate and covering the horizontal transistors, and a plurality of vertical channel transistors on the insulation layer structure.
摘要翻译：半导体器件包括其上形成有多个水平沟道晶体管的衬底，在衬底上的绝缘层结构并覆盖水平晶体管，以及在绝缘层结构上的多个垂直沟道晶体管。

5. 发明授权

US08065366B2 System and method for transmitting personal networking-based blog post, and server applied to the same 有权
标题翻译：基于个人网络的博客文章传输的系统和方法，以及应用于服务器的服务器
公开(公告)号：US08065366B2
公开(公告)日：2011-11-22
申请号：US12676620
申请日：2008-10-17
申请人： Chang-Su Lee , Dong-Chan Lim , Su-Kyung Kim , Sung Kim , Sil-Keun Hwang
发明人： Chang-Su Lee , Dong-Chan Lim , Su-Kyung Kim , Sung Kim , Sil-Keun Hwang
IPC分类号： G06F15/16
CPC分类号： G06Q30/02 , G06Q10/10 , H04L51/32
摘要： Disclosed are a system and method for distributing a blog post based on personal networking, and a server to be applied thereto. The system includes a writer terminal unit, which makes a series of settings for forming a blog post containing contents posted by a writer through the writer's blog registered with an online community service, and then distributes the blog post to at least one or more acquaintances blogs registered to personal networking with the writer, sharer/distributor terminal units, which make setting for posting the blog post on the acquaintances blogs, or distributing the blog post to at least one or more other acquaintances blogs registered to personal networking with sharers/distributors, and a service management server, which differentially provides management authority for the blog post to each of the writer and the sharers/distributors, and integrally manages the blog post distributed to a plurality of blogs, based on a path along which the blog post is distributed. The system and method distributes a blog post containing a writer's specific purpose of posting, such as a help-wanted notice, step by step through blogs registered with an online community service, based on trust relationships, thereby providing a notice platform, which is so efficient that an advertiser who writes a blog post, such as a help-wanted notice, can quickly find a qualified person, based on his/her trust relationships.
摘要翻译：公开了一种用于基于个人网络分发博客文章的系统和方法以及要应用于其的服务器。该系统包括一个作家终端单元，其用于形成博客文章的一系列设置，其中包含由作者通过在线社区服务注册的作者的博客发布的内容，然后将该博客文章分发到至少一个或多个熟人博客注册到与作者，分销商/分销商终端单元的个人网络，这些终端单元在熟人博客上发布博客文章的设置，或者将博客文章分发到至少一个或多个其他熟人登记到与共享者/分发者的个人网络的博客，以及服务管理服务器，其基于分发给博客文章的路径，分散到多个博客的博客文章，分别向每个作者和共享者/分发者提供博客文章的管理权限，并且整合管理博客帖子。系统和方法基于信任关系分发包含作者特定发布目的的博客文章，如帮助通知，逐步通过在线社区服务注册的博客，从而提供通知平台撰写博客文章的广告客户（例如帮助通知）可以根据他/她的信任关系快速找到合格的人员。

6. 发明申请

US20050282338A1 Methods of forming gate patterns using isotropic etching of gate insulating layers 审中-公开
标题翻译：使用各向同性蚀刻栅极绝缘层形成栅极图案的方法
公开(公告)号：US20050282338A1
公开(公告)日：2005-12-22
申请号：US11153653
申请日：2005-06-15
申请人： Jong-Ryeol Yoo , Gil-Heyun Choi , Chang-Won Lee , Byung-Hak Lee , Hee-Sook Park , Dong-Chan Lim , Sun-Pil Youn , Woong-Hee Sohn
发明人： Jong-Ryeol Yoo , Gil-Heyun Choi , Chang-Won Lee , Byung-Hak Lee , Hee-Sook Park , Dong-Chan Lim , Sun-Pil Youn , Woong-Hee Sohn
IPC分类号： H01L21/28 , H01L21/302 , H01L21/336 , H01L21/461 , H01L21/4763 , H01L21/8234 , H01L29/423 , H01L29/49 , H01L29/51
CPC分类号： H01L21/28114 , H01L21/28061 , H01L21/28247 , H01L21/823462 , H01L29/42376 , H01L29/4941 , H01L29/517
摘要： A method for forming a gate pattern of a semiconductor device can include isotropically etching a gate insulating layer located between a gate conductive layer pattern and a substrate to recess an exposed side wall of the gate insulating layer pattern beyond a lower corner of the gate conductive layer pattern to form an undercut region. The gate conductive layer pattern can be treated to round off the lower corner.
摘要翻译：用于形成半导体器件的栅极图案的方法可以包括各向同性蚀刻位于栅极导电层图案和衬底之间的栅极绝缘层，以将栅极绝缘层图案的暴露的侧壁超出栅极导电层的下角形成底切区域。可以对栅极导电层图案进行处理以从下角四舍五入。

7. 发明申请

US20120039564A1 Photoelectric Integrated Circuit Devices And Methods Of Forming The Same 审中-公开
标题翻译：光电集成电路器件及其形成方法
公开(公告)号：US20120039564A1
公开(公告)日：2012-02-16
申请号：US13191874
申请日：2011-07-27
申请人： Pil-Kyu Kang , GilHeyun Choi , Sukchul Bang , Daelok Bae , Byung-Lyul Park , KwangJin Moon , Dong-Chan Lim , Deok-Young Jung
发明人： Pil-Kyu Kang , GilHeyun Choi , Sukchul Bang , Daelok Bae , Byung-Lyul Park , KwangJin Moon , Dong-Chan Lim , Deok-Young Jung
IPC分类号： G02B6/12
CPC分类号： G02B6/131 , G02B6/132 , G02B6/136 , G02B2006/12061
摘要： A photoelectric integrated circuit device may include a substrate including an electronic device region and an on die optical input/output device region, the substrate having a trench in the on die optical input/output device region; a lower clad layer provided in the trench, the lower clad layer having an upper surface lower than a surface of the substrate; a core provided on the lower clad layer; an insulating pattern provided on the core; an optical detection pattern provided on the insulating pattern, the optical detection pattern having at least a portion provided in the trench; and at least one transistor provided on the substrate of the electronic device region.
摘要翻译：光电集成电路器件可以包括包括电子器件区域和裸片上的光输入/输出器件区域的衬底，所述衬底在管芯光输入/输出器件区域中具有沟槽; 设置在所述沟槽中的下包层，所述下包层具有比所述基板的表面低的上表面; 设置在下包层上的芯; 设置在芯上的绝缘图案; 设置在所述绝缘图案上的光学检测图案，所述光学检测图案具有设置在所述沟槽中的至少一部分; 以及设置在电子器件区域的衬底上的至少一个晶体管。

8. 发明申请

US20110318923A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME INCLUDING A CONDUCTIVE STRUCTURE IS FORMED THROUGH AT LEAST ONE DIELECTRIC LAYER AFTER FORMING A VIA STRUCTURE 有权
标题翻译：半导体器件及其制造方法，包括导电结构在形成一个结构之后通过至少一个介电层形成
公开(公告)号：US20110318923A1
公开(公告)日：2011-12-29
申请号：US12913753
申请日：2010-10-27
申请人： Byung-Lyul Park , Gil-Heyun Choi , Suk-Chul Bang , Kwang-Jin Moon , Dong-Chan Lim , Deok-Young Jung
发明人： Byung-Lyul Park , Gil-Heyun Choi , Suk-Chul Bang , Kwang-Jin Moon , Dong-Chan Lim , Deok-Young Jung
IPC分类号： H01L21/768
CPC分类号： H01L21/76898 , H01L21/76801 , H01L25/0657 , H01L25/18 , H01L2224/16 , H01L2225/06513 , H01L2225/06541
摘要： For forming a semiconductor device, a via structure is formed through at least one dielectric layer and at least a portion of a substrate. In addition, a protective buffer layer is formed onto the via structure. Furthermore, a conductive structure for an integrated circuit is formed over the substrate after forming the via structure and the protective buffer layer, with the conductive structure not being formed over the via structure. Thus, deterioration of the conductive and via structures is minimized.
摘要翻译：为了形成半导体器件，通过至少一个电介质层和至少一部分衬底形成通孔结构。此外，在通孔结构上形成保护缓冲层。此外，在形成通孔结构和保护缓冲层之后，在衬底上形成用于集成电路的导电结构，其中导电结构不在过孔结构上形成。因此，导电和通孔结构的劣化被最小化。

9. 发明授权

US07875939B2 Semiconductor device including an ohmic layer 有权
标题翻译：包括欧姆层的半导体器件
公开(公告)号：US07875939B2
公开(公告)日：2011-01-25
申请号：US12453198
申请日：2009-05-01
申请人： Hee-Sook Park , Gil-Heyun Choi , Chang-Won Lee , Byung-Hak Lee , Sun-Pil Youn , Dong-Chan Lim , Jae-Hwa Park , Jang-Hee Lee , Woong-Hee Sohn
发明人： Hee-Sook Park , Gil-Heyun Choi , Chang-Won Lee , Byung-Hak Lee , Sun-Pil Youn , Dong-Chan Lim , Jae-Hwa Park , Jang-Hee Lee , Woong-Hee Sohn
IPC分类号： H01L23/532
CPC分类号： H01L29/4933 , C23C16/42 , H01L21/28061 , H01L21/28194 , H01L21/28556 , H01L21/76846 , H01L29/517
摘要： In an ohmic layer and methods of forming the ohmic layer, a gate structure including the ohmic layer and a metal wiring having the ohmic layer, the ohmic layer is formed using tungsten silicide that includes tungsten and silicon with an atomic ratio within a range of about 1:5 to about 1:15. The tungsten silicide may be obtained in a chamber using a reaction gas including a tungsten source gas and a silicon source gas by a partial pressure ratio within a range of about 1.0:25.0 to about 1.0:160.0. The reaction gas may have a partial pressure within a range of about 2.05 percent to about 30.0 percent of a total internal pressure of the chamber. When the ohmic layer is employed for a conductive structure, such as a gate structure or a metal wiring, the conductive structure may have a reduced resistance.
摘要翻译：在欧姆层和形成欧姆层的方法中，包括欧姆层的栅极结构和具有欧姆层的金属布线，欧姆层使用包含钨和硅的硅化钨形成，原子比在约 1:5至约1:15。可以在室内使用包含钨源气体和硅源气体的反应气体，在约1.0:25.0至约1.0:16.0.0的范围内的分压比获得硅化钨。反应气体可以具有在室的总内部压力的约2.05％至约30.0％的范围内的分压。当欧姆层用于诸如栅极结构或金属布线的导电结构时，导电结构可以具有降低的电阻。

10. 发明授权

US07544597B2 Method of forming a semiconductor device including an ohmic layer 有权
标题翻译：形成包括欧姆层的半导体器件的方法
公开(公告)号：US07544597B2
公开(公告)日：2009-06-09
申请号：US11332476
申请日：2006-01-17
申请人： Hee-Sook Park , Gil-Heyun Choi , Chang-Won Lee , Byung-Hak Lee , Sun-Pil Youn , Dong-Chan Lim , Jae-Hwa Park , Jang-Hee Lee , Woong-Hee Sohn
发明人： Hee-Sook Park , Gil-Heyun Choi , Chang-Won Lee , Byung-Hak Lee , Sun-Pil Youn , Dong-Chan Lim , Jae-Hwa Park , Jang-Hee Lee , Woong-Hee Sohn
IPC分类号： H01L21/44
CPC分类号： H01L29/4933 , C23C16/42 , H01L21/28061 , H01L21/28194 , H01L21/28556 , H01L21/76846 , H01L29/517
摘要： In an ohmic layer and methods of forming the ohmic layer, a gate structure including the ohmic layer and a metal wiring having the ohmic layer, the ohmic layer is formed using tungsten silicide that includes tungsten and silicon with an atomic ratio within a range of about 1:5 to about 1:15. The tungsten silicide may be obtained in a chamber using a reaction gas including a tungsten source gas and a silicon source gas by a partial pressure ratio within a range of about 1.0:25.0 to about 1.0:160.0. The reaction gas may have a partial pressure within a range of about 2.05 percent to about 30.0 percent of a total internal pressure of the chamber. When the ohmic layer is employed for a conductive structure, such as a gate structure or a metal wiring, the conductive structure may have a reduced resistance.
摘要翻译：在欧姆层和形成欧姆层的方法中，包括欧姆层的栅极结构和具有欧姆层的金属布线，欧姆层使用包含钨和硅的钨硅化物形成，原子比在约 1:5至约1:15。可以在室内使用包含钨源气体和硅源气体的反应气体，在约1.0:25.0至约1.0:16.0.0的范围内的分压比获得硅化钨。反应气体可以具有在室的总内部压力的约2.05％至约30.0％的范围内的分压。当欧姆层用于诸如栅极结构或金属布线的导电结构时，导电结构可以具有降低的电阻。

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