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1. 发明申请

US20090033375A1 METHOD AND APPARATUS FOR IDENTIFYING AND REDUCING SPURIOUS FREQUENCY COMPONENTS 有权
标题翻译：识别和减少兴趣频率分量的方法和装置
公开(公告)号：US20090033375A1
公开(公告)日：2009-02-05
申请号：US12170401
申请日：2008-07-09
申请人： Solomon Max , Christopher Joel Hannaford , R. Warren Necoechea
发明人： Solomon Max , Christopher Joel Hannaford , R. Warren Necoechea
IPC分类号： H03B21/00
CPC分类号： G01R31/2841 , H03L7/06
摘要： A method for identifying and reducing spurious frequency components is provided. A method in accordance with at least one embodiment of the present disclosure may include generating a digital sinusoidal waveform at a direct digital synthesizer (DDS) and receiving the digital sinusoidal waveform at an audio digital-to-analog converter. The method may further include converting the digital sinusoidal waveform to an analog sinusoidal waveform containing spurious frequency components, combining the analog sinusoidal waveform with an analog distortion correction waveform to generate a composite output waveform and receiving the composite output waveform at notch filter circuitry. The method may also include filtering the composite output waveform to generate a filtered composite output waveform and amplifying a difference between the filtered composite output waveform and a signal from a circuit-under-test (CUT) to generate an amplified analog signal. The method may also include converting the amplified analog signal to an amplified digital signal. Of course, additional implementations are also within the scope of the present disclosure.
摘要翻译：提供了用于识别和减少杂散频率分量的方法。根据本公开的至少一个实施例的方法可以包括在直接数字合成器（DDS）处生成数字正弦波形并且在音频数模转换器处接收数字正弦波形。该方法还可以包括将数字正弦波形转换为包含杂散频率分量的模拟正弦波形，将模拟正弦波形与模拟失真校正波形组合以产生复合输出波形并在陷波滤波器电路处接收复合输出波形。该方法还可以包括对复合输出波形进行滤波以产生经滤波的复合输出波形，并且放大滤波的复合输出波形与来自被测电路（CUT）的信号之间的差以产生放大的模拟信号。该方法还可以包括将放大的模拟信号转换成放大的数字信号。当然，额外的实现也在本公开的范围内。

2. 发明授权

US06728651B1 Methods and apparatuses for digitally tuning a phased-lock loop circuit 有权
标题翻译：用于数字调谐锁相环电路的方法和装置
公开(公告)号：US06728651B1
公开(公告)日：2004-04-27
申请号：US10097904
申请日：2002-03-13
申请人： Tim Alton , Wai-Kong Chen , Michael Davis , Warren Necoechea
发明人： Tim Alton , Wai-Kong Chen , Michael Davis , Warren Necoechea
IPC分类号： G06F1900
CPC分类号： H03L7/085
摘要： A phase-locked loop circuit having a programmable tuning voltage. As the input reference clock frequency is changed, the tuning voltage is changed accordingly to compensate for the propagation delay through the phase detector and thereby reduce discrepancies in the phase relationship between the input reference clock signal and the output clock signal at different frequencies. A set of compensation values corresponding to input reference clock frequencies are stored in a memory device. When the input reference clock frequency is changed, a corresponding compensation value is programmed to a digital-to-analog converter (DAC). The DAC outputs a voltage that is proportional to the value of the digital input to the DAC and can thus be used to regulate the tuning voltage of the PLL circuit so that the relationship of the input reference clock signal to the output clock signal remains stable with frequency changes.
摘要翻译：具有可编程调谐电压的锁相环电路。随着输入参考时钟频率的改变，调谐电压相应地被改变以补偿通过相位检测器的传播延迟，从而减少输入参考时钟信号和不同频率处的输出时钟信号之间的相位关系的差异。对应于输入参考时钟频率的一组补偿值被存储在存储器件中。当输入参考时钟频率改变时，相应的补偿值被编程到数模转换器（DAC）。 DAC输出与DAC的数字输入值成比例的电压，因此可用于调节PLL电路的调谐电压，使得输入参考时钟信号与输出时钟信号的关系保持稳定，频率变化。

3. 发明授权

US4572971A Tri-state driver circuit for automatic test equipment 失效
标题翻译：用于自动测试设备的三态驱动电路
公开(公告)号：US4572971A
公开(公告)日：1986-02-25
申请号：US585477
申请日：1984-03-02
申请人： R. Warren Necoechea
发明人： R. Warren Necoechea
IPC分类号： G01R31/28 , H03K17/60 , H03K17/74 , H03K19/082 , H03K5/00
CPC分类号： G01R31/28 , H03K17/603 , H03K17/74 , H03K19/0823
摘要： A tri-state driver circuit 10 for selectively driving a node of a device under test by applying and switching between two reference voltages, and for selectively operating at a high impedance output state. Two current sources 16 and 18 provide a bridge current that flows through a diode bridge 20 to establish, at nodes A and B, voltages that equal two reference voltages, DRH and DRL. The diode bridge includes resistors R11 and R16 across which the bridge current is switched to accommodate small voltage swings, and also includes clamp diodes CR3-6 to accommodate large voltage swings. A current switch 22 controls the direction of the bridge current and the selection of which of the two reference voltages appears at node A. A current sink 36, 38, and 40 monitors the average voltage of the diode bridge and adjusts it to equal the average of the two reference voltages. A feedback circuit 42, 44, and 46 monitors the higher of the voltages at nodes A and B and adjusts it to equal the higher of the two reference voltages. A transistor-diode bridge 48 operates as a buffer to generate an output signal equal in voltage to the voltage at node A. A switch controller 50 switches the transistor-diode bridge to a high impedance output state when so selected.
摘要翻译：三状态驱动电路10，用于通过在两个参考电压之间施加和切换来选择性地驱动被测器件的节点，并且用于选择性地以高阻抗输出状态工作。两个电流源16和18提供流过二极管电桥20的桥电流，以在节点A和B处建立等于两个参考电压DRH和DRL的电压。二极管桥包括电阻器R11和R16，桥接电流被切换到其上以适应小的电压摆幅，并且还包括钳位二极管CR3-6以适应大的电压摆幅。电流开关22控制桥电流的方向，并选择两个参考电压中的哪一个出现在节点A处。电流吸收器36,38和40监视二极管电桥的平均电压并将其调整为等于平均值的两个参考电压。反馈电路42,44和46监视节点A和B处的较高电压，并将其调整为等于两个参考电压中的较高者。晶体管二极管桥48作为缓冲器工作，以产生与节点A处的电压相等的电压的输出信号。当如此选择时，开关控制器50将晶体管二极管桥接器切换到高阻抗输出状态。

4. 发明授权

US08269480B2 Method and apparatus for identifying and reducing spurious frequency components 有权
标题翻译：用于识别和减少杂散频率分量的方法和装置
公开(公告)号：US08269480B2
公开(公告)日：2012-09-18
申请号：US12170401
申请日：2008-07-09
申请人： Solomon Max , Christopher Joel Hannaford , R. Warren Necoechea
发明人： Solomon Max , Christopher Joel Hannaford , R. Warren Necoechea
IPC分类号： G01R19/00
CPC分类号： G01R31/2841 , H03L7/06
摘要： A method for identifying and reducing spurious frequency components is provided. A method in accordance with at least one embodiment of the present disclosure may include generating a digital sinusoidal waveform at a direct digital synthesizer (DDS) and receiving the digital sinusoidal waveform at an audio digital-to-analog converter. The method may further include converting the digital sinusoidal waveform to an analog sinusoidal waveform containing spurious frequency components, combining the analog sinusoidal waveform with an analog distortion correction waveform to generate a composite output waveform and receiving the composite output waveform at notch filter circuitry. The method may also include filtering the composite output waveform to generate a filtered composite output waveform and amplifying a difference between the filtered composite output waveform and a signal from a circuit-under-test (CUT) to generate an amplified analog signal. The method may also include converting the amplified analog signal to an amplified digital signal. Of course, additional implementations are also within the scope of the present disclosure.
摘要翻译：提供了用于识别和减少杂散频率分量的方法。根据本公开的至少一个实施例的方法可以包括在直接数字合成器（DDS）处生成数字正弦波形并且在音频数模转换器处接收数字正弦波形。该方法还可以包括将数字正弦波形转换为包含杂散频率分量的模拟正弦波形，将模拟正弦波形与模拟失真校正波形组合以产生复合输出波形并在陷波滤波器电路处接收复合输出波形。该方法还可以包括对复合输出波形进行滤波以产生经滤波的复合输出波形，并且放大滤波的复合输出波形与来自被测电路（CUT）的信号之间的差以产生放大的模拟信号。该方法还可以包括将放大的模拟信号转换成放大的数字信号。当然，额外的实现也在本公开的范围内。

5. 发明授权

US4647796A Multiple level voltage comparator circuit 失效
标题翻译：多电平电压比较电路
公开(公告)号：US4647796A
公开(公告)日：1987-03-03
申请号：US472426
申请日：1983-04-25
申请人： R. Warren Necoechea
发明人： R. Warren Necoechea
IPC分类号： G01R19/165 , G01D21/00 , H03K5/08 , H03K5/24 , H03K5/153
CPC分类号： H03K5/2418
摘要： A high speed voltage comparator circuit is disclosed which accepts a wide range of input potentials CBO1 and compares them with four potential levels CRH, CRL, CRIH, and CRIL. Each comparator includes input transistors Q103 and Q104, one of which is connected to the reference potential and the other is connected to the unknown potential. The emitters of the input transistors Q103 and Q104 are connected together through a resistor R105, and each emitter is connected to a current source, Q105 and Q107 respectively. A third current source Q106 is coupled to diodes D101 and D102 which are connected to the emitters of transistors Q103 and Q104 respectively. The difference between the reference potential and the unknown potential will forward bias one of the diodes and reverse bias the other. The resulting difference in emitter current between the input transistors Q103 and Q104 is detected by an output stage to indicate the relative magnitudes of the reference potential and the unknown potential.
摘要翻译：公开了一种高速电压比较器电路，其接受宽范围的输入电位CBO1并将其与四个电位电平CRH，CRL，CRIH和CRIL进行比较。每个比较器包括输入晶体管Q103和Q104，其中一个连接到参考电位，另一个连接到未知电位。输入晶体管Q103和Q104的发射极通过电阻器R105连接在一起，并且每个发射极分别连接到电流源Q105和Q107。第三电流源Q106耦合到分别连接到晶体管Q103和Q104的发射极的二极管D101和D102。参考电位和未知电位之间的差异将正向偏置二极管之一并反向偏置另一个。通过输出级检测输入晶体管Q103和Q104之间的发射极电流的差异，以指示参考电位和未知电位的相对幅度。

6. 发明授权

US4594544A Participate register for parallel loading pin-oriented registers in test equipment 失效
标题翻译：在测试设备中并行加载引脚定位寄存器的参与寄存器
公开(公告)号：US4594544A
公开(公告)日：1986-06-10
申请号：US472427
申请日：1983-03-07
申请人： R. Warren Necoechea
发明人： R. Warren Necoechea
IPC分类号： G01R31/18 , G01R31/28 , G01R31/317 , G01R31/319 , G01R15/12 , H03K17/00
CPC分类号： G01R31/31908
摘要： An automatic test system for parallel loading of data into pin registers 100 associated with pins of a device being tested includes data bus 130 for transmitting data; an address bus 120 for transmitting addresses; a set of pin registers 100, each having a unique address and each coupled to receive information from the data bus 130; a participate register 150 coupled to data bus 130 and to each of registers 100 for enabling selected ones of registers 100 to receive data from the data bus at the same time; an address decoder 110, 180 connected to the address bus 120, to each of registers 100, and to the participate register 150, for enabling one of the pin registers 100 or the participate register 150 to receive data from the data bus, the data for the participate register 150 comprising the addresses of each of the selected ones of pin registers 100 which are to receive data from the data bus in parallel.
摘要翻译：用于将数据并行加载到与所测试的设备的引脚相关联的引脚寄存器100中的自动测试系统包括用于传输数据的数据总线130; 用于发送地址的地址总线120; 一组引脚寄存器100，每个引脚寄存器100具有唯一的地址，并且每个引脚寄存器100被耦合以从数据总线130接收信息; 耦合到数据总线130和每个寄存器100的参与寄存器150，用于使所选择的寄存器100能够同时从数据总线接收数据; 连接到地址总线120的地址解码器110,180，到每个寄存器100，以及参与寄存器150，用于使引脚寄存器100或参与寄存器150中的一个能够从数据总线接收数据，参与寄存器150包括并行地从数据总线接收数据的每个引脚寄存器100中的每一个的地址。

7. 发明申请

US20110193547A1 METHOD AND APPARATUS FOR IDENTIFYING AND REDUCING SPURIOUS FREQUENCY COMPONENTS 有权
标题翻译：识别和减少兴趣频率分量的方法和装置
公开(公告)号：US20110193547A1
公开(公告)日：2011-08-11
申请号：US13090560
申请日：2011-04-20
申请人： Solomon Max , Christopher Joel Hannaford , R. Warren Necoechea
发明人： Solomon Max , Christopher Joel Hannaford , R. Warren Necoechea
IPC分类号： G01R23/00
CPC分类号： G01R31/2841 , H03L7/06
摘要： A method for identifying and reducing spurious frequency components is provided. A method in accordance with at least one embodiment of the present disclosure may include generating a digital sinusoidal waveform at a direct digital synthesizer (DDS) and receiving the digital sinusoidal waveform at an audio digital-to-analog converter. The method may further include converting the digital sinusoidal waveform to an analog sinusoidal waveform containing spurious frequency components, combining the analog sinusoidal waveform with an analog distortion correction waveform to generate a composite output waveform and receiving the composite output waveform at notch filter circuitry. The method may also include filtering the composite output waveform to generate a filtered composite output waveform and amplifying a difference between the filtered composite output waveform and a signal from a circuit-under-test (CUT) to generate an amplified analog signal. The method may also include converting the amplified analog signal to an amplified digital signal. Of course, additional implementations are also within the scope of the present disclosure.
摘要翻译：提供了用于识别和减少杂散频率分量的方法。根据本公开的至少一个实施例的方法可以包括在直接数字合成器（DDS）处生成数字正弦波形并且在音频数模转换器处接收数字正弦波形。该方法还可以包括将数字正弦波形转换为包含杂散频率分量的模拟正弦波形，将模拟正弦波形与模拟失真校正波形组合以产生复合输出波形并在陷波滤波器电路处接收复合输出波形。该方法还可以包括对复合输出波形进行滤波以产生经滤波的复合输出波形，并且放大滤波的复合输出波形与来自被测电路（CUT）的信号之间的差以产生放大的模拟信号。该方法还可以包括将放大的模拟信号转换成放大的数字信号。当然，额外的实现也在本公开的范围内。

8. 发明授权

US07849374B1 Testing a transceiver 有权
标题翻译：测试收发器
公开(公告)号：US07849374B1
公开(公告)日：2010-12-07
申请号：US11546806
申请日：2006-10-11
申请人： R. Warren Necoechea , Timothy Burnett , Fengming Zhang , Harry Hou
发明人： R. Warren Necoechea , Timothy Burnett , Fengming Zhang , Harry Hou
IPC分类号： G01R31/28
CPC分类号： H04B5/0093 , G01R31/3171
摘要： A filter includes at least a pin diode, an inductive element, and a varactor diode coupled as a resonant circuit. The filter injects data dependent jitter into a digital data signal with a given data rate for testing a transceiver.
摘要翻译：滤波器至少包括作为谐振电路耦合的pin二极管，电感元件和变容二极管。滤波器将数据相关抖动注入具有给定数据速率的数字数据信号，以测试收发器。

9. 发明授权

US07512857B1 Pattern correction circuit 失效
标题翻译：图案校正电路
公开(公告)号：US07512857B1
公开(公告)日：2009-03-31
申请号：US11193873
申请日：2005-07-29
申请人： Warren Necoechea , Timothy Alton , Mark Deome , Henk Zantman
发明人： Warren Necoechea , Timothy Alton , Mark Deome , Henk Zantman
IPC分类号： G06F11/00
CPC分类号： G06F11/26 , G01R31/318307 , G01R31/318371
摘要： A method is described for facilitating use of a first pattern utilizing XOR data formatting in an electronic tester. The method includes dividing the first pattern into at least a first group and a second group, the tester to successively execute the first group and the second group. The method further includes assuming an entry state for each group is one of two binary conditions and inverting programmed commands for the second group if an ending state of the first group is not equal to the assumed entry state.
摘要翻译：描述了一种在电子测试仪中利用利用XOR数据格式化的第一图案的方法。该方法包括将第一图案划分成至少第一组和第二组，测试器连续地执行第一组和第二组。该方法还包括假设如果第一组的结束状态不等于假定的进入状态，则每个组的进入状态是两个二进制条件之一，并且针对第二组反转编程的命令。

10. 发明授权

US08415941B2 Method and apparatus for identifying and reducing spurious frequency components 有权
标题翻译：用于识别和减少杂散频率分量的方法和装置
公开(公告)号：US08415941B2
公开(公告)日：2013-04-09
申请号：US13090560
申请日：2011-04-20
申请人： Solomon Max , Christopher Joel Hannaford , R. Warren Necoechea
发明人： Solomon Max , Christopher Joel Hannaford , R. Warren Necoechea
IPC分类号： G01R19/00
CPC分类号： G01R31/2841 , H03L7/06
摘要： A method for identifying and reducing spurious frequency components is provided. A method in accordance with at least one embodiment of the present disclosure may include generating a digital sinusoidal waveform at a direct digital synthesizer (DDS) and receiving the digital sinusoidal waveform at an audio digital-to-analog converter. The method may further include converting the digital sinusoidal waveform to an analog sinusoidal waveform containing spurious frequency components, combining the analog sinusoidal waveform with an analog distortion correction waveform to generate a composite output waveform and receiving the composite output waveform at notch filter circuitry. The method may also include filtering the composite output waveform to generate a filtered composite output waveform and amplifying a difference between the filtered composite output waveform and a signal from a circuit-under-test (CUT) to generate an amplified analog signal. The method may also include converting the amplified analog signal to an amplified digital signal. Of course, additional implementations are also within the scope of the present disclosure.
摘要翻译：提供了用于识别和减少杂散频率分量的方法。根据本公开的至少一个实施例的方法可以包括在直接数字合成器（DDS）处生成数字正弦波形并且在音频数模转换器处接收数字正弦波形。该方法还可以包括将数字正弦波形转换为包含杂散频率分量的模拟正弦波形，将模拟正弦波形与模拟失真校正波形组合以产生复合输出波形并在陷波滤波器电路处接收复合输出波形。该方法还可以包括对复合输出波形进行滤波以产生经滤波的复合输出波形，并且放大滤波的复合输出波形与来自被测电路（CUT）的信号之间的差以产生放大的模拟信号。该方法还可以包括将放大的模拟信号转换成放大的数字信号。当然，额外的实现也在本公开的范围内。

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