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    • 2. 发明授权
    • FET having a dielectrically isolated gate connect
    • 具有介电隔离栅极的FET连接
    • US5677554A
    • 1997-10-14
    • US435119
    • 1995-05-05
    • Stanley E. Swirhun
    • Stanley E. Swirhun
    • H01L21/335H01L21/76H01L29/778H01L31/0328
    • H01L29/66462H01L21/7605H01L29/7786
    • A HIGFET having a gate with a pad which is isolated from the FET heterostructure wafer by a dielectric layer to minimize leakage current between the gate and the wafer. The method of production of this device involves application of the gate metal only over the active area of the FET and a photo resist covering on the gate metal. The wafer, including the area covered by the photo resist, is covered with the dielectric layer. The photo resist layer is removed along with the dielectric layer from over the gate metal. Another layer of gate metal is formed on the preexisting gate metal including a gate pad on part of the remaining dielectric layer.
    • 具有栅极的HIGFET,其具有通过电介质层与FET异质结构晶片隔离的焊盘,以最小化栅极和晶片之间的漏电流。 该器件的制造方法包括仅在FET的有源区域上施加栅极金属,并在栅极金属上施加光刻胶。 包括由光致抗蚀剂覆盖的区域的晶片被电介质层覆盖。 与栅极金属上的电介质层一起除去光致抗蚀剂层。 在预先存在的栅极金属上形成另一层栅极金属,该栅极金属包括在剩余电介质层的一部分上的栅极焊盘。
    • 7. 发明授权
    • FET having minimized parasitic gate capacitance
    • FET具有最小的寄生栅极电容
    • US5461244A
    • 1995-10-24
    • US176599
    • 1994-01-03
    • Stanley E. Swirhun
    • Stanley E. Swirhun
    • H01L21/335H01L21/76H01L29/423H01L29/778H01L29/20H01L29/22
    • H01L29/66462H01L21/7605H01L29/42316H01L29/7784Y10S148/105
    • A HIGFET having a gate pad situated over a non conducting portion of the channel layer of the heterostructure wafer. The method of producing this device involves application of a very thin layer of gate metal on the wafer to protect the wafer surface during further processing. A photoresist coating is formed over the active area of the channel layer of the FET. An ion isolation implantation is applied to the wafer resulting in a non conducting portion of the channel layer that is not covered by the photoresist layer. The photoresist layer is removed and a thick layer of gate metal is applied on the thin layer of gate metal. The gate layers are fashioned into a pad over the non conducting portion of the channel layer and at least one finger over the conducting portion of the channel layer, resulting in the gate having minimized parasitic gate capacitance.
    • HIGFET具有位于异质结构晶片的沟道层的非导电部分之上的栅极焊盘。 制造该器件的方法包括在晶片上施加非常薄的栅极金属层,以在进一步处理期间保护晶片表面。 在FET的沟道层的有效区域上形成光致抗蚀剂涂层。 对晶片施加离子隔离注入,导致沟道层的不被光致抗蚀剂层覆盖的非导电部分。 去除光致抗蚀剂层,并且在栅极金属的薄层上施加厚的栅极金属层。 栅极层被形成沟道层的非导电部分上的焊盘,并且在沟道层的导电部分上方形成至少一个手指,导致栅极具有最小化的寄生栅极电容。
    • 8. 发明授权
    • Closely-spaced VCSEL and photodetector for applications requiring their independent operation
    • 紧密间隔的VCSEL和光电检测器,可用于需要独立操作的应用
    • US06835992B1
    • 2004-12-28
    • US09484348
    • 2000-01-18
    • Stanley E. SwirhunJeffrey W. Scott
    • Stanley E. SwirhunJeffrey W. Scott
    • H01L3106
    • H01S5/0264H01S5/02208H01S5/02244H01S5/02248H01S5/02284H01S5/0262H01S5/06226H01S5/183H01S5/18388Y10S148/095Y10S148/128
    • A monolthically integrated VCSEL and photodetector, and a method of manufacturing same, are disclosed for applications where the VCSEL and photodetector require separate operation such as duplex serial data communications applications. A first embodiment integrates a VCSEL with an MSM photodetector on a semi-insulating substrate. A second embodiment builds the layers of a p-i-n photodiode on top of layers forming a VCSEL using a standard VCSEL process. The p-i-n layers are etched away in areas where VCSELs are to be formed and left where the photodetectors are to be formed. The VCSELs underlying the photodetectors are inoperable, and serve to recirculate photons back into the photodetector not initially absorbed. The transmit and receive pairs are packaged in a single package for interface to multifiber ferrules. The distance between the devices is precisely defined photolithographically, thereby making alignment easier.
    • 公开了一种单分布式VCSEL和光电检测器及其制造方法,其中VCSEL和光电探测器需要单独的操作,例如双工串行数据通信应用。 第一实施例将VCSEL与半绝缘衬底上的MSM光电检测器集成。 第二实施例使用标准VCSEL工艺在形成VCSEL的层的顶部上构建p-i-n光电二极管的层。 在要形成VCSEL的区域中蚀刻掉p-i-n层,并留在要形成光电探测器的位置。 光电探测器下面的VCSEL是不可操作的,并且用于将光子再循环回到初始被吸收的光电探测器中。 发送和接收对被封装在单个封装中,用于与多光纤套圈的接口。 设备之间的距离是光刻的精确定义,从而使对准更容易。